MC74VHC1GT126 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs http://onsemi.com MARKING DIAGRAMS 5 5 1 SC−88A/SOT−353/SC−70 DF SUFFIX CASE 419A M The MC74VHC1GT126 is a single gate noninverting 3−state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC1GT126 requires the 3−state control input (OE) to be set Low to place the output into the high impedance state. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V CMOS Logic while operating at the high−voltage power supply. The MC74VHC1GT126 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1GT126 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. W3 M G G 1 5 W3 M G G 5 1 TSOP−5/SOT−23/SC−59 DT SUFFIX CASE 483 1 Features • • • • • • • • • W3 M G High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load = Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 62; Equivalent Gates = 16 Pb−Free Packages are Available OE 1 IN A 2 GND 3 PIN ASSIGNMENT 1 OE 2 IN A 3 GND 4 OUT Y 5 VCC 5 VCC FUNCTION TABLE 4 OUT Y Figure 1. Pinout (Top View) A Input OE Input Y Output L H X H H L L H Z OE OUT Y IN A ORDERING INFORMATION Figure 2. Logic Symbol © Semiconductor Components Industries, LLC, 2007 February, 2007 − Rev. 13 See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. 1 Publication Order Number: MC74VHC1GT126/D MC74VHC1GT126 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage Characteristics −0.5 to +7.0 V VIN DC Input Voltage −0.5 to +7.0 V VOUT DC Output Voltage −0.5 to VCC + 0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current +20 mA IOUT DC Output Current, per Pin +25 mA ICC DC Supply Current, VCC and GND +50 mA PD Power Dissipation in Still Air SC−88A, TSOP−5 200 mW qJA Thermal Resistance SC−88A, TSOP−5 333 °C/W TL Lead Temperature, 1 mm from Case for 10 s 260 °C TJ Junction Temperature Under Bias +150 °C Tstg Storage Temperature −65 to +150 °C > 2000 > 200 N/A V ±500 mA VESD VOUT < GND; VOUT > VCC ESD Withstand Voltage ILatchup Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Latchup Performance Above VCC and Below GND at 125°C (Note 4) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22−A114−A 2. Tested to EIA/JESD22−A115−A 3. Tested to JESD22−C101−A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit VCC DC Supply Voltage 3.0 5.5 V VIN DC Input Voltage 0.0 5.5 V VOUT DC Output Voltage 0.0 VCC V TA Operating Temperature Range −55 +125 °C tr, tf Input Rise and Fall Time 0 20 ns/V VCC = 5.0 V ± 0.5 V 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80° C 117.8 TJ = 90 ° C 1,032,200 TJ = 100° C 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110° C Time, Years TJ = 120° C Time, Hours TJ = 130° C Junction Temperature °C NORMALIZED FAILURE RATE Device Junction Temperature versus Time to 0.1% Bond Failures 1 1 10 100 1000 TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 MC74VHC1GT126 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ DC ELECTRICAL CHARACTERISTICS Symbol VIH Parameter Minimum High−Level Input Voltage VIL Maximum Low−Level Input Voltage VOH Minimum High−Level Output Voltage VIN = VIH or VIL VOL Maximum Low−Level Output Voltage VIN = VIH or VIL Test Conditions TA ≤ 85°C TA = 25°C VCC (V) Min 3.0 4.5 5.5 1.4 2.0 2.0 Typ Max Min 3.0 4.5 5.5 0.53 0.8 0.8 VIN = VIH or VIL IOH = − 50 mA 3.0 4.5 2.9 4.4 VIN = VIH or VIL IOH = − 4 mA IOH = − 8 mA 3.0 4.5 2.58 3.94 VIN = VIH or VIL IOL = 50 mA 3.0 4.5 VIN = VIH or VIL IOL = 4 mA IOL = 8 mA Max 1.4 2.0 2.0 3.0 4.5 0.0 0.0 −55 ≤ TA ≤ 125°C Min Max Unit V 0.53 0.8 0.8 V 1.4 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.9 4.4 2.48 3.80 2.34 3.66 V 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 1.0 20 40 mA ICCT Quiescent Supply Current Input: VIN = 3.4 V Other Input: VCC or GND 5.5 1.35 1.50 1.65 mA IOPD Output Leakage Current VOUT = 5.5 V 0.0 0.5 5.0 10 mA Maximum 3−State Leakage Current VIN = VIH or VIL VOUT = VCC or GND 5.5 ± 0.25 ± 2.5 ± 2.5 mA IOZ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns TA ≤ 85°C TA = 25°C Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ Typ Max Min Max 5.6 8.1 8.0 11.5 1.0 1.0 9.5 13.0 12.0 16.0 CL = 15pF CL = 50pF 3.8 5.3 5.5 7.5 1.0 1.0 6.5 8.5 8.5 10.5 VCC = 3.3 ± 0.3 V RL = RI = 500 W CL = 15pF CL = 50pF 5.4 7.9 8.0 11.5 1.0 1.0 9.5 13.0 11.5 15.0 VCC = 5.0 ± 0.5 V RL = RI = 500 W CL = 15pF CL = 50pF 3.6 5.1 5.1 7.1 1.0 1.0 6.0 8.0 7.5 9.5 VCC = 3.3 ± 0.3 V RL = RI = 500 W CL = 15pF CL = 50pF 6.5 8.0 9.7 13.2 1.0 1.0 11.5 15.0 14.5 18.0 VCC = 5.0 ± 0.5 V RL = RI = 500 W CL = 15pF CL = 50pF 4.8 7.0 6.8 8.8 1.0 1.0 8.0 10.0 10.0 12.0 10 10 10 Parameter Maximum Propagation Delay, A to Y (Figures 3 and 5) Test Conditions VCC = 3.3 ± 0.3 V CL = 15pF CL = 50pF VCC = 5.0 ± 0.5 V Maximum Output Enable TIme,OE to Y (Figures 4 and 5) Maximum Output Disable Time,OE to Y (Figures 4 and 5) Min −55 ≤ TA ≤ 125°C Cin Maximum Input Capacitance 4 Cout Maximum Three−State Output Capacitance (Output in High Impedance State) 6 Min Max Unit ns ns ns pF pF Typical @ 25°C, VCC = 5.0 V CPD 14 Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 3 MC74VHC1GT126 SWITCHING WAVEFORMS VCC 50% A OE GND tPZL GND tPHL tPLH VCC 50% tPZH Y VOL + 0.3V tPHZ VOH − 0.3V 50% VCC Y Figure 4. Switching Waveforms HIGH IMPEDANCE Figure 5. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST HIGH IMPEDANCE 50% VCC Y 50% VCC tPLZ DEVICE UNDER TEST C L* *Includes all probe and jig capacitance OUTPUT 1 kW CL * CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 6. Test Circuit Figure 7. Test Circuit INPUT Figure 8. Input Equivalent Circuit ORDERING INFORMATION Device Package MC74VHC1GT126DF1 SC−88A / SOT−353 / SC−70 M74VHC1GT126DF1G SC−88A / SOT−353 / SC−70 (Pb−Free) MC74VHC1GT126DF2 SC−88A / SOT−353 / SC−70 M74VHC1GT126DF2G SC−88A / SOT−353 / SC−70 (Pb−Free) MC74VHC1GT126DT1 TSOP−5 / SOT−23 / SC−59 M74VHC1GT126DT1G TSOP−5 / SOT−23 / SC−59 (Pb−Free) Shipping † 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74VHC1GT126 PACKAGE DIMENSIONS SC−88A, SOT−353, SC−70 CASE 419A−02 ISSUE J A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) M B M N INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC −−− 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 J C K H SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 mm Ǔ ǒinches MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC −−− 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 MC74VHC1GT126 PACKAGE DIMENSIONS TSOP−5 CASE 483−02 ISSUE F NOTE 5 2X 0.10 T 2X 0.20 T NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X 0.20 C A B 5 1 4 2 3 M B S K L DETAIL Z G A DIM A B C D G H J K L M S DETAIL Z J C 0.05 SEATING PLANE H T MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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