ONSEMI NLSF308

NLSF308
Quad 2−Input AND Gate
The NLSF308 is an advanced high speed CMOS 2−input AND gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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Features
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High Speed: tPD = 4.3 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Function Compatible with Other Standard Logic Families
QFN−16 Package
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V;
Machine Model; > 200 V
Chip Complexity: 24 FETs or 6 Equivalent Gates
Pb−Free Package is Available*
FUNCTION TABLE
Inputs
B
Y
L
L
H
H
L
H
L
H
L
L
L
H
MARKING DIAGRAM
ÇÇÇ
ÇÇÇ
ÇÇÇ
16
1
NLSF
308
ALYW G
G
NLSF308 = Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Output
A
QFN−16
MN SUFFIX
CASE 485G
ORDERING INFORMATION
Device
NLSF308MNR2
NLSF308MNR2G
Package
Shipping†
QFN−16
3000 / Tape & Reel
QFN−16
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 4
1
Publication Order Number:
NLSF308/D
NLSF308
B2
A3
B3
14
13
12 A4
1
15
1
16
Y1
NC
2
A2
3
B2
4
NLSF308
MN Package
11 NC
3
5
4
Y2
10 Y4
(Top View)
Y = AB
8
7
9
10
B3
Figure 1. LOGIC DIAGRAM
5
6
7
8
A3
Y4
Y3
12
13
9
Y3
GND
B4
15
Y2
A4
B4
A2
VCC
B1
A1
A1
B1
Y1
16
Figure 2. PIN ASSIGNMENT (QFN−16)
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MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
DC Supply Voltage
VCC
–0.5 to + 7.0
V
DC Input Voltage
Vin
–0.5 to + 7.0
V
DC Output Voltage
Vout
–0.5 to VCC + 0.5
V
Input Diode Current
IIK
−20
mA
Output Diode Current
IOK
±20
mA
DC Output Current, per Pin
Iout
±25
mA
DC Supply Current, VCC and GND Pins
ICC
±50
mA
Power Dissipation in Still Air
PD
450
mW
Storage Temperature
Tstg
–65 to + 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
DC Supply Voltage
VCC
2.0
5.5
V
DC Input Voltage
Vin
0
5.5
V
DC Output Voltage
Vout
0
VCC
V
TA
−40
+ 85
°C
tr, tf
0
0
100
20
ns/V
Operating Temperature
Input Rise and Fall Time
VCC = 3.3 V ±0.3 V
VCC = 5.0 V ±0.5 V
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2
NLSF308
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DC ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Symbol
TA = 25°C
VCC
V
Min
1.50
VCC x 0.7
Minimum High−Level Input
Voltage
VIH
2.0
3.0 to 5.5
Maximum Low−Level Input
Voltage
VIL
2.0
3.0 to 5.5
VOH
2.0
3.0
4.5
1.9
2.9
4.4
3.0
4.5
2.58
3.94
Minimum High−Level Output
Voltage
Vin = VIH or VIL
IOH = −50 mA
Vin = VIH or VIL
IOH = −4 mA,
IOH = −8 mA
Maximum Low−Level Output
Voltage
VOL
Vin = VIH or VIL
IOL = 50 mA
Max
Min
Max
1.50
VCC x 0.7
0.50
VCC x 0.3
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Typ
TA = − 40 to 85°C
V
0.50
VCC x 0.3
2.0
3.0
4.5
Unit
V
V
1.9
2.9
4.4
2.48
3.80
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
V
Maximum Input Leakage Current
Vin = 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
mA
Maximum Quiescent Supply
Current
Vin = VCC or GND
5.5
2.0
20.0
mA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
Parameter
Test Conditions
Symbol
Maximum Propagation Delay, A or B to Y
VCC = 3.3 ± 0.3 V, CL = 15 pF,
CL = 50 pF
tPLH,
tPHL
VCC = 5.0 ± 0.5 V, CL = 15 pF,
CL = 50 pF
Maximum Input Capacitance
Cin
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
6.2
8.7
8.8
12.3
1.0
1.0
10.5
14.0
ns
4.3
5.8
5.9
7.9
1.0
1.0
7.0
9.0
4
10
10
pF
Typical @ 25°C, VCC = 5.0 V
Power Dissipation Capacitance (Note 1)
18
CPD
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25°C
Symbol
Typ
Max
Unit
Quiet Output Maximum Dynamic VOL
VOLP
0.3
0.8
V
Quiet Output Minimum Dynamic VOL
VOLV
−0.3
−0.8
V
Minimum High Level Dynamic Input Voltage
VIHD
3.5
V
Maximum Low Level Dynamic Input Voltage
VILD
1.5
V
Characteristic
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3
NLSF308
VCC
A or B
50%
GND
tPLH
Y
tPHL
50% VCC
Figure 3. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL *
*Includes all probe and jig capacitance
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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4
NLSF308
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
D
PIN 1
LOCATION
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
A
B
ÇÇ
ÇÇ
ÇÇ
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
0.15 C
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
SEATING
PLANE
A1
C
D2
16X
e
L
5
NOTE 5
EXPOSED PAD
8
4
9
E2
16X
K
12
1
16
16X
13
b
0.10 C A B
0.05 C
e
BOTTOM VIEW
NOTE 3
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NLSF308/D