NLSF3T125 Quad Bus Buffer with 3−State Control Inputs The NLSF3T125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The NLSF3T125 requires the 3−state control input (OE) to be set High to place the output into the high impedance state. The T125 inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The NLSF3T125 input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • • • • • • • • • • • • High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model; > 2000 V, Machine Model; > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant http://onsemi.com 1 QFN−16 CASE 485G MARKING DIAGRAM NLSF3 T125 ALYWG G NLSF3T125 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NLSF3T125MNR2G QFN−16 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. FUNCTION TABLE NLSF3T125 Inputs Output A OE Y H L H L L L X H Z © Semiconductor Components Industries, LLC, 2011 June, 2011 − Rev. 5 1 Publication Order Number: NLSF3T125/D NLSF3T125 Active−Low Output Enables 16 A1 1 Y1 15 OE1 5 4 A2 Y2 3 OE2 7 8 A3 Y3 9 OE3 10 12 A4 Y4 13 OE4 Figure 1. Logic Diagram OE1 VCC A1 16 15 14 OE4 Exposed Pad (EP) 13 Y1 1 12 A4 NC 2 11 NC OE2 3 10 Y4 A2 4 9 5 6 Y2 7 GND Y3 OE3 8 A3 Figure 2. QFN − 16 Pinout (Top View) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Units VCC DC Supply Voltage −0.5 to +7.0 V Vin DC Input Voltage –0.5 to +7.0 V Vout DC Output Voltage Output in 3−State High or Low State –0.5 to +7.0 –0.5 to VCC + 0.5 IIK Input Diode Current −20 mA IOK Output Diode Current (VOUT < GND; VOUT > VCC) ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air QFN Packages 500 Tstg Storage Temperature –65 to +150 V mW °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. NLSF3T125 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Units 2.0 5.5 V DC Input Voltage 0 5.5 V DC Output Voltage Output in 3−State High or Low State 0 0 5.5 VCC −40 +85 VCC DC Supply Voltage Vin Vout TA Operating Temperature tr, tf Input Rise and Fall Time VCC = 5.0 V ±0.5 V 0 V °C ns/V 20 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions VCC (V) TA = 25°C Min VIH Minimum High−Level Input Voltage 2.3 V ± 0.3 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V VIL Maximum Low−Level Input Voltage 2.3 V ± 0.3 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V VOH Minimum High−Level Output Voltage VIN = VIH or VIL VOL @ IOL, 50 mA VIN = VIH or VIL IOH = −50 mA 2.0 3.0 4.5 1.9 2.9 4.4 VIN = VIH or VIL IOH = −2.0 mA IOH = −4.0 mA IOH = −8.0 mA 2.0 3.0 4.5 1.82 2.58 3.94 VOL @ IOL, 50 mA VIN = VIH or VIL IOL = 50 mA 2.0 3.0 4.5 VIN = VIH or VIL IOL = 2.0 mA IOL = 4.0 mA IOL = 8.0 mA VOL Maximum Low−Level Output Voltage VIN = VIH or VIL Typ TA 3 85°C Max 0.5 VCC 0.4 VCC 0.44 VCC Min Max 0.5 VCC 0.4 VCC 0.44 VCC 0.3 VCC 0.18 VCC 0.18 VCC 2.0 3.0 4.5 0.0 0.0 0.0 TA 3 125°C Min Max 0.5 VCC 0.4 VCC 0.44 VCC 0.3 VCC 0.18 VCC 0.18 VCC V 0.3 VCC 0.18 VCC 0.18 VCC 1.9 2.9 4.4 1.9 2.9 4.4 1.72 2.48 3.80 1.60 2.34 3.66 Units V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 2.0 3.0 4.5 0.36 0.36 0.36 0.44 0.44 0.44 0.52 0.52 0.52 V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 2.0 20 40 mA ICCT Quiescent Supply Current Input: VIN = 3.4 V 5.5 1.35 1.50 1.65 mA IOZ Maximum 3−State Leakage Current VIN = VIH or VIL VOUT = VCC or GN D 5.5 ±0.25 ±2.5 ±2.5 mA IOPD Output Leakage Current VOUT = 5.5 V 0.0 0.5 5.0 10 mA http://onsemi.com 3 NLSF3T125 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25°C Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ tOSLH, tOSHL Parameter Maximum Propagation Delay, A to Y Maximum Output Enable TIme, OE to Y Maximum Output Disable Time, OE to Y Output−to−Output Skew Test Conditions TA 3 85°C TA 3 125°C Min Typ Max Min Max Min Max Units VCC = 2.3 ± 0.3 V CL = 15 pF 1.0 14.5 16.9 1.0 18.1 1.0 19.2 ns VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 1.0 1.0 5.6 8.1 8.0 11.5 1.0 1.0 9.5 13.0 1.0 1.0 12.0 16.0 ns VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 1.0 1.0 3.8 5.3 5.5 7.5 1.0 1.0 6.5 8.5 1.0 1.0 8.5 10.5 VCC = 2.3 ± 0.3 V CL = 15 pF 1.0 14.8 16.2 1.0 17.4 1.0 19.3 ns VCC = 3.3 ± 0.3 V RL = 1.0 kW CL = 15 pF CL = 50 pF 1.0 1.0 5.4 7.9 8.0 11.5 1.0 1.0 9.5 13.0 1.0 1.0 11.5 15.0 ns VCC = 5.0 ± 0.5 V RL = 1.0 kW CL = 15 pF CL = 50 pF 1.0 1.0 3.6 5.1 5.1 7.1 1.0 1.0 6.0 8.0 1.0 1.0 7.5 9.5 VCC = 2.3 ± 0.3 V CL = 15 pF 1.0 15.4 18.0 1.0 19.8 1.0 22.0 ns VCC = 3.3 ± 0.3 V RL = 1.0 kW CL = 50 pF 1.0 9.5 13.2 1.0 15.0 1.0 18.0 ns VCC = 5.0 ± 0.5 V RL = 1.0 kW CL = 50 pF 1.0 6.1 8.8 1.0 10.0 1.0 12.0 ns VCC = 3.3 ± 0.3 V (Note 1) CL = 50 pF 1.5 1.5 2.0 ns VCC = 5.0 ± 0.5 V (Note 1) CL = 50 pF 1.0 1.0 1.5 10 10 10 Cin Maximum Input Capacitance 4 Cout Maximum Three−State Output Capacitance (Output in High Impedance State) 6 CPD Power Dissipation Capacitance (Note 2) pF pF Typical @ 25°C, VCC = 5.0V 15 pF 1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25°C Symbol Typ Characteristic Max Units VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V VOLV Quiet Output Minimum Dynamic VOL −0.3 −0.8 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V http://onsemi.com 4 NLSF3T125 SWITCHING WAVEFORMS 3.0V OE 1.5V 3.0V GND 1.5V A tPZL GND tPHL tPLH Y tPZH VOL VOL + 0.3V tPHZ VOH - 0.3V 1.5V Y Figure 3. HIGH IMPEDANCE Figure 4. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST HIGH IMPEDANCE 1.5V Y VOH 1.5V tPLZ DEVICE UNDER TEST CL* *Includes all probe and jig capacitance OUTPUT 1 kW CL * CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 5. Test Circuit Figure 6. Test Circuit http://onsemi.com 5 NLSF3T125 PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G−01 ISSUE F D ÇÇÇ ÇÇÇ ÇÇÇ PIN 1 LOCATION 2X A B L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉ ÉÉ EXPOSED Cu 0.10 C TOP VIEW DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 0.10 C 2X L (A3) A3 A1 DETAIL B A 0.05 C ÉÉ ÉÉ ÇÇ MOLD CMPD ALTERNATE CONSTRUCTIONS NOTE 4 A1 SIDE VIEW C 16X L RECOMMENDED SOLDERING FOOTPRINT* D2 8 4 16X MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.18 0.24 0.30 3.00 BSC 1.65 1.75 1.85 3.00 BSC 1.65 1.75 1.85 0.50 BSC 0.18 TYP 0.30 0.40 0.50 0.00 0.08 0.15 SEATING PLANE 0.10 C A B DETAIL A DIM A A1 A3 b D D2 E E2 e K L L1 16X 0.58 PACKAGE OUTLINE 9 1 E2 K 2X 2X 1.84 3.30 1 16 e e/2 BOTTOM VIEW 16X b 16X 0.30 0.10 C A B 0.05 C 0.50 PITCH NOTE 3 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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