ONSEMI NTTFS4821NTWG

NTTFS4821N
Power MOSFET
30 V, 57 A, Single N−Channel, m8FL
Features
•
•
•
•
Small Footprint (3.3 x 3.3 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
This is a Pb−Free Device
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V(BR)DSS
RDS(on) MAX
Applications
7.0 mW @ 10 V
30 V
• DC−DC Converters
• High Side Switching
Symbol
N−Channel MOSFET
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
13.5
A
Continuous Drain
Current RqJA (Note 1)
TA = 25°C
Power Dissipation RqJA
(Note 1)
TA = 25°C
PD
2.1
W
Continuous Drain
Current RqJA ≤ 10 s
(Note 1)
TA = 25°C
ID
18.6
A
Power Dissipation
RqJA ≤ 10 s (Note 1)
TA = 25°C
PD
4.1
W
TC = 25°C
ID
7.5
A
Continuous Drain
Current RqJA (Note 2)
TA = 85°C
9.7
TA = 85°C
Steady
State
13.4
TC = 85°C
5.4
TC = 25°C
PD
0.66
W
Continuous Drain
Current RqJC (Note 1)
TC = 25°C
ID
57
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
38.5
W
TA = 25°C, tp = 10 ms
IDM
171
A
TA = 25°C
IDmaxPkg
90
A
TJ,
Tstg
−55 to
+150
°C
IS
38.5
A
dV/dt
6.0
V/ns
EAS
55
mJ
Pulsed Drain Current
Current Limited by Pkg.
Operating Junction and Storage Temperature
Source Current (Body Diode)
Drain to Source DV/DT
Single Pulse Drain−to−Source Avalanche Energy
(TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 33 Apk, L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
41
TL
260
D (5−8)
G (4)
S (1,2,3)
MARKING DIAGRAM
1
S
S
S
G
1
Power Dissipation
RqJA (Note 2)
TC = 85°C
57 A
10.8 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
ID MAX
°C
WDFN8
(m8FL)
CASE 511AB
FLAT LEAD
4821
A
Y
WW
G
4821
AYWWG
G
D
D
D
D
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
NTTFS4821NTAG
WDFN8 1500/Tape & Reel
(Pb−Free)
NTTFS4821NTWG
WDFN8 5000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2009
June, 2009 − Rev. 3
1
Publication Order Number:
NTTFS4821N/D
NTTFS4821N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
3.25
°C/W
Junction−to−Ambient – Steady State (Note 3)
RqJA
58.3
Junction−to−Ambient – Steady State (Note 4)
RqJA
188.4
Junction−to−Ambient – (t ≤ 10 s) (Note 3)
RqJA
30.6
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
25
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
gFS
1.9
6
VGS = 10 V to 11.5 V
VGS = 4.5 V
Forward Transconductance
1.5
ID = 20 A
5.8
ID = 10 A
5.7
ID = 20 A
8.8
ID = 10 A
8.6
VDS = 15 V, ID = 30 A
mV/°C
7.0
mW
10.8
53
S
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
1300
1755
Output Capacitance
Coss
300
405
Reverse Transfer Capacitance
Crss
150
233
Total Gate Charge
QG(TOT)
10.5
15
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V, ID = 30 A
pF
nC
1.3
3.9
4.5
VGS = 11.5 V, VDS = 15 V, ID = 20 A
24
nC
12
ns
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
22
16
4.5
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NTTFS4821N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
ns
8.5
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
20
23
2.8
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.9
TJ = 125°C
0.78
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 20 A
1.0
ns
9.0
VGS = 0 V,
dIS/dt = 100 A/ms,
IS = 20 A
V
6.5
2.5
QRR
1.7
nC
Source Inductance
LS
0.38
nH
Drain Inductance
LD
Gate Inductance
LG
Gate Resistance
RG
PACKAGE PARASITIC VALUES
TA = 25°C
0.054
1.3
0.6
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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3
2.0
W
NTTFS4821N
TYPICAL CHARACTERISTICS
90
10 V
80
70
ID, DRAIN CURRENT (A)
VGS = 4.5 V
5.0 V
4.0 V
7.0 V
60
3.8 V
50
3.6 V
40
3.4 V
30
20
3.2 V
60
50
40
30
0
1
2
3
4
5
6
1
TJ = −55°C
2
3
4
5
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.013
0.012
0.011
0.010
0.009
0.008
0.007
0.006
0.005
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
6
0.015
TJ = 25°C
0.013
0.011
0.009
VGS = 4.5 V
0.007
VGS = 10 V
0.005
0.003
20
40
30
50
60
70
80
90
100
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
1.8
ID = 20 A
VGS = 10 V
VGS = 0 V
IDSS, LEAKAGE (nA)
1.6
0
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 20 A
TJ = 25°C
3
TJ = 25°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.014
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = 100°C
20
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
TJ = 25°C
0.015
0.004
70
10
10
0
VDS ≥ 10 V
80
4.2 V
ID, DRAIN CURRENT (A)
90
1.4
1.2
1
TJ = 150°C
1000
TJ = 125°C
100
0.8
0.6
−50
−25
0
25
50
75
100
125
150
10
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTTFS4821N
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
1800
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
2000
1600
Ciss
1400
1200
1000
800
600
Coss
400
200
0
Crss
0
5
10
15
20
25
30
10
8
6
VGS
4
Qgs
Qgd
2
0
ID = 30 A
TJ = 25°C
0
4
8
12
16
20
24
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
30
IS, SOURCE CURRENT (A)
VDD = 15 V
ID = 15 A
VGS = 10 V
td(off)
tf
100
t, TIME (ns)
QT
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
1000
tr
10
1
td(on)
1
10
15
10
5
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
75
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
0.01
20
RG, GATE RESISTANCE (W)
10 ms
100 ms
10
0.1
VGS = 0 V
TJ = 25°C
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
100
1
25
0
0.2
100
1000
ID, DRAIN CURRENT (A)
12
1 ms
10 ms
VGS = 20 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
dc
10
100
ID = 33 A
50
25
0
25
50
75
100
125
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE(°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
150
NTTFS4821N
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB−01
ISSUE B
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
0.20 C
D
A
D1
B
2X
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
0.20 C
8 7 6 5
4X
E1 E
1 2 3 4
q
c
TOP VIEW
A1
0.10 C
A
0.10 C
e
SIDE VIEW
0.10
8X b
C A B
0.05
c
L
C
6X
DETAIL A
SEATING
PLANE
DETAIL A
INCHES
NOM
0.030
−−−
0.012
0.008
0.130 BSC
0.116
0.120
0.078
0.083
0.130 BSC
0.116
0.120
0.058
0.063
0.026 BSC
0.012
0.016
0.025
−−−
0.012
0.017
0.002
0.005
0.055
0.059
0_
−−−
MIN
0.028
0.000
0.009
0.006
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.020
−−−
0.022
0.008
0.063
12 _
SOLDERING FOOTPRINT*
8X
0.42
e/2
1
4
E2
0.65
PITCH
PACKAGE
OUTLINE
K
4X
0.66
M
8
G
MILLIMETERS
MIN
NOM
MAX
0.70
0.75
0.80
0.00
−−−
0.05
0.23
0.30
0.40
0.15
0.20
0.25
3.30 BSC
2.95
3.05
3.15
1.98
2.11
2.24
3.30 BSC
2.95
3.05
3.15
1.47
1.60
1.73
0.65 BSC
0.30
0.41
0.51
0.64
−−−
−−−
0.30
0.43
0.56
0.06
0.13
0.20
1.40
1.50
1.60
0_
−−−
12 _
5
D2
L1
3.60
BOTTOM VIEW
0.75
2.30
0.57
0.47
2.37
3.46
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTTFS4821N/D