NB7V585M 1.8V / 2.5V Differential 2:1 Mux Input to 1:6 CML Clock/Data Fanout Buffer/Translator Multi−Level Inputs w/ Internal Termination http://onsemi.com Description The NB7V585M is a differential 1−to−6 CML clock/data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels (see Figure 9). The NB7V585M produces six identical output copies of clock or data operating up to 6 GHz or 10 Gb/s, respectively. As such, NB7V585M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. The 16 mA differential CML output structure provides matching internal 50 W source terminations, 400 mV output swings when externally terminated with a 50 W resistor to VCC (see Figure 14) and is optimized for low skew and minimal jitter. The NB7V585M is powered with either 1.8 V or 2.5 V supply and is offered in a low profile 5x5 mm 32−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7V585M is a member of the GigaComm™ family of high performance clock products. MARKING DIAGRAM* 1 Maximum Input Data Rate > 10 Gb/s Data Dependent Jitter < 10 ps Maximum Input Clock Frequency > 6 GHz Random Clock Jitter < 0.8 ps RMS, Max Low Skew 1:6 CML Outputs, 20 ps Max 2:1 Multi−Level Mux Inputs 175 ps Typical Propagation Delay 50 ps Typical Rise and Fall Times Differential CML Outputs, 330 mV Peak−to−Peak, Typical Operating Range: VCC = 1.71 V to 1.89 V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN32 Package, 5 mm x 5 mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices 32 1 A WL YY WW G NB7V 585M AWLYYWW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. SIMPLIFIED LOGIC DIAGRAM Features • • • • • • • • • • • • • • • QFN32 MN SUFFIX CASE 488AM VCC Q0 Q0 Q1 Q1 SEL VREFAC0 IN0 VT0 IN0 0 IN1 VT1 1 IN1 VREFAC1 Q2 Q2 Q3 Q3 Q4 Q4 VCC GND Q5 Q5 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2009 February, 2009 − Rev. 1 1 Publication Order Number: NB7V585M/D 32 31 30 Table 1. INPUT SELECT FUNCTION TABLE 29 28 27 26 VCC Q1 Q1 Q0 Exposed Pad (EP) Q0 VCC SEL GND NB7V585M 25 IN0 1 24 GND VT0 2 23 VCC VREFAC0 3 22 Q2 IN0 4 21 Q2 IN1 5 20 Q3 VT1 6 19 Q3 VREFAC1 7 18 VCC IN1 8 17 SEL* CLK Input Selected 0 IN0 1 IN1 *Defaults HIGH when left open. 14 15 16 VCC Q5 13 Q4 12 Q4 11 Q5 10 VCC GND 9 NC NB7V585M GND Figure 1. 32−Lead QFN Pinout (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1,4 5,8 IN0, IN0 IN1, IN1 LVPECL, CML, LVDS Input 2,6 VT0, VT1 31 SEL LVTTL/LVCMOS Input 10 NC − No Connect 11, 16, 18 23, 25, 30 VCC − Positive Supply Voltage. 29, 28 27, 26 Q0, Q0 Q1, Q1 CML Output Non−inverted, Inverted Differential Outputs (Note 1). 22, 21 20, 19 Q2, Q2 Q3, Q3 CML Output Non−inverted, Inverted Differential Outputs (Note 1). 15, 14 13, 12 Q4, Q4 Q5, Q5 CML Output Non−inverted, Inverted Differential Outputs (Note 1). 9, 17, 24, 32 GND 3 7 VREFAC0 VREFAC1 − Output Voltage Reference for Capacitor−Coupled Inputs, only − EP − The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. Non−inverted, Inverted, Differential Inputs Internal 100 W Center−tapped Termination Pin for IN0/IN0 and IN1/IN1 Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open Negative Supply Voltage, connected to Ground 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INn/INn input, then, the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50 W source termination resistors. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB7V585M Table 3. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model > 4 kV > 200 V Input Pullup Resistor (RPU) 75 kW Moisture Sensitivity (Note 3) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 308 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 3.0 V −0.5 to VCC + 0.5 V VCC Positive Power Supply GND = 0 V VIO Input/Output Voltage GND = 0 V VINPP Differential Input Voltage |INx − INx| 1.89 V IIN Input Current Through RT (50 W Resistor) $40 mA IOUT Output Current 34 40 mA IVFREFAC VREFAC Sink/Source Current $1.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 4) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 4) Standard Board QFN−32 12 °C/W Tsol Wave Solder 265 °C −0.5 v VIO v VCC + 0.5 Continuous Surge Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7V585M Table 5. DC CHARACTERISTICS − CML OUTPUT VCC = 1.8 V $5% or 2.5 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 5) Symbol Characteristic Min Typ Max 235 210 260 Unit POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) VCC = 2.65 V VCC = 1.89 V mA CML OUTPUTS (Note 6) VOH Output HIGH Voltage VOL Output LOW Voltage VCC = 2.5 V VCC = 1.8 V VCC – 40 2460 1760 VCC – 20 2480 1780 VCC 2500 1800 mV VCC = 2.5 V VCC = 1.8 V VCC – 500 2000 1300 VCC – 400 2100 1400 VCC – 275 2200 1500 mV 1050 VCC − 100 mV DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figure 6) Vth Input Threshold Reference Voltage Range (Note 8) VIH Single−Ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−Ended Input LOW Voltage GND Vth − 100 mV VISE Single−Ended Input Voltage (VIH − VIL) 200 1200 mV VCC − 400 mV VREFAC VREFAC Output Reference Voltage @ 100 mA for Capacitor − Coupled Inputs, Only VCC − 625 VCC − 500 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 9) (Figures 4 and 7) VIHD Differential Input HIGH Voltage (IN, IN) 1100 VCC mV VILD Differential Input LOW Voltage (IN, IN) GND VCC − 100 mV VID Differential Input Voltage (IN, IN) (VIHD − VILD) 100 1200 mV VCMR Input Common Mode Range (Differential Configuration, Note 10) (Figure 9) 1050 VCC − 50 mV IIH Input HIGH Current IN/IN (VTO / VT1 Open) −150 150 mA IIL Input LOW Current IN/IN (VTO / VT1 Open) −150 150 mA CONTROL INPUT (SEL Pin) VIH Input HIGH Voltage for Control Pin VCC x 0.65 VCC mV VIL Input LOW Voltage for Control Pin GND VCC x 0.35 mV IIH Input HIGH Current −150 20 +150 mA IIL Input LOW Current −150 5 +150 mA TERMINATION RESISTORS RTIN Internal Input Termination Resistor (Measured from INx to VTx) 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. CML outputs (Qn/Qn) have internal 50 W source termination resistors and must be externally terminated with 50 W to VCCO for proper operation. 7. Vth, VIH, VIL and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB7V585M Table 6. AC CHARACTERISTICS VCC = 1.8 V $5% or 2.5 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 11) Symbol Min Typ fMAX Maximum Input Clock Frequency, VOUTPP w 200 mV Characteristic 6.0 7.0 fDATAMAX Maximum Operating Input Data Rate (PRBS23) 10 VOUTPP Output Voltage Amplitude (See Figures 4, Note 15) fin v 4.0 GHz fin v 6.0 GHz 250 200 400 325 tPLH, tPHL Propagation Delay to Output Differential @ 1 GHz, Measured at Differential Crosspoint INx/INx to Qn/Qn SEL to Qn 125 175 200 tPLH TC Propagation Delay Temperature Coefficient tSKEW Output − Output Skew (Within Device) (Note 12) Device − Device Skew (tpd Max − tpdmin) tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 4.0 GHz tJITTER Output Random Jitter (RJ) (Note 13) Deterministic Jitter (DJ) (Note 14) VINPP Input Voltage Swing (Differential Configuration) (Note 15) tr, tf Output Rise/Fall Times @ 1 GHz (20% − 80%) Max Gbps mV 250 300 100 45 ps 50 55 % 0.2 0.8 10 ps rms ps pk−pk 1200 mV 65 ps 100 Qn, Qn ps fs/°C 30 50 fin v 6.0 GHz fin v 10 Gbps Unit GHz 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50 W to VCC. Input edge rates 40 ps (20% − 80%). 12. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the crosspoint of the outputs. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23. 15. Input and output voltage swing is a single−ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 450 400 VCC 350 300 INx 50 W 250 VTx 200 150 50 W INx 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 2. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 5 Figure 3. Input Structure NB7V585M INx VID = |VIHD(IN) − VILD(IN)| INx Qn VIHD INx VINPP = VIH(INx) − VIL(INx) INx VILD VOUTPP = VOH(Qn) − VOL(Qn) Qn tPHL tPLH Figure 4. Differential Inputs Driven Differentially Figure 5. AC Reference Measurement INx INx INx INx Vth Vth Figure 6. Differential Input Driven Single−Ended VCC Vthmax Vth VCC VIHmax VILmax IN Vthmin GND Figure 7. Differential Inputs Driven Differentially VIHDmax VCMmax VILDmax VID = VIHD − VILD VIHDtyp INx VIH Vth VIL VCMR VIHmin VILmin INx VILDtyp VIHDmin VILDmin VCMmin GND Figure 8. Vth Diagram Figure 9. VCMR Diagram NB7V585M VCCO VCC (Receiver) 50 W 50 W Q 50 W 50 W Q 16 mA GND Figure 10. Typical CML Output Structure and Termination http://onsemi.com 6 NB7V585M VCC VCC VCC ZO = 50 W LVPECL Driver VCC NB7V585M ZO = 50 W INx 50 W VT = VCC − 2 V ZO = 50 W LVDS Driver 50 W 50 W GND GND Figure 11. LVPECL Interface GND Figure 12. LVDS Interface VCC VCC VCC VCC NB7V585M ZO = 50 W INx 50 W VT = VCC ZO = 50 W Differential Driver 50 W NB7V585M INx 50 W VT = VREFAC* ZO = 50 W INx GND 50 W INx GND CML Driver INx VT = Open ZO = 50 W INx ZO = 50 W NB7V585M 50 W INx GND GND Figure 14. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) Figure 13. Standard 50 W Load CML Interface GND *VREFAC bypassed to ground with a 0.01 mF capacitor ORDERING INFORMATION Package Shipping† NB7V585MMNG QFN32 (Pb−Free) 74 Units / Rail NB7V585MMNR4G QFN32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB7V585M PACKAGE DIMENSIONS QFN32 5*5*1 0.5 P CASE 488AM−01 ISSUE O PIN ONE LOCATION 2X ÉÉ 0.15 C 2X A B D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 32 X 0.08 C C L 32 X 9 D2 SEATING PLANE A1 SIDE VIEW SOLDERING FOOTPRINT* 5.30 EXPOSED PAD 16 MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 −−− −−− 0.300 0.400 0.500 K 32 X 17 3.20 8 32 X 0.63 E2 1 24 32 3.20 25 b 0.10 C A B 32 X 5.30 e 0.05 C 32 X 0.28 BOTTOM VIEW 28 X 0.50 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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