ONSEMI NBSG14MN

NBSG14
2.5V/3.3VSiGe Differential
1:4 Clock/Data Driver with
RSECL* Outputs
*Reduced Swing ECL
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The NBSG14 is a 1−to−4 clock/data distribution chip, optimized for
ultra−low skew and jitter.
Inputs incorporate internal 50 termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are RSECL (Reduced Swing ECL),
400 mV.
•
•
•
•
•
•
•
MARKING
DIAGRAM*
SG
14
LYW
FCBGA−16
BA SUFFIX
CASE 489
Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
RSECL Output Level (400 mV Peak−to−Peak Output),
Differential Output
50 Internal Input Termination Resistors
SG14
ALYW
QFN−16
MN SUFFIX
CASE 485G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
•
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
*For further details, refer to Application Note
AND8002/D
ORDERING INFORMATION
Device
4x4 mm
FCBGA−16
100 Units/Tray
NBSG14BAR2
4x4 mm
FCBGA−16
500 / Tape & Reel
NBSG14MN
3x3 mm
QFN−16
123 Units / Rail
NBSG14MNR2
3x3 mm
QFN−16
3000 / Tape & Reel
NBSG14BAEVB
August, 2003 − Rev. 7
1
Shipping
NBSG14BA
Board
 Semiconductor Components Industries, LLC, 2003
Package
Description
NBSG14BA Evaluation Board
Publication Order Number:
NBSG14/D
NBSG14
1
A
VTCLK
B
CLK
2
3
Q3
VEE
Q3
VCC
4
VEE
Q0
Q0
VCC
16
15
14
13
Exposed Pad (EP)
Q2
Q2
VTCLK
1
CLK
2
12 Q1
11 Q1
NBSG14
C
CLK
D
VTCLK
VEE
VCC
Q0
Q0
CLK
3
10 Q2
VTCLK
4
9
Q1
Q2
Q1
Figure 1. BGA−16 Pinout (Top View)
5
6
7
8
VEE
Q3
Q3
VCC
Figure 2. QFN−16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
Description
D1
1
VTCLK
−
Internal 50 Termination pin. See Table 2.
C1
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 k to VEE and 36.5 k to VCC.
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 k to VEE.
A1
4
VTCLK
−
Internal 50 Termination Pin. See Table 2.
B2,C2
5,16
VEE
−
Negative Supply Voltage. All VEE Pins must be Externally Connected to
Power Supply to Guarantee Proper Operation.
A2*
6
Q3
RSECL Output
Inverted Differential Output 3. Typically Terminated with 50 to
VTT = VCC − 2 V*
A3*
7
Q3
RSECL Output
Noninverted Differential Output 3. Typically Terminated with 50 to
VTT = VCC − 2 V*
B3,C3
8,13
VCC
−
A4*
9
Q2
RSECL Output
Inverted Differential Output 2. Typically Terminated with 50 to
VTT = VCC − 2 V*
B4*
10
Q2
RSECL Output
Noninverted Differential Output 2. Typically Terminated with 50 to
VTT = VCC − 2 V*
C4*
11
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 to
VTT = VCC − 2 V*
D4*
12
Q1
RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50 to
VTT = VCC − 2 V*
D3*
14
Q0
RSECL Output
Inverted Differential Output 0. Typically Terminated with 50 to
VTT = VCC − 2 V*
D2*
15
Q0
RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50 to
VTT = VCC − 2 V*
N/A
−
EP
−
Positive Supply Voltage. All VCC Pins must be Externally Connected to
Power Supply to Guarantee Proper Operation.
Exposed Pad. The thermally exposed pad on package bottom (see case
drawing) must be attached to a heat−sinking conduit.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no
signal is applied then the device will be susceptible to self−oscillation.
*Devices in BGA package typically terminated with 50 to VTT = VCC−1.5 V.
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NBSG14
VCC
Q3
Q3
VTCLK
36.5 K
Q2
50 Q2
CLK
CLK
50 75 K
75 K
Q1
VTCLK
Q1
Q0
VEE
Q0
Figure 3. Logic Diagram
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK and VTCLK to VCC
LVDS
Connect VTCLK and VTCLK Together
AC−COUPLED
Bias VTCLK and VTCLK Inputs within
Common Mode Range (VIHCMR)
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An External Voltage (VTHR) should be Applied to the
Unused Differential Input. Nominal VTHR is 1.5 V for LVTTL
and VCC/2 for LVCMOS Inputs. This Voltage must be
within the VTHR Specification.
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NBSG14
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (CLK, CLK)
75 k
Internal Input Pullup Resistor (CLK)
ESD Protection
36.5 k
Human Body Model
Machine Model
> 2 kV
> 100 V
FCBGA−16
QFN−16
Level 3
Level 1
Moisture Sensitivity (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
158
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 2)
Rating
Units
VCC
Positive Power Supply
Parameter
VEE = 0 V
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage |CLK−CLK|
VCC − VEE 2.8 V
VCC − VEE < 2.8 V
2.8
|VCC−VEE|
V
IIN
Input Current Through RT (50 Resistor)
Static
Surge
45
80
mA
mA
IOUT
Output Current
Continuous
Surge
25
50
mA
mA
TA
Operating Temperature Range
16 FCBGA
16 QFN
−40 to +70
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
(Note 3)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
2S2P (Note 3)
2S2P (Note 4)
16 FCBGA
16 QFN
5
4.0
°C/W
°C/W
Tsol
Wave Solder
< 15 Seconds
225
°C
Symbol
Condition 1
Condition 2
VI VCC
VI VEE
2. Maximum Ratings are those values beyond which device damage may occur.
3. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG14
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 5)
−40°C
25°C
70°C(BGA)/85°C(QFN)**
Symbol
IEE
Characteristic
Negative Power Supply Current
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
45
60
75
45
60
75
45
60
75
Unit
mA
VOH
Output HIGH Voltage (Note 6)
1525
1575
1625
1550
1610
1650
1575
1635
1675
mV
VOUTPP
Output Amplitude Voltage
315
405
495
315
405
495
315
405
495
mV
VIH
Input HIGH Voltage (Single−Ended)
(Notes 8 and 10)
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 9 and 10)
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
mV
VTHR
Input Threshold Voltage
(Single−Ended) (Note 10)
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
1.2
2.5
1.2
2.5
1.2
2.5
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@ VIH)
80
150
80
150
80
150
A
IIL
Input LOW Current (@ VIL)
25
100
25
100
25
100
A
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.5 V.
6. All outputs loaded with 50 to VCC − 1.5 V for BGA package and VCC − 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical).
7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
8. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
9. VIL always ≥ VEE. |VIL − VTHR| < 2600 mV.
10. VTHR is the voltage applied to one input when running in single−ended mode.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 11)
−40°C
25°C
70°C(BGA)/85°C(QFN)**
Symbol
IEE
Characteristic
Negative Power Supply Current
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
45
60
75
45
60
75
45
60
75
Unit
mA
VOH
Output HIGH Voltage (Note 12)
2325
2375
2425
2350
2410
2450
2375
2435
2475
mV
VOUTPP
Output Amplitude Voltage
350
440
530
350
440
530
350
440
530
mV
VIH
Input HIGH Voltage (Single−Ended)
(Notes 14 and 16)
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 15 and 16)
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
mV
VTHR
Input Threshold Voltage
(Single−Ended) (Note 16)
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
1.2
3.3
1.2
3.3
1.2
3.3
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@ VIH)
80
150
80
150
80
150
A
IIL
Input LOW Current (@ VIL)
25
100
25
100
25
100
A
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.165 V.
12. All outputs loaded with 50 to VCC − 1.5 V for BGA package and VCC − 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical).
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
14. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
15. VIL always ≥ VEE. |VIL − VTHR| < 2600 mV.
16. VTHR is the voltage applied to one input when running in single−ended mode.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
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NBSG14
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 17)
−40°C
25°C
70°C(BGA)/85°C(QFN)**
Symbol
IEE
Characteristic
Negative Power Supply Current
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
45
60
75
45
60
75
45
60
75
Unit
mA
VOH
Output HIGH Voltage (Note 18)
−975
−925
−875
−950
−890
−850
−925
−865
−825
mV
VOUTPP
Output Amplitude Voltage
−3.465 V VEE −3.0 V
−3.0 V < VEE −2.375 V
350
315
440
405
530
495
350
315
440
405
530
495
350
315
440
405
530
495
mV
VIH
Input HIGH Voltage (Single−Ended)
(Notes 20 and 22)
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
VCC−
1435
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 21 and 22)
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
VIH−
2500
VCC−
1400*
VIH−
150
mV
VTHR
Input Threshold Voltage
(Single−Ended) (Note 22)
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
VEE +
1125
VCC−
75
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
VEE + 1.2
0.0
V
RTIN
Internal Input Termination Resistor
45
IIH
Input HIGH Current (@ VIH)
IIL
Input LOW Current (@ VIL)
0.0
VEE + 1.2
0.0
VEE + 1.2
50
55
45
50
55
50
55
80
150
80
150
80
150
A
25
100
25
100
25
100
A
45
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
17. Input and output parameters vary 1:1 with VCC.
18. All outputs loaded with 50 to VCC −1.5 V for BGA package and VCC − 2 V for QFN package. VOH/VOL measured at VIH/VIL (Typical).
19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
20. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
21. VIL always ≥ VEE. |VIL − VTHR| < 2600 mV.
22. VTHR is the voltage applied to one input when running in single−ended mode.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
Table 8. AC CHARACTERISTICS for FCBGA−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Symbol
fmax
Characteristic
Maximum Frequency
(See Figure 4) (Note 23)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Duty Cycle Skew (Note 24)
Within−Device Skew (Note 25)
Device−to−Device Skew (Note 26)
tJITTER
RMS Random Clock Jitter
(Figure 4) (Note 28)
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
(Note 29)
fin < 10 Gb/s
Min
Typ
10.7
12
100
125
150
2
6
25
0.2
Max
70°C
Min
Typ
10.7
12
Max
100
125
150
10
15
50
2
6
25
1
0.2
Min
Typ
10.7
12
Max
Unit
GHz
100
125
150
ps
10
15
50
2
6
25
10
15
50
ps
1
0.2
1
ps
10
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
75
tr
tf
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
20
Q, Q
25°C
30
2600
75
55
20
30
2600
75
55
20
30
2600
mV
55
ps
23. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 to VCC − 1.5 V. Input edge rates 40 ps
(20% − 80%).
24. See Figure 6. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform.
25. Within−Device skew is measured between outputs under identical transitions and conditions on any one device.
26. Device−to−device skew for identical transitions at identical VCC levels.
27. VINPP (MAX) cannot exceed VCC − VEE (applicable only when VCC−VEE < 2600 mV).
28. Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
29. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data at 10 Gb/s.
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NBSG14
Table 9. AC CHARACTERISTICS for QFN−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 4) (Note 30)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Duty Cycle Skew (Note 31)
Within−Device Skew (Note 32)
Device−to−Device Skew (Note 33)
tJITTER
RMS Random Clock Jitter
(Figure 4) (Note 35)
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
(Note 36)
fin < 10 Gb/s
25°C
Min
Typ
Max
10.5
12
90
125
160
3
6
25
0.2
85°C
Min
Typ
Max
Min
Typ
10.5
12
90
125
160
15
15
50
3
6
25
1
0.2
Max
10.5
12
90
125
160
ps
15
15
50
3
6
25
15
15
50
ps
1
0.2
1
Unit
GHz
ps
10
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 34)
75
tr
tf
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
15
Q, Q
2600
75
55
20
30
30
2600
75
55
20
30
2600
mV
55
ps
30. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 to VCC − 2.0 V. Input edge rates 40 ps
(20% − 80%)
31. See Figure 6. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform.
32. Within−Device skew is measured between outputs under identical transitions and conditions on any one device.
33. Device−to−device skew for identical transitions at identical VCC levels.
34. VINPP (MAX) cannot exceed VCC − VEE (applicable only when VCC−VEE < 2600 mV).
35. Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
36. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data at 10 Gb/s.
10
500
8
400
7
OUTPUT AMPLITUDE
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÑÑÑÑ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
6
300
5
4
200
OUTPUT P−P SPEC
(AMPLITUDE GUARANTEE)
3
2
100
RMS JITTER
0
1
2
3
4
5
6
7
1
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
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0
JITTERout ps (RMS)
OUTPUT VOLTAGE AMPLITUDE (mV)
9
NBSG14
X = 17 ps/DIV, Y = 53 mV/DIV
Figure 5. Eye Diagram at 10.8 Gbps
(VCC − VEE = 3.3 V @ 25C with Input Data Pattern of 2^31−1 PRBS.
Total Pk−Pk System Jitter Including Signal Generator is 18 ps.
This Data was taken by Acquiring 7000 Waveforms.)
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NBSG14
D/CLK
VINPP = = VIH(CLK) − VIL(CLK)
D/CLK
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPLH
tPHL
Figure 6. AC Reference Measurement
Zo = 50 Q
Driver
Device
D
Receiver
Device
Zo = 50 Q
D
50 50 VTT
VTT = VCC − 1.5 V (BGA PACKAGE)
VTT = VCC − 2.0 V (QFN PACKAGE)
Figure 7. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 − Termination of ECL Logic Devices)
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NBSG14
PACKAGE DIMENSIONS
FCBGA−16
BA SUFFIX
PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE
CASE 489−01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
−X−
D
M
−Y−
K
E
M
0.20
3X
e
4
3
2
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
1
A
3
B
b
16 X
C
D
S
VIEW M−M
0.15
M
Z X Y
0.08
M
Z
5
0.15 Z
A
A2
A1
16 X
4
−Z−
0.10 Z
DETAIL K
ROTATED 90 CLOCKWISE
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10
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
DIM
A
A1
A2
b
D
E
e
S
MILLIMETERS
MIN
MAX
1.40 MAX
0.25
0.35
1.20 REF
0.30
0.50
4.00 BSC
4.00 BSC
1.00 BSC
0.50 BSC
NBSG14
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G−01
ISSUE A
−X−
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
M
−Y−
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
B
N
0.25 (0.010) T
0.25 (0.010) T
J
R
C
0.08 (0.003) T
−T−
K
SEATING
PLANE
E
H
G
L
5
8
4
9
F
12
1
16
D
13
P
NOTE 3
0.10 (0.004)
M
T X Y
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11
MILLIMETERS
MIN
MAX
3.00 BSC
3.00 BSC
0.80
1.00
0.23
0.28
1.75
1.85
1.75
1.85
0.50 BSC
0.875
0.925
0.20 REF
0.00
0.05
0.35
0.45
1.50 BSC
1.50 BSC
0.875
0.925
0.60
0.80
INCHES
MIN
MAX
0.118 BSC
0.118 BSC
0.031
0.039
0.009
0.011
0.069
0.073
0.069
0.073
0.020 BSC
0.034
0.036
0.008 REF
0.000
0.002
0.014
0.018
0.059 BSC
0.059 BSC
0.034
0.036
0.024
0.031
NBSG14
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12
NBSG14/D