NBSG16M 2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer http://onsemi.com Description The NBSG16M is a differential current mode logic (CML) receiver/driver/translator buffer. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 W source termination resistor to VCC. The device generates 400 mV output amplitude with 50 W receiver resistor to VCC. The VBB pin is internally generated voltage supply available to this device only. For all single−ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open. Features • • • • • • • • • • • Maximum Input Clock Frequency > 10 GHz Typical Maximum Input Data Rate > 10 Gb/s Typical 120 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V CML Output Level; 400 mV Peak−to−Peak Output with 50 W Receiver Resistor to VCC 50 W Internal Input and Output Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL and SG Devices VBB Reference Voltage Output Pb−Free Packages are Available © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 5 1 MARKING DIAGRAM* 16 1 1 QFN−16 MN SUFFIX CASE 485G A L Y W G SG 16M ALYW G G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Publication Order Number: NBSG16M/D NBSG16M VCC VBB 16 VTD 1 D 2 VEE VEE 14 13 15 Exposed Pad (EP) 12 VCC 11 Q NBSG16M D 3 10 Q VTD 4 9 VCC 5 6 7 8 VCC NC VEE VEE Figure 1. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin Name I/O Description 1 VTD − 2 D LVDS, CML, ECL, LVTTL, LVCMOS Input Inverted Differential Input (Note 3) 3 D LVDS, CML, ECL, LVTTL, LVCMOS Input Noninverted Differential Input. (Note 3) 4 VTD − Internal 50 W Termination Pin. See Table 2. (Note 3) 5 VCC − Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. 6 NC − No Connect (Note 1) 7 VEE − Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. 8 VEE − Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. 9 VCC − Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. 10 Q CML Output Noninverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2) 11 Q CML Output Inverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2) 12 VCC − Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. 13 VEE − Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. 14 VEE − Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. 15 VBB − Internally Generated ECL Reference Output Voltage 16 VCC − Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. − EP − Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. Internal 50 W Termination Pin. See Table 2. (Note 3) 1. The NC pins are electrically connected to the die and MUST be left open. 2. CML outputs require 50 W receiver termination resistor to VCC for proper operation. 3. In the differential configuration when the input termination pin (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. http://onsemi.com 2 NBSG16M VCC VCC VTD 50 W 50 W 50 W 50 W D Q D Q 50 W Q Q 50 W VTD VBB 16 mA VEE VEE Figure 2. Logic Diagram Figure 3. CML Output Structure Table 2. Interfacing Options INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD together AC−COUPLED Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. Table 3. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 4) QFN−16 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 1 kV > 100 V > 4 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 UL 94 V−0 @ 0.125 in 145 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. http://onsemi.com 3 NBSG16M Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Power Supply Parameter VEE = 0 V Condition 1 3.6 V VEE Negative Power Supply VCC = 0 V −3.6 V VI Positive Input Negative Input VEE = 0 V VCC = 0 V 3.6 −3.6 V V VINPP Differential Input Voltage |D − D| VCC − VEE w 2.8 V VCC − VEE < 2.8 V 2.8 |VCC − VEE| V IIN Input Current Through RT (50 W Resistor) Static Surge 45 80 mA mA Iout Output Current Continuous Surge 25 50 mA mA IBB VBB Sink/Source 1.0 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 5) 0 lfpm 500 lfpm QFN−16 QFN−16 42 35 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 5) QFN−16 4.0 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free Condition 2 VI v VCC VI w VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) http://onsemi.com 4 NBSG16M Table 5. DC CHARACTERISTICS, POSITIVE CML OUTPUT VCC = 2.5 V; VEE = 0 V (Note 6) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit ICC Positive Power Supply Current 37 43 51 37 43 51 37 43 51 mA VOH Output HIGH Voltage (Note 7) VCC − 40 VCC − 10 VCC VCC − 40 VCC − 10 VCC VCC − 40 VCC − 10 VCC mV VOL Output LOW Voltage (Note 6) VCC − 400 VCC− 330 VCC − 400 VCC− 330 VCC − 400 VCC− 330 mV VIH Input HIGH Voltage (Single−Ended) (Note 8) VEE + 1.275 VCC − 1.0* VCC VEE + 1.275 VCC − 1.0* VCC VEE+ 1..275 VCC − 1.0* VCC V VIL Input LOW Voltage (Single−Ended) (Note 8) VEE VCC − 1.4* VIH− 0.150 VEE VCC − 1.4* VIH− 0.150 VEE VCC − 1.4* VIH− 0.150 V VBB ECL Reference Voltage Output 1075 1170 1265 1075 1170 1265 1075 1170 1265 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 8) (Differential Configuration) 1.2 2.5 1.2 2.5 1.2 2.5 V RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 45 50 55 45 50 55 W IIH Input HIGH Current (@ VIH) 60 100 60 100 60 100 mA IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 mA Symbol Characteristic NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V. 7. All loading with 50 W to VCC. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes. http://onsemi.com 5 NBSG16M Table 6. DC CHARACTERISTICS, POSITIVE CML OUTPUT VCC = 3.3 V; VEE = 0 V (Note 9) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit ICC Positive Power Supply Current 37 43 51 37 43 51 37 43 51 mA VOH Output HIGH Voltage (Note 10) VCC − 40 VCC − 10 VCC VCC − 40 VCC − 10 VCC VCC − 40 VCC − 10 VCC mV VOL Output LOW Voltage (Note 9) VCC − 400 VCC − 330 VCC − 400 VCC − 330 VCC − 400 VCC − 330 mV VIH Input HIGH Voltage (Single−Ended) (Note 11) VEE + 1.275 VCC − 1.0* VCC VEE + 1.275 VCC − 1.0* VCC VEE + 1.275 VCC − 1.0* VCC V VIL Input LOW Voltage (Single−Ended) (Note 11) VEE VCC − 1.4* VIH − 0.150 VEE VCC − 1.4* VIH − 0.150 VEE VCC − 1.4* VIH − 0.150 V VBB ECL Reference Voltage Output 1875 1970 2065 1875 1970 2065 1875 1970 2065 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 11) (Differential Configuration) 1.2 3.3 1.2 3.3 1.2 3.3 V RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 45 50 55 45 50 55 W IIH Input HIGH Current (@ VIH) 60 100 60 100 60 100 mA IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 mA Symbol Characteristic NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V. 10. All loading with 50 W to VCC. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes. http://onsemi.com 6 NBSG16M Table 7. DC CHARACTERISTICS, NEGATIVE CML OUTPUT VCC = 0 V; VEE = −3.465 to −2.375 V (Note 12) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit ICC Positive Power Supply Current 37 43 51 37 43 51 37 43 51 mA VOH Output HIGH Voltage (Note 13) VCC − 40 VCC − 10 VCC VCC − 40 VCC − 10 VCC VCC − 40 VCC − 10 VCC mV VOL Output LOW Voltage (Note 12) VCC − 400 VCC − 330 VCC − 400 VCC − 330 VCC − 400 VCC − 330 mV VIH Input HIGH Voltage (Single−Ended) (Note 13) VEE + 1.275 VCC − 1.0* VCC VEE + 1.275 VCC − 1.0* VCC VEE + 1.275 VCC − 1.0* VCC V VIL Input LOW Voltage (Single−Ended) (Note 13) VEE VCC − 1.4* VIH− 0.150 VEE VCC − 1.4* VIH− 0.150 VEE VCC − 1.4* VIH− 0.150 V VBB ECL Reference Voltage Output −1425 −1330 −1235 −1425 −1330 −1235 −1425 −1330 −1235 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 14) (Differential Configuration) VCC V RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 45 50 55 45 50 55 W IIH Input HIGH Current (@ VIH) 60 100 60 100 60 100 mA IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 mA Symbol Characteristic VEE+1.2 VCC VEE+1.2 VCC VEE+1.2 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Input and output parameters vary 1:1 with VCC. 13. All loading with 50 W to VCC. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes. http://onsemi.com 7 NBSG16M Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V −40°C Symbol Characteristic VOUTPP Output Voltage Amplitude (See Figure 4) (Note 15) fin < 7 GHz fin < 10 GHz tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 16) tJITTER RMS Random Clock Jitter (Note 18) Min Typ 300 200 400 250 90 110 150 3 fin < 10 GHz Peak−to−Peak Data Dependent Jitter (Note 19) fin < 10 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 17) tr tf Output Rise/Fall Times @ 1 GHz (20% − 80%) 21 Typ 300 200 400 250 100 120 150 15 3 0.2 1 8 15 35 Max 85°C Min 75 Q, Q 25°C 2500 75 53 21 Max Min Typ 300 100 400 150 100 125 155 ps 15 3 15 ps 0.2 1 0.2 1.0 8 15 8 15 35 2500 75 53 21 35 Max Unit mV ps 2500 mV 53 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 15. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC. Input edge rates 40 ps (20% − 80%). 16. See Figure 8 tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform. 17. VINPP(max) cannot exceed VCC − VEE. (Applicable only when VCC − VEE < 2500 mV). Input voltage swing is a single−ended measurement operating in differential mode. 18. Additive RMS jitter with 50% duty cycle clock signal at 10GHz. 19. Additive Peak−to−Peak data dependent jitter with NRZ PRBS231−1 data rate at 10 Gb/s. OUTPUT VOLTAGE AMPLITUDE (mV) 500 VCC − VEE = 3.3 V 450 400 350 VCC − VEE = 2.5 V 300 250 200 150 100 50 0 0 1 2 3 4 5 6 FREQUENCY (GHz) 7 8 9 Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 8 10 NBSG16M Application Information Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). All inputs can accept PECL, CML, and LVDS signal levels. The input voltage can range from VCC to 1.2 V. VCC 50 W VCC 50 W Q D Z SG16M VCC VTD Z Q VCC D 50 W SG16M 50 W VTD VEE VEE Figure 5. CML to CML Interface VCC VCC 50 W PECL Driver VCC 3.3 V 150 W VEE 80 W VTD D RT VBias 50 W SG16M Z RT 5.0 V 290 W 2.5 V VBias 50 W RT Recommended RT Values D Z 50 W VTD VEE VEE Figure 7. PECL to CML Receiver Interface VCC VCC D Z LVDS Driver VTD 50 W SG16M Z D 50 W VTD VEE VEE Figure 6. LVDS to CML Receiver Interface http://onsemi.com 9 NBSG16M D VINPP(D) = VIH(D) − DIL(D) VINPP(D) = VIH(D) − DIL(D) D Q VOUTPP(Q) = VOH(Q) − VOL(Q) VOUTPP(Q) = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 8. AC Reference Measurement VCC Zo = 50 W 50 W 50 W Q D Driver Device Receiver Device Zo = 50 W Q D Figure 9. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 − Termination of ECL Logic Devices) ORDERING INFORMATION Package Shipping† QFN−16 123 Units / Rail NBSG16MMNG QFN−16 (Pb−Free) 123 Units / Rail NBSG16MMNR2 QFN−16 3000 / Tape & Reel QFN−16 (Pb−Free) 3000 / Tape & Reel Device NBSG16MMN NBSG16MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NBSG16M PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C PIN 1 LOCATION ÇÇ ÇÇ ÇÇ 0.15 C D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW SEATING PLANE A1 16X L 5 NOTE 5 e 4 16X E2 12 1 16 16X 3.25 0.128 0.30 0.012 EXPOSED PAD 9 K 1.50 0.059 3.25 0.128 e 13 b 0.10 C A B 0.05 C 0.575 0.022 EXPOSED PAD 8 SOLDERING FOOTPRINT* C D2 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 BOTTOM VIEW 0.50 0.02 NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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