Revised October 2003 74LVX174 Low Voltage Hex D-Type Flip-Flop with Master Reset General Description Features The LVX174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. ■ Input voltage level translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number 74LVX174M 74LVX174SJ 74LVX174MTC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names © 2003 Fairchild Semiconductor Corporation DS011607 Description D0–D5 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0–Q5 Outputs www.fairchildsemi.com 74LVX174 Low Voltage Hex D-Type Flip-Flop with Master Reset May 1993 74LVX174 Truth Table Inputs Outputs Operating Mode MR CP Dn Qn Reset (Clear) L X X L Load ‘1’ H H H Load ‘0’ H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA −0.5V to 7V DC Input Voltage (VI) 2.0V to 3.6V Input Voltage (VI) 0V to 5.5V Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC Operating Temperature (TA) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA Input Rise and Fall Time (∆t/∆V) −0.5V to VCC + 0.5V DC Output Voltage (VO) ±25 mA DC VCC or Ground Current ±50 mA (ICC or IGND) 0 ns/V to 100 ns/V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC Output Source or Sink Current (IO) −40°C to +85°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. −65°C to +150°C Storage Temperature (TSTG) Power Dissipation (PD) 180 mW DC Electrical Characteristics Symbol VIH VIL VOH VOL VCC Parameter TA = +25°C Min TA = −40°C to +85°C Typ Max Min HIGH Level 2.0 1.5 1.5 Input Voltage 3.0 2.0 2.0 3.6 2.4 2.4 Max 2.0 0.5 0.5 Input Voltage 3.0 0.8 0.8 3.6 0.8 0.8 HIGH Level 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 3.0 2.58 Conditions V LOW Level Output Voltage Units V VIN = VIL or VIH IOH = −4 mA 2.48 LOW Level 2.0 0.0 Output Voltage 3.0 0.0 IOH = −50 µA IOH = −50 µA V 0.1 VIN = VIL or VIH 0.1 0.1 0.1 3.0 0.36 0.44 IOL = 50 µA IOL = 50 µA V IOL = 4 mA IIN Input Leakage Current 3.6 ±0.1 ±1.0 µA VIN = 5.5V or GND ICC Quiescent Supply Current 3.6 4.0 40.0 µA VIN = VCC or GND Noise Characteristics (Note 3) Symbol Parameter VCC (V) TA = 25°C Typ Limit Units CL (pF) VOLP Quiet Output Maximum Dynamic VOL 3.3 0.3 0.5 V 50 VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.3 −0.5 V 50 VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50 VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50 Note 3: (Input tr = tf = 3 ns) 3 www.fairchildsemi.com 74LVX174 Absolute Maximum Ratings(Note 1) 74LVX174 AC Electrical Characteristics Symbol Parameter tPLH Propagation tPHL Delay Time CP to Qn tPHL Propagation Delay TA = +25°C VCC (V) Min 2.7 3.3 ± 0.3 2.7 MR to Qn 3.3 ± 0.3 tS tH tREC Setup Time Max 7.6 14.5 1.0 17.5 15 18.0 1.0 21.0 50 5.9 9.3 1.0 11.0 8.4 12.8 1.0 14.5 15.0 1.0 18.5 15 18.5 1.0 22.0 50 6.2 9.7 1.0 11.5 8.7 13.2 1.0 15.0 8.5 6.0 Hold Time 2.7 0 0 Dn to CP 3.3 ± 0.3 0 0 2.7 4.5 4.5 3.3 ± 0.3 3.0 3.0 2.7 6.5 7.5 3.3 ± 0.3 5.0 5.0 2.7 6.5 7.5 3.3 ± 0.3 5.0 5.0 2.7 65 130 55 45 60 40 115 180 95 65 95 MR Pulse Maximum Clock Frequency 3.3 ± 0.3 15 50 7.9 7.5 Clock Pulse ns 10.4 5.0 Removal Time CL (pF) Units 10.1 2.7 Width fMAX Min 3.3 ± 0.3 Width tW Max Dn to CP MR to CP tW TA = −40°C to +85°C Typ ns 15 50 ns ns ns 15 50 MHz 15 55 50 tOSLH Output to Output 2.7 1.5 1.5 tOSHL Skew (Note 4) 3.3 1.5 1.5 50 ns Note 4: Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn| Capacitance Symbol TA = +25°C Parameter Min TA = −40°C to +85°C Typ Max 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance (Note 5) 29 Min Max 10 Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. www.fairchildsemi.com 4 Units pF pF 74LVX174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com 74LVX174 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74LVX174 Low Voltage Hex D-Type Flip-Flop with Master Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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