FAIRCHILD 74VHC4053WM

Revised April 1999
74VHC4051 • 74VHC4052 • 74VHC4053
8-Channel Analog Multiplexer • Dual 4-Channel Analog
Multiplexer • Triple 2-Channel Analog Multiplexer
General Description
These multiplexers are digitally controlled analog switches
implemented in advanced silicon-gate CMOS technology.
These switches have low “on” resistance and low “off” leakages. They are bidirectional switches, thus any analog
input may be used as an output and vice-versa. Also these
switches contain linearization circuitry which lowers the
“on” resistance and increases switch linearity. These
devices allow control of up to ±6V (peak) analog signals
with digital control signals of 0 to 6V. Three supply pins are
provided for VCC, ground, and VEE. This enables the connection of 0–5V logic signals when VCC = 5V and an analog
input range of ±5V when VEE = 5V. All three devices also
have an inhibit control which when high will disable all
switches to their off state. All analog inputs and outputs
and digital inputs are protected from electrostatic damage
by diodes to VCC and ground.
VHC4051: This device connects together the outputs of 8
switches, thus achieving an 8 channel Multiplexer. The
binary code placed on the A, B, and C select lines determines which one of the eight switches is “on”, and connects one of the eight inputs to the common output.
VHC4052: This device connects together the outputs of 4
switches in two sets, thus achieving a pair of 4-channel
multiplexers. The binary code placed on the A, and B
select lines determine which switch in each 4 channel section is “on”, connecting one of the four inputs in each section to its common output. This enables the implementation
of a 4-channel differential multiplexer.
VHC4053: This device contains 6 switches whose outputs
are connected together in pairs, thus implementing a triple
2 channel multiplexer, or the equivalent of 3 single-poledouble throw configurations. Each of the A, B, or C select
lines independently controls one pair of switches, selecting
one of the two switches to be “on”.
Features
■ Wide analog input voltage range: ±6V
■ Low “on” resistance: 50 typ. (VCC–VEE = 4.5V)
30 typ. (VCC–VEE = 9V)
■ Logic level translation to enable 5V logic with ±5V analog signals
■ Low quiescent current: 80 µA maximum
■ Matched switch characteristic
■ Pin and function compatible with the 74HC4051/ 4052/
4053
Ordering Code:
Order Number
74VHC4051M
Package Number
M16A
74VHC4051WM
M16B
74VHC4051MTC
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4051N
N16E
74VHC4052M
M16A
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC4052WM
M16B
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74VHC4052MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4052N
N16E
74VHC4053M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC4053WM
M16B
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74VHC4053MTC
MTC16
74VHC4053N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS011674.prf
www.fairchildsemi.com
74VHC4051 • 74VHC4052 • 74VHC4053 8-Channel Analog Multiplexer • Dual 4-Channel Analog Multiplexer • Triple
2-Channel Analog Multiplexer
April 1994
74VHC4051 • 74VHC4052 • 74VHC4053
Connection Diagrams
Truth Tables
4051
Input
“ON”
INH
C
B
A
Channel
H
X
X
X
None
L
L
L
L
Y0
L
L
L
H
Y1
L
L
H
L
Y2
L
L
H
H
Y3
L
H
L
L
Y4
L
H
L
H
Y5
L
H
H
L
Y6
L
H
H
H
Y7
Top View
4052
Inputs
“ON” Channels
INH
B
A
X
Y
H
X
X
None
None
L
L
L
0X
0Y
L
L
H
1X
1Y
L
H
L
2X
2Y
L
H
H
3X
3Y
4053
Top View
Input
Top View
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2
“ON” Channels
INH
C
B
A
C
B
A
H
X
X
X
None
None
None
L
L
L
L
CX
BX
AX
L
L
L
H
CX
BX
AY
L
L
H
L
CX
BY
AX
L
L
H
H
CX
BY
AY
L
H
L
L
CY
BX
AX
L
H
L
H
CY
BX
AY
L
H
H
L
CY
BY
AX
L
H
H
H
CY
BY
AY
74VHC4051 • 74VHC4052 • 74VHC4053
Logic Diagrams
74VHC4051
74VHC4052
74VHC4053
3
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74VHC4051 • 74VHC4052 • 74VHC4053
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
Supply Voltage (VCC )
−0.5 to +7.5V
Supply Voltage (VEE)
+0.5 to −7.5V
Control Input Voltage (VIN)
Switch I/O Voltage (VIO)
Clamp Diode Current (IIK, IOK)
−1.5 to VCC+1.5V
VEE−0.5 to VCC+0.5V
±20 mA
Output Current, per pin (IOUT)
±25 mA
VCC or GND Current, per pin (ICC)
±50 mA
Max
2
6
Units
V
Supply Voltage (VEE)
0
−6
V
DC Input or Output Voltage
0
VCC
V
−40
+85
°C
VCC = 2.0V
(VIN, VOUT)
Operating Temperature Range
(TA)
Storage Temperature Range
(TSTG)
Min
Supply Voltage (VCC)
Input Rise or Fall Times
−65°C to +150°C
(tr, tf)
Power Dissipation (PD)
1000
ns
(Note 3)
600 mW
VCC = 4.5V
500
ns
S.O. Package only
500 mW
VCC = 6.0V
400
ns
Lead Temperature (TL)
(Soldering 10 seconds)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
260°C
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
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4
Symbol
VIH
VIL
RON
RON
IN
ICC
IIZ
IIZ
Parameter
(Note 4)
VEE
Conditions
VCC
TA = 25°C TA = −40 to 85°C
Typ
Guaranteed Limits
Units
Minimum HIGH Level
2.0V
1.5
1.5
Input Voltage
4.5V
3.15
3.15
V
V
6.0V
4.2
4.2
V
V
Maximum LOW Level
2.0V
0.5
0.5
Input Voltage
4.5V
1.35
1.35
V
6.0V
1.8
1.8
V
Maximum “ON” Resistance
VINH = VIL, IS = 2.0 mA
GND
4.5V
40
160
200
Ω
(Note 5)
VIS = VCC to VEE
−4.5V
4.5V
30
120
150
Ω
(Figure 1)
−6.0V
6.0V
20
100
125
Ω
VINH = VIL, IS = 2.0 mA
GND
2.0V
100
230
280
Ω
VIS = VCC or VEE
GND
4.5V
40
110
140
Ω
(Figure 1)
−4.5V
4.5V
20
90
120
Ω
−6.0V
6.0V
15
80
100
Ω
Maximum “ON” Resistance
VINH = VIL
GND
4.5V
10
20
25
Ω
Matching
VIS = VCC to GND
−4.5V
4.5V
5
10
15
Ω
−6.0V
6.0V
5
10
12
Ω
±.05
±0.5
µA
Maximum Control
VIN = VCC or GND
Input Current
VCC = 2 − 6V
Maximum Quiescent
VIN = VCC or GND
GND
6.0V
4
40
µA
Supply Current
IOUT = 0 µA
−6.0V
6.0V
8
80
µA
Maximum Switch “OFF”
VOS = VCC or VEE
GND
6.0V
±60
±300
nA
Leakage Current
VIS = VEE or VCC
−6.0V
6.0V
±100
±500
nA
GND
6.0V
±0.1
±1.0
µA
−6.0V
6.0V
±0.2
±2.0
µA
GND
6.0V
±0.050
±0.5
µA
−6.0V
6.0V
±0.1
±1.0
µA
GND
6.0V
±0.05
±0.5
µA
−6.0V
6.0V
±0.5
±0.5
µA
GND
6.0V
±0.1
±1.0
µA
−6.0V
6.0V
±0.2
±2.0
µA
GND
6.0V
±0.05
±0.5
µA
−6.0V
6.0V
±0.1
±1.0
µA
(Switch Input)
VINH = VIH (Figure 2)
Maximum Switch “ON”
VIS = VCC to VEE
Leakage Current
VHC4051 VINH = VIL
(Figure 3)
VIS = VCC to VEE
VHC4052 VINH = VIL
(Figure 3)
VIS = VCC to VEE
VHC4053 VINH = VIL
(Figure 3)
IIZ
Maximum Switch
“OFF” Leakage
Current (Common Pin)
VOS = VCC or VEE
VHC4051 VIS = VEE or VCC
VINH = VIH
VOS = VCC or VEE
VHC4052 VIS = VEE or VCC
VINH = VIH
VOS = VCC or VEE
VHC4053 VIS = VEE or VCC
GND
6.0V
±0.05
±0.5
µA
−6.0V
6.0V
±0.05
±0.5
µA
VINH = VIH
Note 4: For a power supply of 5V ±10% the worst case on resistances (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occur
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (VCC–VEE) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
these devices be used to transmit digital only when using these supply voltages.
Note 6: Adjust 0 dB for f = 1 kHz (Null R1/RON Attenuation).
5
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74VHC4051 • 74VHC4052 • 74VHC4053
DC Electrical Characteristics
74VHC4051 • 74VHC4052 • 74VHC4053
AC Electrical Characteristics
VCC = 2.0V − 6.0V, VEE = 0V − 6V, CL = 50 pF (unless otherwise specified)
Symbol
tPHL, tPLH
tPZL, tPZH
tPHZ, tPLZ
fMAX
Parameter
VEE
Conditions
Maximum Propagation Delay
Switch In to Out
Maximum Switch Turn “ON”
Delay
RL = 1 kΩ
Maximum Switch Turn “OFF”
Delay
VCC
TA=25°C
Typ
TA=−40 to 85°C
Guaranteed Limits
Units
GND
3.3V
25
35
40
ns
GND
4.5V
5
12
15
ns
−4.5V
4.5V
4
8
12
ns
−6.0V
6.0V
3
7
11
ns
GND
3.3V
92
200
250
ns
69
87
ns
16
46
58
ns
GND
4.5V
−4.5V
4.5V
−6.0V
6.0V
15
41
51
ns
GND
3.3V
65
170
210
ns
GND
4.5V
28
58
73
ns
−4.5V
4.5V
18
37
46
ns
32
41
−6.0V
6.0V
16
Minimum Switch
GND
4.5V
30
MHz
Frequency Response
−4.5V
4.5V
35
MHz
ns
20 log (VI/VO) = 3 dB
Control to Switch
RL = 600Ω,
VIS = 4 VPP
0V
4.5V
1080
mV
Feedthrough Noise
f = 1 MHz,
VIS = 8 VPP
−4.5V
4.5V
250
mV
CL = 50 pF
THD
Crosstalk between
RL = 600Ω,
VIS = 4 VPP
0V
4.5
−52
dB
any Two Switches
f = 1 MHz
VIS = 8 VPP
−4.5V
4.5V
−50
dB
Switch OFF Signal
RL = 600Ω,
VIS = 4 VPP
0V
4.5V
−42
dB
Feedthrough
f = 1 MHz,
VIS = 8 VPP
−4.5V
4.5V
−44
dB
Isolation
VCTL = VIL
Sinewave Harmonic
RL = 10 kΩ,
VIS = 4 VPP
0V
4.5V
0.013
%
Distortion
CL = 50 pF,
VIS = 8 VPP
−4.5V
4.5V
0.008
%
f = 1 kHz
CIN
Maximum Control
5
10
10
pF
Input Capacitance
CIN
CIN
Maximum Switch
Input
15
Input Capacitance
4051 Common
90
4052 Common
45
4053 Common
30
Maximum Feedthrough
5
Capacitance
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6
pF
pF
74VHC4051 • 74VHC4052 • 74VHC4053
AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
FIGURE 6. tPZH, tPHZ Propagation Delay TIme Control to Signal Output
FIGURE 7. Crosstalk: Control Input to Signal Output
7
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74VHC4051 • 74VHC4052 • 74VHC4053
AC Test Circuits and Switching Time Waveforms
(Continued)
FIGURE 8. Crosstalk Between Any Two Switches
Typical Performance Characteristics
Typical “On” Resistance
vs Input Voltage
VCC =−VEE
Special Considerations
In certain applications the external load-resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the analog switch pins, the voltage drop across the switch must not exceed
1.2V (calculated from the ON resistance).
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8
74VHC4051 • 74VHC4052 • 74VHC4053
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M16B
9
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74VHC4051 • 74VHC4052 • 74VHC4053
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
www.fairchildsemi.com
10
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC4051 • 74VHC4052 • 74VHC4053 8-Channel Analog Multiplexer • Dual 4-Channel Analog Multiplexer • Triple
2-Channel Analog Multiplexer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)