FAIRCHILD MM74C86

Revised January 1999
MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
General Description
Features
The MM74C86 employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption and high noise margin these gates
provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel
enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to VCC and GND.
■ Wide supply voltage range:
3.0V to 15V
■ Guaranteed noise margin:
■ High noise immunity:
1.0V
0.45 VCC (typ.)
■ Low power: TTL compatibility:
Fan out of 2 driving 74L
■ Low power consumption:
10 nW/package (typ.)
■ The MM74C86 follows the MM74LS86 Pinout
Ordering Code:
Order Number
Package Number
Package Description
MM74C86M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C86N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Inputs
Pin Assignments for DIP and SOIC
Output
A
B
L
L
Y
L
L
H
H
H
L
H
H
H
L
H = HIGH Level
L = LOW Level
Top View
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MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
October 1987
MM74C86
Absolute Maximum Ratings(Note 1)
Voltage at any Pin (Note 1)
Absolute Maximum (VCC)
−0.3V to VCC + 0.3V
Operating Temperature Range
Storage Temperature Range
(Soldering, 10 seconds)
−40°C to +85°C
−65°C to +150°C
700 mW
Small Outline
500 mW
Operating Range (VCC)
260°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions
for actual device operation.
Power Dissipation (PD)
Dual-In-Line Package
18V
Lead Temperature
3.0V to 15V
DC Electrical Characteristics
Min/max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
VIN(0)
VOUT(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
VCC = 5.0V
3.5
VCC = 10V
8.0
V
V
VCC = 5.0V
1.5
V
VCC = 10V
2.0
V
VCC = 5.0V, IO = −10 µA
4.5
VCC = 10V, IO = −10 µA
9.0
VOUT(0)
Logical “0” Output Voltage
VCC = 5.0V, IO = +10 µA
IIN(1)
Logical “1” Input Current
VCC = 15V, VIN = 15V
IIN(0)
Logical “0” Input Current
VCC = 15V, VIN = 0V
ICC
Supply Current
VCC = 15V
V
V
0.5
VCC = 10V, IO = +10 µA
0.005
−1.0
1.0
V
1.0
µA
−0.005
0.01
V
µA
15
µA
0.8
V
CMOS/LPTTL INTERFACE
VIN(1)
Logical “1” Input Voltage
VCC = 4.75V
VIN(0)
Logical “0” Input Voltage
VCC = 4.75V
VCC−1.5
VOUT(1)
Logical “1” Output Voltage
VCC = 4.75V, IO = −360 µA
VOUT(0)
Logical “0” Output Voltage
VCC = 4.75V, IO = 360 µA
V
2.4
V
0.4
V
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
ISOURCE
ISINK
ISINK
Output Source Current
VCC = 5.0V, VOUT = 0V
(P-Channel)
TA = 25°C
Output Source Current
VCC = 10V, VOUT = 0V
(P-Channel)
TA = 25°C
Output Sink Current
VCC = 5.0V, VOUT = VCC
(N-Channel)
TA = 25°C
Output Sink Current
VCC = 10V, VOUT = VCC
(N-Channel)
TA = 25°C
−1.75
−3.3
mA
−8.0
−15
mA
1.75
3.6
mA
8.0
16
mA
Min
AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol
Typ
Max
Propagation Time to Logical
VCC = 5.0V
110
185
ns
“1” or “0”
VCC = 10V
50
90
ns
CIN
Input Capacitance
(Note 3)
5.0
pF
CPD
Power Dissipation Capacitance
Per Gate (Note 4)
20
pF
tpd
Parameter
Conditions
Units
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note—
AN-90.
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2
MM74C86
Typical Performance Characteristics
Propagation Delay Time vs
Load Capacitance
Test Circuits and Waveforms
Delays Measured with Input tr, tf = 20 ns
FIGURE 1. AC Test Circuit
FIGURE 2. Switching Time Waveforms
3
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MM74C86
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
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4
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
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1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)