Revised January 2000
74VHC4066
Quad Analog Switch
General Description
Features
These devices are digitally controlled analog switches utilizing advanced silicon-gate CMOS technology. These
switches have low “on” resistance and low “off” leakages.
They are bidirectional switches, thus any analog input may
be used as an output and visa-versa. Also the 4066
switches contain linearization circuitry which lowers the
“on” resistance and increases switch linearity. The 4066
devices allow control of up to 12V (peak) analog signals
with digital control signals of the same range. Each switch
has its own control input which disables each switch when
low. All analog inputs and outputs and digital inputs are
protected from electrostatic damage by diodes to VCC and
ground.
■ Typical switch enable time: 15 ns
■ Wide analog input voltage range: 0–12V
■ Low “on” resistance: 30 typ. ('4066)
■ Low quiescent current: 80 µA maximum (74VHC)
■ Matched switch characteristics
■ Individual switch controls
■ Pin and function compatible with the 74HC4066
Ordering Code:
Order Number
74VHC4066M
74VHC4066MTC
74VHC4066N
Package Number
M14A
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Schematic Diagram
Top View
Truth Table
© 2000 Fairchild Semiconductor Corporation
DS011677
Input
Switch
CTL
I/O–O/I
L
“OFF”
H
“ON”
www.fairchildsemi.com
74VHC4066 Quad Analog Switch
April 1994
74VHC4066
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
Supply Voltage (VCC)
DC Control Input Voltage (VIN)
DC Switch I/O Voltage (VIO)
−0.5 to +15V
−1.5 to VCC + 1.5V
VEE − 0.5 to VCC + 0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
DC VCC or GND Current, per pin
(ICC)
Storage Temperature Range (TSTG)
V
DC Input or Output Voltage
0
VCC
V
−40
+85
°C
Input Rise or Fall Times
600 mW
500 mW
Units
(tr, tf)
VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 9.0V
400
ns
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
12
(VIN, VOUT)
±50 mA
S.O. Package only
Max
2
Operating Temperature Range (TA)
−65°C to +150°C
Power Dissipation (PD) (Note 3)
Min
Supply Voltage (VCC)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
VIH
VIL
RON
Parameter
(Note 4)
VCC
Conditions
IIN
IIZ
IIZ
Units
2.0V
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
V
9.0V
6.3
5.3
V
12.0V
8.4
8.4
V
Maximum LOW Level
2.0V
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
V
9.0V
2.7
2.7
V
12.0V
3.6
3.6
V
Maximum “ON” Resistance
VCTL = VIH, IS = 2.0 mA
4.5V
100
170
200
Ω
See (Note 5)
VIS = V CC to GND
9.0V
50
85
105
Ω
(Figure 1)
12.0V
30
70
85
Ω
2.0V
120
180
215
Ω
4.5V
50
80
100
Ω
Ω
VIS = V CC or GND
9.0V
35
60
75
(Figure 1)
12.0V
20
40
60
Ω
Maximum “ON” Resistance
VCTL = VIH
4.5V
10
15
20
Ω
Matching
VIS = V CC to GND
Ω
Maximum Control
9.0V
5
10
15
12.0V
5
10
15
Ω
±0.05
±0.5
µA
VIN = VCC or GND
Input Current
VCC = 2 − 6V
Maximum Switch “OFF”
VOS = V CC or GND
6.0V
10
±60
±600
nA
Leakage Current
VIS = GND or VCC
9.0V
15
±80
±800
nA
VCTL = VIL (Figure 2)
12.0V
20
±100
±1000
nA
VIS = V CC to GND
6.0V
10
±40
±150
nA
nA
Maximum Switch “ON”
VCTL = VIH
9.0V
15
±50
±200
VOS = OPEN (Figure 3)
12.0V
20
±60
±300
nA
Maximum Quiescent
VIN = VCC or GND
6.0V
1.0
10
µA
Supply Current
IOUT = 0 µA
Leakage Current
ICC
TA=−40 to 85°C
Guaranteed Limits
Minimum HIGH Level
VCTL = VIH, IS = 2.0 mA
RON
TA=25°C
Typ
9.0V
2.0
20
µA
12.0V
4.0
40
µA
Note 4: For a power supply of 5V ± 10% the worst case on resistance (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (VCC – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
these devices be used to transmit digital only when using these supply voltages.
www.fairchildsemi.com
2
VCC = 2.0V−6.0V VEE = 0V−12V, CL = 50 pF (unless otherwise specified)
Symbol
tPHL, tPLH
tPZL, tPZH
Parameter
VCC
Conditions
TA=−40 to 85°C
Guaranteed Limits
Units
Maximum Propagation
3.3V
25
30
20
Delay Switch In to Out
4.5V
5
10
13
ns
9.0V
4
8
10
ns
ns
Maximum Switch Turn
RL = 1 kΩ
“ON” Delay
tPHZ, tPLZ
TA=25°C
Typ
Maximum Switch Turn
RL = 1 kΩ
“OFF” Delay
ns
12.0V
3
7
11
3.3V
30
58
73
ns
4.5V
12
20
25
ns
9.0V
6
12
15
ns
12.0V
5
10
13
ns
3.3V
60
100
125
ns
4.5V
25
36
45
ns
9.0V
20
32
40
ns
30
38
12.0V
15
Minimum Frequency
RL = 600Ω
4.5V
40
MHz
Response (Figure 7)
VIS = 2 VPP at (VCC/2)
9.0V
100
MHz
dB
20 log(VO/VI) = −3 dB
(Note 6)(Note 7)
Crosstalk Between
RL = 600Ω, F = 1 MHz
any Two Switches
(Note 7)(Note 8)
(Figure 8)
4.5V
−52
9.0V
−50
dB
Peak Control to Switch
RL = 600Ω, F = 1 MHz
4.5V
100
mV
Feedthrough Noise
CL = 50 pF
9.0V
250
mV
4.5V
−42
dB
9.0V
−44
dB
%
(Figure 9)
Switch OFF Signal
RL = 600Ω, F = 1 MHz
Feedthrough
V(CT) VIL
Isolation
(Note 7)(Note 8)
(Figure 10)
THD
CIN
Total Harmonic
RL = 10 kΩ, CL = 50 pF,
Distortion
F = 1 kHz
(Figure 11)
VIS = 4 VPP
4.5V
.013
VIS = 8 VPP
9.0V
.008
Maximum Control
5
%
10
10
pF
Input Capacitance
CIN
Maximum Switch
20
pF
0.5
pF
15
pF
Input Capacitance
CIN
Maximum Feedthrough
VCTL = GND
Capacitance
CPD
Power Dissipation
Capacitance
Note 6: Adjust 0 dBm for F = 1 kHz (Null RL/RON Attenuation).
Note 7: VIS is centered at VCC/2.
Note 8: Adjust input for 0 dBm.
3
www.fairchildsemi.com
74VHC4066
AC Electrical Characteristics
74VHC4066
AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
www.fairchildsemi.com
4
74VHC4066
AC Test Circuits and Switching Time Waveforms
(Continued)
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output
FIGURE 7. Frequency Response
Crosstalk and Distortion Test Circuits
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Crosstalk Between Any Two Switches
5
www.fairchildsemi.com
74VHC4066
Crosstalk and Distortion Test Circuits
(Continued)
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
Typical Performance Characteristics
Typical “ON” Resistance
Typical Crosstalk Between
Any Two Switches
Typical Frequency Response
Special Considerations
In certain applications the external load-resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must not
exceed 0.6V (calculated from the ON resistance).
www.fairchildsemi.com
6
74VHC4066
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
7
www.fairchildsemi.com
74VHC4066
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com
8
74VHC4066 Quad Analog Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
www.fairchildsemi.com
9
www.fairchildsemi.com