FUJITSU MB81ES173225-15WFKT-X

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11408-3E
MEMORY
CMOS
× 512 K × 16 BIT / 2 × 256 K × 32 BIT
SINGLE DATA RATE I/F FCRAMTM(Extended Temp. Version)
2
Consumer/Embedded Application Specific Memory for SiP
MB81ES171625/173225-15-X
■ DESCRIPTION
The Fujitsu MB81ES171625/173225 is a Fast Cycle Random Access Memory (FCRAM*) containing 16,777,216
bit memory cells accessible in a 2×512K×16 bit / 2×256K×32 bit format. The MB81ES171625/173225 features a
fully synchronous operation referenced to a positive edge clock same as that of SDRAM operation, whereby all
operations are synchronized at a clock input which enables high performance and simple user interface coexistence.
The MB81ES171625/173225 is utilized using a Fujitsu advanced FCRAM core technology and designed for low
power consumption and low voltage operation than regular synchronous DRAM (SDRAM).
The MB81ES171625/173225 is dedicated for SiP (System in a Package), and ideally suited for various embedded/
consumer applications including digital AVs, and image processing where a large band width and low power
consumption memory is needed.
* : FCRAM is a trademark of Fujitsu Limited, Japan.
■ PRODUCT LINEUP
Parameter
MB81ES171625/173225-15-X
Clock Frequency (Max)
Burst Mode Cycle Time (Min)
Access Time From Clock (Max)
66.7 MHz
CL = 1
30 ns
CL = 2
15 ns
CL = 1
27 ns
CL = 2
12 ns
XRAS Cycle Time (Min)
75 ns
Operating Current (Max) (IDD1)
30 mA
Power Down Mode Current (Max) (IDD2P)
1 mA
Self-refresh Current (Max) (IDD6)
5 mA
MB81ES171625/173225-15-X
■ FEATURES
• FCRAM core with Single Data Rate SDRAM
interface
• 512 K word × 16 bit × 2 bank or 256 K word × 32 bit
× 2 bank organization
• Single +1.8 V Supply ±0.15 V tolerance
• CMOS I/O interface
• Programmable burst type, burst length, and CAS latency
Burst type : Sequential Mode, Interleave Mode
Burst length : 1, 2, 4, 8, full column (64 : ×16 bit, 32 : ×32 bit)
CAS latency
MB81ES171625/173225-15-X
CL = 1 (Min tCK = 30 ns, Max 33.3 MHz)
CL = 2 (Min tCK = 15 ns, Max 66.7 MHz)
• 2 K refresh cycles every 4 ms
• Auto- and Self-refresh
• CKE power down mode
• Output Enable and Input Data Mask
• Burst Stop command at full column burst
• Burst read/write
• 66.7 MHz Clock frequency
2
MB81ES171625/173225-15-X
■ PAD LAYOUT
PAD
• MB81ES171625
DSE
BME
TBST
DQC
VSS
VDD
VSS
VDD
DQ8
DQ9
DQ10
DQ11
VDDQ
VSSQ
DQ12
DQ13
DQ14
DQ15
DQM1
A12
A11
BA
A10/AP
A9
A8
A7
A6
CLK
CKE
VSSQ
S16
VDDQ
XCS
XRAS
XCAS
XWE
A5
A4
A3
A2
A1
A0
DQM0
DQ7
DQ6
DQ5
DQ4
VSSQ
VDDQ
DQ3
DQ2
DQ1
DQ0
VDD
VSS
VDD
VSS
-
PAD No.84
PAD No.1
3
MB81ES171625/173225-15-X
PAD
• MB81ES173225
DSE
BME
TBST
DQC
DQ16
DQ17
DQ18
DQ19
VDDQ
VSSQ
DQ20
DQ21
DQ22
DQ23
VSS
VDD
VSS
VDD
DQ24
DQ25
DQ26
DQ27
VDDQ
VSSQ
DQ28
DQ29
DQ30
DQ31
DQM2
DQM3
A12
A11
BA
A10/AP
A9
A8
A7
A6
CLK
CKE
VSSQ
S32
VDDQ
XCS
XRAS
XCAS
XWE
A5
A4
A3
A2
A1
A0
DQM1
DQM0
DQ15
DQ14
DQ13
DQ12
VSSQ
VDDQ
DQ11
DQ10
DQ9
DQ8
VDD
VSS
VDD
VSS
DQ7
DQ6
DQ5
DQ4
VSSQ
VDDQ
DQ3
DQ2
DQ1
DQ0
-
PAD No.84
PAD No.1
4
MB81ES171625/173225-15-X
■ PAD DESCRIPTIONS
• MB81ES171625
Symbol
Function
VDD, VDDQ
Supply Voltage
VSS, VSSQ
Ground
DQ15 to DQ0
Data I/O
DQM1 to DQM0
DQ MASK
XWE
Write Enable
XCAS
Column Address Strobe
XRAS
Row Address Strobe
XCS
Chip Select
BA
Bank Select
AP
Auto Precharge Enable
A12 to A0
Address Input
CKE
Clock Enable
CLK
Clock Input
TBST
BIST Control
BME
Burn In Enable
DSE
Disable
DQC
BIST Output
S16
× 16 Select
• MB81ES173225
Symbol
Function
VDD, VDDQ
Supply Voltage
VSS, VSSQ
Ground
DQ31 to DQ0
Data I/O
DQM3 to DQM0
• Row : A12 to A0 • Column : A5 to A0
DQ MASK
XWE
Write Enable
XCAS
Column Address Strobe
XRAS
Row Address Strobe
XCS
Chip Select
BA
Bank Select
AP
Auto Precharge Enable
A12 to A0
Address Input
CKE
Clock Enable
CLK
Clock Input
TBST
BIST Control
BME
Burn In Enable
DSE
Disable
DQC
BIST Output
S32
× 32 Select
• Row : A12 to A0 • Column : A4 to A0
5
MB81ES171625/173225-15-X
■ BLOCK DIAGRAM
• MB81ES171625
To each block
CLK
CKE
CLOCK
BUFFER
BANK-1
S16
BANK-0
XRAS
DSE
BME
XCS
COMMAND
DECODER
CONTROL
SIGNAL
LATCH
XCAS
XWE
XRAS
FCRAM
CORE
(8,192 × 64 × 16)
XCAS
XWE
A12,A11,A9 to A0,
A10/AP
BA
MODE
REGISTER
ADDRESS
BUFFER/
REGISTER
&
BANK
SELECT
ROW
ADDR.
13
COLUMN
ADDRESS
COUNTER
6
COL.
ADDR.
I/O
DQM1 to DQM0
I/O DATA
BUFFER/
REGISTER
DQ15 to DQ0
16
VDD
VDDQ
VSS/VSSQ
TBST
DQC
6
BIST
MB81ES171625/173225-15-X
• MB81ES173225
To each block
CLK
CKE
CLOCK
BUFFER
BANK-1
S32
BANK-0
XRAS
CONTROL
SIGNAL
LATCH
DSE
BME
XCS
XRAS
XCAS
COMMAND
DECODER
XWE
FCRAM
CORE
(8,192 × 32 × 32)
XCAS
XWE
A12,A11,A9 to A0,
A10/AP
BA
MODE
REGISTER
ADDRESS
BUFFER/
REGISTER
&
BANK
SELECT
ROW
ADDR.
13
COLUMN
ADDRESS
COUNTER
5
COL.
ADDR.
I/O
DQM3 to DQM0
DQ31 to DQ0
I/O DATA
BUFFER/
REGISTER
32
VDD
VDDQ
VSS/VSSQ
TBST
BIST
DQC
7
MB81ES171625/173225-15-X
■ FUNCTIONAL TRUTH TABLE
1. Command Truth Table
CKE
BA
A10/
AP
A12 to
A6
A5
A4 to
A0
X
X
X
X
X
X
H
H
X
X
X
X
X
H
H
L
X
X
X
X
X
L
H
L
H
V
L
X
V
V
X
L
H
L
H
V
L
X
X
V
H
X
L
H
L
H
V
H
X
V
V
H
X
L
H
L
H
V
H
X
X
V
H
X
L
H
L
L
V
L
X
V
V
H
X
L
H
L
L
V
L
X
X
V
H
X
L
H
L
L
V
H
X
V
V
H
X
L
H
L
L
V
H
X
X
V
ACTV
H
X
L
L
H
H
V
V
V
V
V
Precharge Single Bank *5
PRE
H
X
L
L
H
L
V
L
X
X
X
Precharge All Banks *5
PALL
H
X
L
L
H
L
X
H
X
X
X
MRS
H
X
L
L
L
L
L
L
V
V
V
Function
Command
n-1
n
Device Deselect *1
DESL
H
X
H
X
X
No Operation *1
NOP
H
X
L
H
BST
H
X
L
H
X
H
Burst Stop*
2
X16
Read *3
X32
Read with
Auto-precharge *3
X32
X16
Write *3
X32
Write with
Auto-precharge *3
Bank Active *
X16
X16
X32
4
5, 6
Mode Register Set * *
READ
READA
WRIT
WRITA
XCS XRAS XCAS XWE
V = Valid, L = Logic Low, H = Logic High, X = either L or H,
n = state at current clock cycle, n−1 = state at 1 clock cycle before n.
*1: NOP and DESL commands have the same effect on the part. At DESL command (XCS = “H”) , all input signal
are ignored, but hold the internal state. NOP command (XCS = “L”, XRAS = XCAS = XWE = “H”) is no effect on
device operation and the internal state continue.
*2: BST command is effective on every Burst Length. (BL = 1, 2, 4, 8, full column)
*3: READ, READA, WRIT and WRITA commands should be issued only after the corresponding bank has been
activated (ACTV command) . Refer to “■STATE DIAGRAM”.
*4: ACTV command should be issued only after the corresponding bank has been precharged (PRE or PALL
command) .
*5: Required after power up. Refer to “17. Power-Up- Initialization” in “■FUNCTIONAL DESCRIPTION.”
*6: MRS command should be issued only after all banks have been precharged (PRE or PALL command) and DQ
is in High-Z. Refer to “■STATE DIAGRAM”.
Notes: • All commands assumes no CSUS command on previous rising edge of clock.
• All commands are assumed to be valid state transitions.
• All inputs are latched on the rising edge of the clock.
• TBST,BME and DSE should be held Low.
• S16 should be held VIH, and S32 should be held VIL.
8
MB81ES171625/173225-15-X
2. DQM Truth Table
Function
CKE
Command
Data Input/Output Enable
DQM
n-1
n
H
X
L
H
X
H
ENBL
Data Input/Output Disable
MASK
V = Valid, L = Logic Low, H = Logic High, X = either L or H,
n = state at current clock cycle, n−1 = state at 1 clock cycle before n.
Notes : • MB81ES171625; DQM0 and DQM1 control DQ7 to DQ0 and DQ15 to DQ8, respectively.
• MB81ES173225; DQM0, DQM1, DQM2 and DQM3 control DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, and
DQ31 to DQ24, respectively.
• All commands assume no CSUS command on previous rising edge of clock.
• All commands are assumed to be valid state transition.
• All inputs are latched on the rising edge of clock.
• TBST, BME and DSE should be held Low.
• S16 should be held VIH, and S32 should be held VIL.
3. CKE Truth Table
Current
State
CKE
A10/
AP
A12, A11,
A9 to A0
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
Command
n-1
n
CSUS
H
L
X
X
X
X
Any
Clock Suspend
(Except Idle) Continue *1

L
L
X
X
X
Clock
Suspend
Clock Suspend Mode Exit

L
H
X
X
Idle
Auto-refresh Command *2
REF
H
H
L
L
SELF
H
L
L
L
L
H
X
X
X
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
H
L
L
H
H
H
X
X
X
H
L
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
L H
H
X
V = Valid, L = Logic Low, H = Logic High, X = either L or H,
n = state at current clock cycle, n−1 = state at 1 clock cycle before n.
X
X
X
X
X
Bank Active
Idle
Function
Clock Suspend Mode
Entry *1
2, 3
Self-refresh Entry * *
Self Refresh Self-refresh Exit *4
Idle
Power Down Entry *3
Power Down Power Down Exit
SELFX
PD

XCS XRAS XCAS XWE BA
*1 : CSUS command requires that at least one bank is active. Refer to “■STATE DIAGRAM”.
*2 : REF and SELF commands should be issued only after all banks have been precharged (PRE or PALL command).
Refer to “■STATE DIAGRAM”.
*3 : SELF and PD commands should be issued only after the last read data have been appeared on DQ.
*4 : CKE should be held High during tREFC.
Notes: • TBST,BME and DSE should be held Low.
• S16 should be held VIH, and S32 should be held VIL.
• All commands assume no CSUS command on previous rising edge of clock.
• All commands assumed to be valid state transition.
• All inputs are latched on the rising edge of clock.
9
MB81ES171625/173225-15-X
4. Operation Command Table (Applicable to single bank)
Current
State
Idle
Bank Active
Read
XCS XRAS XCAS XWE
Addr
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
NOP
L
L
H
L
AP
PALL
NOP *1
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA Begin Read; Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
Precharge
L
L
H
L
AP
PALL
Precharge *1
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, New Read;
Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, Start Write;
Determine AP *4
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
Terminate Burst, Precharge → Idle
L
L
H
L
AP
PALL
Terminate Burst, Precharge → Idle *1
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
NOP
NOP *1
Illegal *2
Bank Active after tRCD
Auto-refresh or Self-refresh *3, *5
Mode Register Set
(Idle after tRSC) *3, *6
NOP
Begin Write; Determine AP
Illegal *2
Illegal
Continue Burst to End → Bank Active
Burst Stop → Bank Active
Illegal *2
Illegal
(Continued)
10
MB81ES171625/173225-15-X
Current
State
Write
Read with
Autoprecharge
Write with
Autoprecharge
XCS XRAS XCAS
XWE
Addr
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, Start Read;
Determine AP *4
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, New Write;
Determine AP
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
Terminate Burst, Precharge → Idle
L
L
H
L
AP
PALL
Terminate Burst, Precharge → Idle *1
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
Continue Burst to End → Precharge
→ Idle
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
L
L
H
L
AP
PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
Continue Burst to End → Precharge
→ Idle
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
L
L
H
L
AP
PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
Continue Burst to End → Bank Active
Burst Stop → Bank Active
Illegal *2
Illegal
Illegal *2
Illegal
Illegal *2
Illegal
(Continued)
11
MB81ES171625/173225-15-X
Current
State
Precharging
Bank
Activating
Refreshing
XCS XRAS XCAS
XWE
Addr
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
NOP *7
L
L
H
L
AP
PALL
NOP *1
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
L
L
H
L
AP
PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
X
X
READ/READA/
WRIT/WRITA
L
L
H
X
X
ACTV/
PRE/PALL
L
L
L
X
X
REF/SELF/
MRS
Idle after tRP
Illegal *2
Illegal
Bank Active after tRCD
Bank Active after tRCD *1
Illegal *2
Illegal
Idle after tREFC
Illegal
(Continued)
12
MB81ES171625/173225-15-X
(Continued)
Current
State
Mode
Register
Setting
XCS
XRAS XCAS
XWE
Addr
Command
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
X
X
READ/READA/
WRIT/WRITA
X
ACTV/PRE/
PALL/REF/SELF/
MRS
L
L
X
X
Function
Idle after tRSC
Illegal
ABBREVIATIONS
L = Logic Low, H = Logic High, X = either L or H
RA = Row Address
BA = Bank Address
CA = Column Address AP = Auto Precharge
*1: Entry may affect other bank.
*2: Illegal to the bank in specified state; entry may be legal to the bank specified by BA, depending on the state of
that bank.
*3: Illegal if any bank is not idle.
*4: Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to “11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)” and “12. WRITE to READ Timing
(Example @ CL = 1, BL = 4)” in “■TIMING DIAGRAMS.”
*5: SELF command should be issued only after the last read data has been appeared on DQ.
*6: MRS command should be issued only when all DQ are in High-Z.
*7: NOP in precharging or idle state. PRE may affect to the bank specified BA and AP.
Notes: • TBST,BME and DSE should be held Low.
• S16 should be held VIH, and S32 should be held VIL.
• All entries in “4. Operation Command Table” assume that CKE was High during the proceeding clock
cycle and the current clock cycle.
• Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence
will be asserted after power shut down.
• All commands assume no CSUS command on previous rising edge of clock.
• All commands are assumed to be valid state transitions.
• All inputs are latched on the rising edge of the clock.
13
MB81ES171625/173225-15-X
5. Command Truth Table for CKE
Current
State
Selfrefresh
Selfrefresh
Recovery
Power
Down
All
Banks
Idle
CKE
XCS XRAS XCAS
XWE
Addr
X
X
X
Invalid
X
X
X
X
L
H
H
H
X
Exit Self-refresh
(Self-refresh Recovery → Idle after tREFC)
H
L
H
H
L
X
L
H
L
H
L
X
X
L
H
L
L
X
X
X
L
L
X
X
X
X
X
Maintain Self-refresh
L
X
X
X
X
X
X
Invalid
H
H
H
X
X
X
X
H
H
L
H
H
H
X
H
H
L
H
H
L
X
H
H
L
H
L
X
X
H
H
L
L
X
X
X
H
L
X
X
X
X
X
Illegal *1
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
L
H
L
H
H
H
X
L
L
X
X
X
X
X
L
H
L
L
X
X
X
L
H
L
H
L
X
X
L
H
L
H
H
L
X
H
H
H
X
X
X
V
H
H
L
H
X
X
V
H
H
L
L
H
X
V
H
H
L
L
L
H
X
Auto-refresh
H
H
L
L
L
L
V
Refer to “4. Operation Command Table”.
H
L
H
X
X
X
X
H
L
L
H
H
H
X
H
L
L
H
H
L
X
H
L
L
H
L
X
X
H
L
L
L
H
X
X
H
L
L
L
L
H
X
Self-refresh *2
H
L
L
L
L
L
X
Illegal
L
X
X
X
X
X
X
Invalid
(n-1)
(n)
H
X
X
X
L
H
H
L
H
L
Function
Illegal
Idle after tREFC
Illegal
Exit Power Down Mode → Idle
Maintain Power Down Mode
Illegal
Refer to “4. Operation Command Table”.
Power Down
Illegal
(Continued)
14
MB81ES171625/173225-15-X
(Continued)
Current
State
Bank Active
Bank
Activating
Read/Write
Clock
Suspend
Any State
Other Than
Listed Above
CKE
XCS XRAS XCAS XWE
Addr
Function
X
X
Refer to “4. Operation Command Table”.
X
X
X
Begin Clock Suspend next cycle
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to “4. Operation Command Table”.
H
L
X
X
X
X
X
Illegal
(n-1)
(n)
H
H
X
X
X
H
L
X
X
L
X
X
H
X
L
Invalid
V = Valid, L = Logic Low, H = Logic High, X = either L or H
*1: CKE should be held High for tREFC period.
*2: SELF command should be issued only after the last data has been appeared on DQ.
Notes: • TBST,BME and DSE should be held Low.
• S16 should be held VIH, and S32 should be held VIL.
• All entries in “COMMAND TRUTH TABLE FOR CKE” are specified at CKE (n) state and CKE input from
CKE (n−1) to CKE (n) state must satisfy the corresponding setup and hold time for CKE.
15
MB81ES171625/173225-15-X
■ FUNCTIONAL DESCRIPTION
1. SDR I/F FCRAM Basic Function
Three major differences between SDR I/F FCRAMs and conventional DRAMs are : synchronized operation,
burst mode, and mode register.
The synchronized operation is the fundamental difference. SDR I/F FCRAM uses a clock input for synchronization, while DRAM is basically asynchronous memory although it has been using two clocks, XRAS and XCAS.
Each operation of DRAM is determined by their timing phase differences while each operation of SDR I/F FCRAM
is determined by commands and all operations are referenced to a rising edge of a clock.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a
column address for the first access is set, following addresses are automatically generated by the internal column
address counter.
The mode register is to configure SDR I/F FCRAM operation and function into desired system conditions.
“■MODE REGISTER TABLE” shows how SDR I/F FCRAM can be configured for system requirements by mode
register programming.
The program to the mode resister should be excuted after all banks are precharged.
2. FCRAMTM
MB81ES171625/173225 utilizes FCRAM core technology. FCRAM is an acronym for Fast Cycle Random Access
Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
3. Clock (CLK) and Clock Enable (CKE)
All input and output signals of SDR I/F FCRAM use register type buffers. CLK is used as a trigger for the register
and internal burst counter increment. All inputs are latched by a rising edge of CLK. All outputs are validated by
a rising edge of CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input
during active cycle, the next clock will be internally masked. During idle state (all banks have been
precharged) , the Power Down mode (standby) is entered with CKE = Low and this will make extremely low
standby current.
4. Chip Select (XCS)
XCS enables all command inputs, XRAS, XCAS, XWE and address inputs. When XCS is High, command signals
are negated but internal operations such as a burst cycle will not be suspended. If such a control isn’t needed,
XCS can be tied to ground level.
5. Command Input (XRAS, XCAS and XWE)
Unlike a conventional DRAM, XRAS, XCAS and XWE do not directly imply SDR I/F FCRAM operations, such
as Row address strobe by XRAS. Instead, each combination of XRAS, XCAS, and XWE input in conjunction
with XCS input at the rising edge of the CLK determines SDR I/F FCRAM operations. Refer to “■FUNCTIONAL
TRUTH TABLE.”
6. Address Input (A12 to A0)
Address input selects an arbitrary location of each memory cell matrix, 524,288 (×16 bit) or 262,144 (×32 bit) .
A total of 19 ( × 16 bit) or 18 ( × 32 bit) address input signals are required to decode 13 bit Row addresses and
6 bit (×16 bit) or 5 bit (×32 bit) column addresses matrix. SDR I/F FCRAM adopts an address multiplexer in order
to reduce the pin count of the address line. At a Bank Active command (ACTV) , 13 bit Row addresses are
initially latched and the remainder of 6 bit ( × 16 bit) or 5 bit ( × 32 bit) Column addresses are then latched by a
Column address strobe command of either a Read command (READ or READA) or a Write command (WRIT
or WRITA) . A10 selects READ or READA, WRIT or WRITA and PRE or PALL.
16
MB81ES171625/173225-15-X
7. Bank Select (BA)
This SDR I/F FCRAM has two banks.
Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT
or WRITA) , and precharge commands (PRE or PALL) .
8. Data Inputs and Outputs (DQ15 to DQ0/DQ31 to DQ0)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input :
tRAC ; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.)
tCAC ; from the read command when tRCD is greater than tRCD (Min) at CL = 1.
tAC ; from the rising edge of clock after tRAC and tCAC.
The polarity of the output data is identical to that of input data. Data is valid between access time (determined
by the three conditions above) and the next positive clock edge (tOH) .
Refer to “■AC CHARACTERISTICS”.
9. Data I/O Mask (DQM1 to DQM0/DQM3 to DQM0)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and
when DQM = High is latched by a clock, input is masked at the same clock and output will be masked at CL later
while internal burst counter will increment by one or will go to the next stage depending on the burst type.
10. Burst Mode Operation
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row
address and by automatically strobing column address. Access time and cycle time of Burst mode is specified
as tCAC/tAC and tCK, respectively. The internal column address counter operation is determined by a mode register
which defines burst type and the burst count length of 1, 2, 4, 8 bits of boundary or full column. In order to
terminate or move from the current burst mode to the next stage while the remaining burst count is more than
1, the following combinations will be required :
(1) Burst Type
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential
mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns
+1 to the previous (or initial) address until reaching the end of boundary address and then wraps around to the
least significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A0 through A2. If the
first access of column address is even (0) , the next address will be odd (1) , or vice-versa.
(2) Burst Mode Termination and Method of Next Stage Set
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Read Command
Burst Read
Burst Write
Burst Write
Burst Write
Write Command
Burst Write
Burst Read
Read Command
Burst Read
Precharge
Precharge Command
Burst Write
Precharge
Precharge Command
1st Step
Mask Command (Normally 3 clock cycles)
2nd Step
Write Command after lOWD
17
MB81ES171625/173225-15-X
(3) Counter Operation of Sequential Mode and lnterleave Mode
Starting Column Address
Burst
Sequential Mode
Length
A1
A0
A2
2
4
8
Interleave Mode
X
X
0
0−1
0−1
X
X
1
1−0
1−0
X
0
0
0−1−2−3
0−1−2− 3
X
0
1
1−2−3−0
1−0−3−2
X
1
0
2−3−0−1
2−3−0−1
X
1
1
3−0−1−2
3−2−1−0
0
0
0
0−1−2−3−4−5−6−7
0−1−2−3−4−5−6−7
0
0
1
1−2−3−4−5−6−7−0
1−0−3−2−5−4−7−6
0
1
0
2−3−4−5−6−7−0−1
2−3−0−1−6−7−4−5
0
1
1
3−4−5−6−7−0−1−2
3−2−1−0−7−6−5−4
1
0
0
4−5−6−7−0−1−2−3
4−5−6−7−0−1−2−3
1
0
1
5−6−7−0−1−2−3−4
5−4−7−6−1−0−3−2
1
1
0
6−7−0−1−2−3−4−5
6−7−4−5−2−3−0−1
1
1
1
7−0−1−2−3−4−5−6
7−6−5−4−3−2−1−0
11. Full Column Burst and Burst Stop Command (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full
column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address,
then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read
(READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge
option is illegal during the full column burst operation.
BST command is applicable to terminate the burst operation. If BST command is asserted during the burst mode,
its operation is terminated immediately and the internal state moves to Bank Active.
When a read mode is interrupted by BST command, the output will be in High-Z.
For the detailed rule, please refer to “8. Read Interrupted by Burst Stop (Example @ BL = Full Column)” in
“■TIMING DIAGRAMS.”
When a write mode is interrupted by BST command, the data to be applied at the same time with BST command
will be ignored.
12. Precharge and Precharge Option (PRE, PALL)
SDR I/F FCRAM memory core is the same as a conventional DRAM’s, requiring precharge and refresh operations. Precharge rewrites the bit line and reset the internal Row address line and is executed by the Precharge
command (PRE) . With the Precharge command, SDR I/F FCRAM will automatically be in standby state after
precharge time (tRP) .
The precharged bank is selected by combination of AP and BA when the Precharge command is asserted. If
AP = High, all banks are precharged regardless of BA (PALL) . If AP = Low, a bank to be selected by BA is
precharged (PRE) .
The auto-precharge enters precharge mode at the end of burst mode of read or write without the Precharge
command assertion.
This auto precharge is entered by AP = High when a read or write command is asserted. Refer to “■FUNCTIONAL
TRUTH TABLE.”
18
MB81ES171625/173225-15-X
13. Auto-Refresh (REF)
Auto-refresh uses the internal refresh address counter. SDR I/F FCRAM Auto-refresh command (REF) generates
the Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the Auto-refresh
command. The Auto-refresh command should also be asserted every 1.95 µs or a total 2048 refresh commands
within a 4 ms period.
14. Self-Refresh Entry (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh function until cancelled by SELFX.
Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF) . Once
SDR I/F FCRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or
low level state) and outputs will be in High-Z state. During a self-refresh mode, CKE = Low should be maintained.
SELF command should be issued only after the last read data has been appeared on DQ.
Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within
1 ms prior to the self-refresh mode entry.
15. Self-Refresh Exit (SELFX)
To exit the Self-refresh mode, apply minimum tSI after CKE brought high, and then the No operation command
(NOP) or the Deselect command (DESL) should be asserted within one tREFC period. CKE should be held High
within one tREFC period after tSI. Refer to “16. Self-Refresh Entry and Exit Timing” in “■TIMING DIAGRAMS” for
the detail.
It is recommended to assert an Auto-refresh command just after the tREFC period to avoid the violation of refresh
period.
Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1
ms after the Self-refresh exit.
16. Mode Register Set (MRS)
The mode register of SDR I/F FCRAM provides a variety of operations. The register consists of 3 operation
fields; Burst Length, Burst Type, and CAS latency. Refer to “■MODE REGISTER TABLE.”
The mode register can be programmed by the Mode Register Set command (MRS) . Each field is set by the
address line. Once a mode register is programmed, the contents of the register will be held until re-programmed
by another MRS command (or part loses power) . MRS command should be issued only when DQ is in High-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDR I/F FCRAM. Refer to “17. Power-Up Initialization”.
17. Power-Up Initialization
SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following Power
On Sequence to execute read or write operation.
1.
Apply the power and start the clock. Attempt to maintain either NOP or DESL command at the input.
2.
Maintain stable power, stable clock, and NOP condition for a minimum of 500 µs.
3.
Precharge all banks by Precharge (PRE) or Precharge All command (PALL) .
4.
Assert minimum of 2 Auto-refresh commands (REF) .
5.
Program the mode register by Mode Register Set command (MRS) .
In addition, it is recommended that DQM and CKE track VDD to insure that output is in High-Z state. The Mode
Register Set command (MRS) can be set before 2 Auto-refresh commands (REF) . It is possible to excute 5
before 4.
19
MB81ES171625/173225-15-X
■ STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
MRS
SELF
MODE
REGISTER
SET
SELF
REFRESH
SELFX
IDLE
REF
CKE\(PD)
CKE
AUTO
REFRESH
ACTV
POWER
DOWN
CKE\(CSUS)
BANK
ACTIVE
SUSPEND
BANK
ACTIVE
CKE
BST
BST
READ
WRIT
READ
WRIT
WRITA
CKE\(CSUS)
READ
WRITE
CKE
READA
CKE\(CSUS) WRITE WITH
AUTO
CKE
PRECHARGE
PRE or
PALL
POWER
ON
POWER
APPLIED
PRE or PALL
WRITA
CKE
PRE or
PALL
PRECHARGE
DEFINITION OF ALLOWS
Manual
Input
READ
SUSPEND
READA
READ WITH
AUTO
PRECHARGE
Note: CKE\ means CKE goes Low-level from High-level.
20
CKE\(CSUS)
READ
WRIT
WRITA
WRITE
SUSPEND
READA
PRE or
PALL
WRITE
SUSPEND
Automatic
Sequence
CKE\(CSUS)
CKE
READ
SUSPEND
MB81ES171625/173225-15-X
■ BANK OPERATION COMMAND TABLE
• Minimum Clock Latency or Delay Time for Single Bank Operation
Second
command
(same
bank)
MRS
ACTV
tRSC
tRSC
READ READA
WRIT
WRITA
PRE
PALL
REF
SELF
BST
tRSC
tRSC
tRSC
tRSC
tRSC
First
command
MRS
tRCD
ACTV
1
READ
READA
*1, *2
BL +
tRP
tRCD
tRCD
tRCD
tRAS
tRAS
1
1
*4
1
*4
1
*3
1
*3
1
1
*3
BL +
tRP
*3
BL +
tRP
*3
*3
tDPL
tDPL
*1
BL +
tRP
tWR
WRIT
tWR
1
1
*1
BL +
tRP
*1
BL +
tRP
*1
BL +
tRP
1
*1, *2
BL-1
+ tDAL
*1
BL-1
+ tDAL
*3
BL-1
+ tDAL
*3
BL-1
+ tDAL
*1
BL-1
+ tDAL
*1
BL-1
+ tDAL
*1
BL-1
+ tDAL
PRE
*1, *2
tRP
tRP
1
*3
1
*1
tRP
*1, *5
tRP
1
PALL
*2
tRP
tRP
1
1
tRP
*5
tRP
1
REF
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
SELFX
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
WRITA
*1: Assume all banks are in idle state.
*2: Assume output is in High-Z state.
*3: Assume tRAS (Min) is satisfied.
*4: Assume no I/O conflict.
*5: Assume the last data has been appeared on DQ.
Illegal Command.
21
MB81ES171625/173225-15-X
• Minimum Clock Latency or Delay Time for Multi Bank Operation
Second
command
(other
bank)
*4
MRS
ACTV
tRSC
tRSC
*4
*4
WRIT
WRITA
*4
READ READA
PRE
PALL
REF
SELF
BST
tRSC
tRSC
tRSC
tRSC
tRSC
*6
First
command
MRS
*1
ACTV
*6
1
*6
1
*6
1
*5, *6
1
tRAS
*1, *3
1
1
1
*8
1
*8
1
*5
1
*5
1
*1, *3
1
*5
1
*5
1
*5, *8
1
*5, *8
1
*5
1
*5
BL +
tRP
*1, *3
1
1
1
1
1
*5
1
tRRD
READ
READA
*6
1
*1, *2
BL +
tRP
WRIT
1
*1
BL +
tRP
*1
BL +
tRP
*5
*1
BL +
tRP
1
tDPL
WRITA
*1, *2
BL-1
+ tDAL
*1, *3
1
*5
1
*5
1
*5
1
*5
1
*5
1
*5
BL-1
+ tDAL
*1
BL-1
+ tDAL
*1
BL-1
+ tDAL
*1
BL-1
+ tDAL
PRE
*1, *2
tRP
*1, *3
1
*6
1
*6
1
*6
1
*6
1
*5, *6
1
*6
1
*1
tRP
*1, *7
tRP
1
PALL
*2
tRP
tRP
1
1
tRP
*7
tRP
1
REF
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
SELFX
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
*1: Assume all banks are in idle state.
*2: Assume output is in High-Z state.
*3: tRRD (Min) of other bank (the second command will be asserted) is satisfied.
*4: Assume other bank is in active, read or write state.
*5: Assume tRAS (Min) is satisfied.
*6: Assume other banks are not in READA/WRITA state.
*7: Assume the last data has been appeared on DQ.
*8: Assume no I/O conflict.
Illegal Command.
22
1
MB81ES171625/173225-15-X
■ MODE REGISTER TABLE
MODE REGISTER SET
A11
A10
BA
A12
A9
0 or 1
A8*2
A7*2
0
0
A6
A5
A4
A3
CL
A6
A5
A4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
1
2
Reserved
Reserved
Reserved
Reserved
Reserved
A2
BT
A1
A0
ADDRESS
MODE
REGISTER
BL
A2 A1
A0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
Burst Length
BT = 0
BT = 1 *1
1
2
4
8
Reserved
Reserved
Reserved
Full Column
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
A3
Burst Type
0
1
Sequential
Interleave
*1: BL = 1 and Full Column are not applicable to the interleave mode.
*2: A7 and A8 = 1 are reserved for vender test.
23
MB81ES171625/173225-15-X
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Voltage of VCC Supply Relative to VSS
VDD, VDDQ
−0.5
+3.0
V
Voltage at Any Pin Relative to VSS
VIN, VOUT
−0.5
+3.0
V
Short Circuit Output Current
IOUT
−13
+13
mA
Storage Temperature
TSTG
−55
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter
Symbol
Supply Voltage*1
Input High Voltage *
2
Input Low Voltage *3
Ambient Temperature
4
Junction Temperature*
Value
Unit
Min
Typ
Max
VDD, VDDQ
1.65
1.8
1.95
V
VSS, VSSQ
0
0
0
V
VIH
VDDQ−0.4

VDDQ + 0.3
V
VIL
−0.3

0.4
V
TA
−40

+85
°C
Tj
−40

+125
°C
*1 : All voltages are referenced to VSS.
*2 : Overshoot limit: VIH (Max) =
3.0 V for pulse width ≤ 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
VIH
3.0 V
50% of pulse amplitude
VIH
VIH (Min)
VIL
*3 : Undershoot limit: VIL (Min) =
VSS –1.5 V for pulse width ≤ 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
Pulse width ≤ 5 ns
VIL (Max)
VIL
Pulse width ≤ 5 ns
50% of pulse amplitude
-1.5 V
*4 : The maximum junction temperature of FCRAM (Tj) should not be more than +125 °C.
Tj is represented by the power consumption of FCRAM (PFCRAM) and Logic LSI(PD),the thermal resistance of the
package(θja),and the maximum ambient temperature of the SiP(TAMax).
TjMax[ °C] = TAMax[ °C] + θja[ °C/W] × Σ PMax[W]
Σ PMax[W] = PFCRAM + PD
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
24
MB81ES171625/173225-15-X
■ CAPACITANCE
(f = 1 MHz, TA = + 25 °C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Input Capacitance, Except for CLK
CIN1
2.0

5.0
pF
Input Capacitance for CLK
CIN2
2.0

5.0
pF
I/O Capacitance
CI/O
2.0

5.0
pF
25
MB81ES171625/173225-15-X
■ DC CHARACTERISTICS
Parameter
(At recommended operating conditions unless otherwise noted.)
Value
Symbol
Condition
Unit
Min
Max
Output High Voltage
VOH(DC)
IOH = −2 mA
Output Low Voltage
VOL(DC)
VDDQ −0.2

V
IOL = 2 mA

0.2
V
Input Leakage Current (Any Input)
ILI
0 V ≤ VIN ≤ VDDQ;
All other pins not under
test = 0 V
−5
5
µA
Output Leakage Current
ILO
0 V ≤ VIN ≤ VDDQ;
Data out disabled
−5
5
µA
IDD1
Burst Length = 1,
tRC = Min for BL = 1,
tCK = Min,
One bank active,
Output pin open,
Addresses changed up to
one time during tCK (Min),
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VDDQ

30
mA
IDD2P
CKE = 0 V,
All banks idle, tCK = Min,
Power down mode,
VIL = 0 V,
VIH = VDDQ

1
mA
IDD2PS
CKE = 0 V, All banks idle,
CLK = VDDQ or 0 V,
Power down mode,
VIL = 0 V,
VIH = VDDQ

1
mA
IDD2N
CKE = VDDQ , All banks idle,
tCK = Min,
NOP command only,
Input signals (except to
CMD) are changed one
time during 30 ns,
VIL= 0 V,
VIH = VDDQ

4
mA
IDD2NS
CKE = VDDQ,
All banks idle,
CLK = VDDQ or 0 V,
Input signal are stable,
VIL= 0 V,
VIH = VDDQ

1
mA
Operating Current
(Average Power Supply Current)
Power Supply Current
(Precharge Standby Current)
(Continued)
26
MB81ES171625/173225-15-X
(Continued)
Parameter
Symbol
Average Power Supply Current
(Refresh Current #1)
Average Power Supply Current
(Refresh Current #2)
Value
Unit
Min
Max
IDD3P
CKE = 0 V,
Any bank active,
tCK = Min,
VIL = 0 V,
VIH = VDDQ

1
mA
IDD3PS
CKE = 0 V,
Any bank active,
CLK = VDDQ or 0 V,
VIL = 0 V,
VIH = VDDQ

1
mA
IDD3N
CKE = VDDQ,
Any bank active,
tCK = Min,
NOP command only,
Input signals (except to
CMD) are changed one
time during 30 ns,
VIL = 0 V,
VIH = VDDQ

10
mA
IDD3NS
CKE = VDDQ,
Any bank active,
CLK = VDDQ or 0 V,
Input signals are stable,
VIL = 0 V,
VIH = VDDQ

1
mA
IDD4
tCK = Min,
Burst Length = 4,
Output pin open,
All-banks active,
Gapless data,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VDDQ

40
mA
IDD5
Auto-refresh;
tCK = Min,
tREFC = Min,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VDDQ

73
mA
IDD6
Self-refresh;
CLK = VDDQ or 0 V,
CKE= 0 V,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VDDQ

5
mA
Power Supply Current
(Active Standby Current)
Average Power Supply Current
(Burst mode Current)
Condition
Notes: • All voltages are referenced to VSS and VSSQ.
• DC characteristics are measured after following “17. Power-Up Initialization” procedure in
“■FUNCTIONAL DESCRIPTION”.
• IDD depends on output termination, load conditions, clock rate, number of address and/or command change
within certain period. The specified values are obtained with the output open.
27
MB81ES171625/173225-15-X
■ AC CHARACTERISTICS
(1) Basic AC Characteristics
Parameter
(At recommended operating conditions unless otherwise noted.)
Value
Symbol
Unit
Min
Max
CL = 1
tCK1
30
CL = 2
tCK2
15
tCH
6

ns
tCL
6

ns
tSI
3

ns
tHI
2

ns
tRAC

57
ns
tCAC

27
ns
CL = 1
tAC1

27
ns
CL = 2
tAC2

12
ns
tLZ
0

ns
CL = 1
tHZ1
2.5
10
ns
CL = 2
tHZ2
2.5
10
ns
Output Hold Time *1, *3
tOH
2.5

ns
Time between Auto-Refresh command interval *2
tREFI

1.95
µs
Time between Refresh
tREF

4
ms
tT
0.5
5
ns
Clock Period
Clock High Time *1
Clock Low Time *
1
Input Setup Time *
1
Input Hold Time except for CKE *1
XRAS Access Time *2
1, 3
XCAS Access Time * *
Access Time from Clock (tCK = Min) *1, *3, *4
Output in Low-Z *1
Output in High-Z *1, *5
Transition Time
1000
ns
ns
*1: If input signal transition time (tT) is longer than 1 ns; [ (tT / 2) − 0.5] ns should be added to tCAC (Max) , tAC (Max) ,
tHZ (Max) and tSI (Min) spec values, [ (tT / 2) − 0.5] ns should be subtracted from tLZ (Min) , tHZ (Min) and tOH (Min)
spec values, and (tT − 1.0) ns should be added to tCH (Min) , tCL (Min) , tSI (Min) , and tHI (Min) spec values.
*2: This value is for reference only.
*3: Measured under AC test load circuit shown in “ (5) Measurement Condition of AC Characteristics (Load Circuit) ”.
*4: tAC also specifies the access time at burst mode except for first access at CL = 1.
*5: Specified where output buffer is no longer driven.
Notes: • AC characteristics are measured after following “17. Power-Up Initialization” procedure in “■FUNCTIONAL
DESCRIPTION”.
• AC characteristics assume tT = 1 ns ,10 pF of capacitive and 50 Ω of terminated load.
Refer to “ (5) Measurement Condition of AC Characteristics (Load Circuit) ”
• 0.9 V is the reference level for measuring timing of input/output signals.
• Transition times are measured between VIH (Min) and VIL (Max) . Refer to “(6) Setup, Hold and Delay Time”.
28
MB81ES171625/173225-15-X
(2) Base Values for Clock Count/Latency
Parameter
Symbol
Value
Min
Max
Unit
XRAS Cycle Time *
tRC
75

ns
XRAS Precharge Time
tRP
30

ns
XRAS Active Time
tRAS
45
110000
ns
XRAS to XCAS Delay Time
tRCD
30

ns
Write Recovery Time
tWR
15

ns
XRAS to XRAS Bank Active Delay Time
tRRD
15

ns
Data-in to Precharge Lead Time
tDPL
15

ns
Data-in to Active/ Refresh Command Period
tDAL
1cyc+ tRP

ns
Refresh Cycle Time
tREFC
75

ns
Mode Resister Set Cycle Time
tRSC
45

ns
*: tRC (Min) is not sum of tRAS (Min) and tRP (Min) . Actual clock count of tRC (lRC) must satisfy tRC (Min) , tRAS (Min)
and tRP (Min) .
(3) Clock Count Formula
Clock ≥
Base Value
Clock Period
(Round up to a whole number)
Note: All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula : clock count equals base value divided
by clock period (round up to a whole number) .
29
MB81ES171625/173225-15-X
(4) Latency - Fixed Values
(The latency values on these parameters are fixed regardless of clock period.)
Parameter
Symbol
Value
Unit
CKE to Clock Disable
CKE
1
cycle
CL = 1
DQZ1
1
cycle
CL = 2
DQZ2
2
cycle
DQM to Input Data Delay
DQD
0
cycle
Last Output to Write Command Delay
OWD
2
cycle
Write Command to Input Data Delay
DWD
0
cycle
CL = 1
ROH1
1
cycle
CL = 2
ROH2
2
cycle
CL = 1
BSH1
1
cycle
CL = 2
BSH2
2
cycle
XCAS to XCAS Delay (Min)
CCD
1
cycle
XCAS Bank Delay (Min)
CBD
1
cycle
DQM to Output in High-Z
Precharge to Output in High-Z Delay
Burst Stop Command to Output in High-Z Delay
(5) Measurement Condition of AC Characteristics (Load Circuit)
R1 = 50 Ω
Output
0.9 V
CL = 10 pF
30
MB81ES171625/173225-15-X
(6) Setup, Hold and Delay Time
tCK
tCH
tCL
1.4 V
CLK
0.9 V
0.4 V
tSI
tHI
1.4 V
Input
(Control,
Addr. & Data)
0.9 V
VALID
0.4 V
tHZ1 or tHZ2
tCAC, tAC1 or tAC2
tOH
tLZ
VOH
Output
VALID
0.9 V
VOL
Notes: • Reference level of input/output signal is 0.9 V.
• Access time is measured at 0.9 V.
• AC characteristics are also measured in this condition.
(7) Delay Time for Power Down Exit
CLK
H or L
tSI
1 clock (Min)
CKE
Command
H or L
NOP
ACTV
31
MB81ES171625/173225-15-X
(8) Pulse Width
CLK
tRC, tRP, tRAS, tRCD, tWR, tREFI, tREFC,
Input
(Control)
tDPL, tDAL, tRSC, tRRD
COMMAND
COMMAND
: INVALID
Notes : • These parameters are a limit value of the rising edge of the clock from one command input to
the next input.
• Measurement reference voltage is 0.9 V.
(9) Access Time
CLK
tRAC
XRAS
tRCD
tCAC
XCAS
tAC
tAC
tAC
1 clock at CL = 2
DQ
(Output)
32
Q (Valid)
Q (Valid)
Q (Valid)
MB81ES171625/173225-15-X
■ TIMING DIAGRAMS
1. Clock Enable - READ and WRITE Suspend (@ BL = 4)
CSUS command
CSUS command
CLK
tSI
tHI
tSI
tHI
tSI
tHI
CKE
CKE
*1
(1 clock)
CLK
(Internal)
CKE
1
(1 clock)*
*2
*2
DQ
(Read)
Q1
DQ
(Write)
D1
*1: The latency of CKE (
Q2
NOT *3
WRITTEN
*2
(NO CHANGE)
D2
Q3
*2
(NO CHANGE)
NOT *3
WRITTEN
Q4
D3
D4
) is one clock.
CKE
*2: During the read mode, burst counter will not be increased/decreased at the next clock of CSUS command.
Output data remains the same data.
*3: During the write mode, data at the next clock of CSUS command is ignored.
2. Clock Enable - Power Down Entry and Exit
CLK
tSI
1 clock (Min)
CKE
Command
1
NOP *
PD (NOP)
H or L
2
NOP *
3
ACTV *
tREF (Max)
*1: The Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2: The NOP command should be asserted in conjunction with CKE.
*3: The ACTV command can be latched after tSI + 1 clock (Min) .
33
MB81ES171625/173225-15-X
3. Column Address to Column Address Input Delay
CLK
XRAS
CCD
tRCD (Min)
(1 clock)
CCD
CCD
CCD
XCAS
Address
ROW
ADDRESS
COLUMN
ADDRESS
Note : XCAS to XCAS delay (
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
) can be one or more clock period.
CCD
4. Different Bank Address Input Delay
CLK
tRRD (Min)
XRAS
CBD
tRCD (Min) or more
(1 clock)
CBD
XCAS
tRCD (Min)
Address
BA
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Note : XCAS Bank delay (
34
) can be one or more clock period.
CBD
MB81ES171625/173225-15-X
5. DQM - Input Mask and Output Disable (@ CL = 2, BL = 4)
CLK
DQM
(@ Read)
DQZ2
DQ
(@ Read)
Q1
High-Z
Q2
Q4
End of burst
DQM
(@ Write)
DQD
DQ
(@ Write)
D1
(same clock)
MASKED
D3
D4
End of burst
6. Precharge Timing (Applied to the Same Bank)
CLK
tRAS (Min)
Command
ACTV
PRE
Note : PRE means ‘PRE’ or ‘PALL’.
35
MB81ES171625/173225-15-X
7. READ Interrupted by Precharge (Example @ CL = 2, BL = 4)
CLK
Command
PRE
ROH2
DQ
Command
(2 clocks)
High-Z
Q1
PRE
ROH2
DQ
Q1
Command
(2 clocks)
Q2
High-Z
PRE
ROH2
DQ
Q1
Q2
Command
(2 clocks)
Q3
High-Z
PRE
No effect (end of burst)
DQ
Q1
Note : In case of CL = 1, the ROH is 1 clock.
In case of CL = 2, the ROH is 2 clocks.
PRE means ‘PRE’ or ‘PALL’.
36
Q2
Q3
Q4
MB81ES171625/173225-15-X
8. READ Interrupted by Burst Stop (Example @ BL = Full Column)
CLK
Command
(CL = 1)
BST
BSH1
(1 clock)
High-Z
DQ
Qn − 2
Qn − 1
Command
(CL = 2)
Qn
BST
BSH2
Qn − 2
DQ
Qn − 1
(2 clocks)
Qn + 1
Qn
High-Z
9. WRITE Interrupted by Burst Stop (Example @ BL = 2)
CLK
BST
Command
DQ
LAST Dn
Command
Masked
by BST
37
MB81ES171625/173225-15-X
10. WRITE Interrupted by Precharge
CLK
tDPL (Min)
DQ
ACTV
PRE
Command
Dn − 1
LAST Dn
tRP (Min)
MASKED
by Precharge
Note : The precharge command (PRE) should be issued only after the tDPL of final data input is satisfied.
PRE means ‘PRE’ or ‘PALL’.
11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)
CLK
OWD
Command
DQM
(2 clocks)
READ
WRIT
*1
*2
DQZ2
*3
(2 clocks)
DWD
DQ
Q1
Masked
D1
(same clock)
D2
*1: The First DQM makes high-impedance state (High-Z) between the last output and the first input data.
*2: The Second DQM makes internal output data mask to avoid bus contention.
*3: The Third DQM in illustrated above also makes internal output data mask. If burst read ends (the final
data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus
contention.
38
MB81ES171625/173225-15-X
12. WRITE to READ Timing (Example @ CL = 1, BL = 4)
CLK
tWR (Min)
WRIT
Command
READ
DQM
tCAC (Max)
DQ
D1
D2
D3
Q1
Masked
by READ
tAC1
tAC1
Q2
tAC1
Q3
Notes: • READ command should be issued after tWR of the final data input is satisfied.
• The write data after READ command is masked by READ command.
13. READ with Auto-Precharge (Example @ CL = 2, BL = 2 Applied to same bank)
CLK
Command
ACTV
READA
NOP or DESL
ACTV
BL + tRP *
DQM
DQ
Q1
Q2
*: The Next ACTV command should be issued after BL + tRP from READA command.
39
MB81ES171625/173225-15-X
14. WRITE with Auto-Precharge (Example @ CL = 2, BL = 2 Applied to same bank)
CLK
tDAL (Min)
(BL − 1) + tDAL *
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM
DQ
D1
D2
*: The Next command should be issued after (BL − 1) + tDAL from WRITA command.
Notes: • If the final data is masked by DQM, the precharge does not start at the clock of the final data input.
• Once the auto precharge command is asserted, no new command within the same bank can be
issued.
• The Auto-precharge command can not be invoked at full column burst operation.
15. Auto-Refresh Timing
CLK
Command
REF *1
NOP *2
NOP *2
NOP *2
REF
tREFC (Min)
BA
H or L
NOP *2
Command *3
tREFC (Min)
H or L
BA
*1: All banks should be precharged prior to the first Auto-refresh command (REF) .
*2: Either NOP or DESL command should be asserted within tREFC period while Auto-refresh mode.
*3: Any activation command such as ACTV or MRS commands other than REF command should be asserted
after tREFC from the last REF command.
Note: Bank select is ignored at the REF command. The refresh address and bank select are selected by
the internal refresh counter.
40
MB81ES171625/173225-15-X
16. Self-Refresh Entry and Exit Timing
Entry
Exit
CLK
tSI
tSI (Min)
CKE
tREFC (Min) *4
Command
NOP *1
SELF
H or L
SELFX *2
NOP *3
Command
*1: The Precharge command (PRE or PALL) should be asserted if any bank is active prior to the Self-refresh
Entry command (SELF) .
*2: The Self-refresh Exit command (SELFX) is latched after tSI.
*3: Either NOP or DESL command can be used during tREFC period.
*4: CKE should be held high for at least one tREFC period after tSI.
17. Mode Register Set Timing
CLK
tRSC (Min)
Command
Address
MRS
MODE
NOP or DESL
ACTV
ROW
ADDRESS
Note : The Mode Register Set command (MRS) should be asserted only after all banks have been
precharged and DQ is in High-Z.
41
MB81ES171625/173225-15-X
■ ORDERING INFORMATION
Part number
42
Configuration
Shipping form
MB81ES171625-15WFKT-X
512 K word × 16 bit × 2 bank
wafer
MB81ES173225-15WFKT-X
256 K word × 32 bit × 2 bank
wafer
Remarks
MB81ES171625/173225-15-X
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
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Tel: +81-3-5322-3353
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
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Tel: +1-408-737-5600
Fax: +1-408-737-5999
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FUJITSU MICROELECTRONICS EUROPE GmbH
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D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
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FUJITSU MICROELECTRONICS ASIA PTE LTD.
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Singapore 556741
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F0306
 FUJITSU LIMITED Printed in Japan
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The contents of this document are subject to change without notice.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
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device based on such information, you must assume any
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function and schematic diagrams, shall not be construed as license
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