FUJITSU MB81EDS256445

FUJITSU MICROELECTRONICS
DATA SHEET
DS05-11456-1E
MEMORY Consumer FCRAMTM
CMOS
256M Bit (4 bank x 1M word x 64 bit)
Consumer Applications Specific Memory for SiP
MB81EDS256445
■ DESCRIPTION
The Fujitsu MB81EDS256445 is a CMOS Fast Cycle Random Access Memory (FCRAM*) with Low Power Double
Data Rate (LPDDR) SDRAM Interface containing 268,435,456 storages accessible in a 64-bit format.
MB81EDS256445 is suited for consumer application requiring high data band width with low power consumption.
* : FCRAM is a trademark of Fujitsu Microelectronics Limited, Japan
■ FEATURES
• 1 M word × 64 bit × 4 banks organization
• DDR Burst Read/Write Access Capability
-tCK = 4.6 ns Min / 216 MHz Max (Tj ≤ + 105 °C)
-tCK = 5 ns Min / 200 MHz Max (Tj ≤ + 125 °C)
• Low Voltage Power Supply: VDD = VDDQ + 1.7 V to + 1.95 V
• Junction Temperature:
TJ = − 10 °C to + 125 °C
• 1.8 V-CMOS compatible inputs
• Burst Length: 2, 4, 8, 16
• CAS latency: 2, 3, 4
• Clock Stop capability during idle periods
• Auto Precharge option for each burst access
• Configurable Driver Strength and Pre Driver Strength
• Auto Refresh and Self Refresh Modes
• Deep Power Down Mode
• Low Power Consumption
-IDD4R =300 mA Max @ 3.46 GByte/s
-IDD4W =330 mA Max @ 3.46 GByte/s
• 4 K refresh cycles / 4 ms (Tj ≤ +125 °C)
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
MB81EDS256445
■ PIN DESCRIPTIONS
Symbol
Type
CK, CK
Input
Clock
CKE
Input
Clock Enable
CS
Input
Chip Select
RAS
Input
Row Address Strobe
CAS
Input
Column Address Strobe
WE
Input
Write Enable
BA[1:0]
Input
Bank Address Inputs
A[11:0]
Input
Address Inputs
AP(A10)
Input
Auto Precharge Enable
DM[7:0] *1
Input
Input Data Mask Enable
DQ[63:0] *1, *2
I/O
Data Bus Input / Output
I/O
Data Strobe
DQS[7:0] *
2
Function
VDDQ, VDD
Supply
Power Supply
VSSQ, VSS
Supply
Ground
Row
A0 to A11
Column
A0 to A7
*1 : DM0, DM1, DM2, DM3, DM4, DM5, DM6 and DM7 correspond to DQ[7:0], DQ[15:8], DQ[23:16], DQ[31:24],
DQ[39:32], DQ[47:40], DQ[55:48] and DQ[63:56].
*2 : DQS0, DQS1, DQS2, DQS3, DQS4, DQS5, DQS6 and DQS7 correspond to DQ[7:0], DQ[15:8], DQ[23:16],
DQ[31:24], DQ[39:32], DQ[47:40], DQ[55:48] and DQ[63:56].
2
DS05-11456-1E
MB81EDS256445
1. Clock Inputs (CK and CK)
CK and CK are differential clock inputs. All address and control input signals are sampled on the rising edge of
CK. And the rising edge of CK and the rising edge of CK increment device internal address counter and drive
even and odd data input/out respectively.
tCK
CK
tCH
tDC
tCL
tDC
tCK
CK
tCH
tCL
2. Clock Enable (CKE)
CKE is a high active clock enable signal. When CKE = Low is latched at the rising edge of CK, the next CK rising
edge will be invalid. CKE controls power down mode and self refresh mode.
CK
CK
tIS
tIS
CKE
CK
(Internal)
3. Chip Select (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address inputs. CS = High disable command input
but internal operation such as burst cycle will not be suspended.
4. Command Inputs (RAS, CAS and WE)
The combination of RAS, CAS, and WE input in conjunction with CS at a rising edge of the CK define the
command for device operation. Refer to the “■COMMAND TRUTH TABLE”.
5. Bank Address Inputs (BA0, BA1)
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied.
DS05-11456-1E
3
MB81EDS256445
6. Address Inputs (A0 to A11)
Address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. Total twenty
address input signals are required to decode such a matrix. Row Address (RA) is input from A0 to A11 and
Column Address (CA) is input from A0 to A7. Row addresses are latched with ACTIVE (ACT or MACT) commands, and Column addresses and Auto Precharge (AP) bit are latched with Read (READ or READA) or Write
command (WRIT or WRITA).
• Command and address inputs setup and hold time
CK
tIS
tIH
Command
(CS, RAS, CAS, WE)
Address
tIPW
7. Input Data Mask (DM0 to DM7)
DM is an input mask signal for write data. Input data is masked when DM is sampled High on the both edges
of DQS along with input data. DM0, DM1, DM2, DM3, DM4, DM5, DM6 and DM7 correspond to DQ[7:0],
DQ[15:8], DQ[23:16], DQ[31:24], DQ[39:32], DQ[47:40], DQ[55:48] and DQ[63:56] respectively. Refer to the
“DQ/DQS/DM Correspondence Table”.
8. Data Bus Input / Output (DQ0 to DQ63)
DQ is data bus input / output signal.
9. Data Strobe (DQS0 to DQS7)
DQS is edge aligned with output read data and center aligned with input write data. DQS0, DQS1, DQS2, DQS3,
DQS4, DQS5, DQS6 and DQS7 correspond to DQ[7:0], DQ[15:8], DQ[23:16], DQ[31:24], DQ[39:32], DQ[47:40],
DQ[55:48] and DQ[63:56] respectively. Refer to the “DQ/DQS/DM Correspondence Table”.
• DQ/DQS/DM Correspondence Table
DQ
4
DQS
DM
DQ[7:0]
DQS0
DM0
DQ[15:8]
DQS1
DM1
DQ[23:16]
DQS2
DM2
DQ[31:24]
DQS3
DM3
DQ[39:32]
DQS4
DM4
DQ[47:40]
DQS5
DM5
DQ[55:48]
DQS6
DM6
DQ[63:56]
DQS7
DM7
DS05-11456-1E
MB81EDS256445
■ BLOCK DIAGRAM
VDDQ
CK
CK
CLOCK
BUFFER
VDD
To each block
VSS
CKE
VSSQ
ADDRESS
COUNTROLLER
MODE
REGISTER
CS
RAS
CAS
Bank3
Bank2
Bank1
Bank0
ADDRESS
BUFFER
X CONTROLLER
BA[1:0]
Y CONTROLLER
BURST
COUNTROLLER
A[11:0]
MEMORY
CELL
ARRAY
(1 M bit × 64)
COMMAND
DECODER
WE
MEMORY
CORE
CONTROLLER
READ
AMP
WRITE
AMP
DM[7:0]
DQS[7:0]
I/O
BUFFER
BUS
CONTROLLER
DQ[63:0]
DS05-11456-1E
5
MB81EDS256445
■ SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
SELF
DEEP
POWER
DOWN
SELFX
REF
DPD
AUTO
REFRESH
IDLE
PD
MRS
ACT
PDX
MODE
REGISTER
SET
POWER
DOWN
PD
BANK
ACTIVE
PDX
BST
BST
READ
WRIT
DPDX
ACTIVE
POWER
DOWN
READ
WRIT
WRITE
READ
WRITA
READA
WRITA
PRE
READA
WRITE WITH
AUTO
PRECHARGE
POWER
ON
PRE
PRE
READ WITH
AUTO
PRECHARGE
PRE
PRECHARGE
Automatic Sequence
POWER
APPLIED
Manual Input
Note: “■SIMPLIFIED STATE DIAGRAM” is based on the single bank operation.
State transition of multi bank operation are not described in all detail.
6
DS05-11456-1E
MB81EDS256445
■ FUNCTIONAL DESCRIPTION
1. Power Up Initialization
This device internal condition after power-up will be undefined. The following Power up initialization sequence
must be performed to start proper device operation.
1.
2.
3.
4.
5.
6.
Apply power (VDD should be applied before or in parallel with VDDQ) and start clock. Attempt to maintain
either NOP or DESL command at the input.
Maintain stable power, stable clock, and NOP or DESL condition for a minimum of 300 μs.
Precharge all banks by PRECHARGE (PRE) or PRECHARGE ALL (PALL) command.
Assert minimum of 2 AUTO REFRESH (REF) commands.
Program the Mode Register by MODE REGISTER SET (MRS) command.
Program the Extended Mode Register by MODE REGISTER SET (MRS) command.
In addition, CKE must be High to ensure that output is High-Z state. The Mode Register and Extended Mode
Register can be set before 2 Auto-refresh commands (REF).
2. Mode Register
The Mode Register is used to configure the type of device function among optional features. This device has 2
Mode Registers, Mode Register and Extended Mode Register. Mode Registers can be programmed by MODE
REGISER SET (MRS) command. Refer to the “Mode Register Table” in
“■FUNCTIONAL DESCRIPTION”.
DS05-11456-1E
7
MB81EDS256445
Mode Register Table
Mode Register
A6
A5
A4
BA0
A11
A10
A9
A8
A7
0
0
0
0
0
0
0
A6
A5
A4
CAS Latency
A2
A1
A0
Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
4
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
4
8
16
Reserved
Reserved
Reserved
CL
A3
A2
0
A1
A0
ADDRESS
BA1
Mode Register
BL
Extended Mode Register
8
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ADDRESS
0
1
0
0
0
0
0
PDS
DS
0
0
0
0
0
Extended Mode
Register
A6
Pre Driver Strength
A5
Driver Strength
0
1
Fast
Slow
0
1
Normal
Weak
DS05-11456-1E
MB81EDS256445
3. Burst Length (BL)
Burst Length (BL) is the number of word to be read or write as the result of a single READ or WRITE command.
It can be set on 2, 4, 8, 16 words boundary through Mode Register. The burst type is sequential that is incremental
decoding scheme within a boundary address to be determined by burst length. Device internal address counter
assigns +1 to the previous address until reaching the end of boundary address and then wrap round to least
significant address ( = 0).
Starting Column Address
Burst
Burst Address Sequence
Length
(Hexadecimal)
A3
A2
A1
A0
2
4
8
16
DS05-11456-1E
X
X
X
0
0-1
X
X
X
1
1-0
X
X
0
0
0-1-2-3
X
X
0
1
1-2-3-0
X
X
1
0
2-3-0-1
X
X
1
1
3-0-1-2
X
0
0
0
0-1-2-3-4-5-6-7
X
0
0
1
1-2-3-4-5-6-7-0
X
0
1
0
2-3-4-5-6-7-0-1
X
0
1
1
3-4-5-6-7-0-1-2
X
1
0
0
4-5-6-7-0-1-2-3
X
1
0
1
5-6-7-0-1-2-3-4
X
1
1
0
6-7-0-1-2-3-4-5
X
1
1
1
7-0-1-2-3-4-5-6
0
0
0
0
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0
0
0
1
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0
0
0
1
0
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1
0
0
1
1
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2
0
1
0
0
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3
0
1
0
1
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4
0
1
1
0
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5
0
1
1
1
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6
1
0
0
0
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
1
0
0
1
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8
1
0
1
0
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9
1
0
1
1
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A
1
1
0
0
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B
1
1
0
1
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C
1
1
1
0
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D
1
1
1
1
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E
9
MB81EDS256445
4. CAS Latency (CL)
CAS Latency (CL) is the delay between READ command being registered and first read data becoming available
during read operation. First read data will be valid after (CL-1) × tCK + tAC from the CK rising edge where Read
command being latched.
5. Driver Strength (DS)
Driver Strength (DS) is to adjust the driver strength of data output.
6. Pre Driver Strength (PDS)
Pre Driver Strength (PDS) is to adjust the transition time of the data output without changing the output driver
impedance.
10
DS05-11456-1E
MB81EDS256445
■ COMMAND TRUTH TABLE
1) Basic Command Truth Table
Symbol
CS
RAS
CAS
WE
BA
A10
(AP)
A[9:0],
A11
DESL
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
BST
L
H
H
L
X
X
X
READ
L
H
L
H
V
L
CA
READA
L
H
L
H
V
H
CA
WRIT
L
H
L
L
V
L
CA
WRITA
L
H
L
L
V
H
CA
ACT
L
L
H
H
V
PRE
L
L
H
L
V
L
X
PRECHARGE ALL BANKS * *
PALL
L
L
H
L
X
H
X
AUTO REFRESH *6
REF
L
L
L
H
X
X
X
MODE REGISTER SET *7
MRS
L
L
L
L
V
V
V
Command
DESELECT *1
NO OPERATION *1
2, 3
BURST TERMINATE * *
3, 4
READ * *
READ with Auto-precharge *3, *4
3, 4
WRITE * *
3, 4
WRITE with Auto-precharge * *
BANK ACTIVE *4, *5
5, 6
PRECHARGE SINGLE BANK * *
5, 6
RA
Note: V = Valid, L = VIL, H = VIH, X can be either VIL or VIH, RA = Row Address, CA = Column Address
All commands are assumed to be valid state transitions and latched on the rising edge of CK. CKE assume
to be kept High.
*1: NOP and DESL commands have the same functionality. Unless specifically noted, NOP will represent both NOP
and DESL command in later description.
*2: When the current state is IDLE and CKE=L, BST command will represent DPD command. Refer to the “■CKE
COMMAND TRUTH TABLE”.
*3: BST command can be applied to READ or WRIT. READA and WRITA must not be terminated by BST command.
*4: READ, READA, WRIT and WRITA commands can be issued after the corresponding bank has been activated.
Refer to the “■SIMPLIFIED STATE DIAGRAM”.
*5: ACT command can be issued after corresponding bank has been precharged by PRE or PALL command.
Refer to the “■ SIMPLIFIED STATE DIAGRAM”.
*6: REF command can be issued after all banks have been precharged by PRE or PALL command. Refer to the
“■SIMPLIFIED STATE DIAGRAM”.
*7: MRS command can be issued after all banks have been precharged and all DQ are in High-Z. Mode Register
and Extended Mode Register are selected through BA input. Mode Register and Extended Mode Register must
be set by MRS command after power up.
DS05-11456-1E
11
MB81EDS256445
2) CKE Command Truth Table
Command
SELF REFRESH ENTRY *1
SELF REFRESH EXIT *2
POWER DOWN ENTRY *1
POWER DOWN EXIT
DEEP POWER DOWN ENTRY *1
DEEP POWER DOWN EXIT
Symbol
CKE
n-1
n
SELF
H
L
SELFX
L
H
PD
PDX
H
L
CS
RAS CAS
WE
BA
A[11:0]
L
L
L
H
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
H
DPD
H
L
DPDX
L
H
Note: V = Valid, L = VIL, H = VIH, X can be either VIL or VIH
*1: SELF and DPD commands can be issued after all banks have been precharged and all DQ are in High-Z.
*2: CKE should be held High more than tREFC period after SELFX.
12
DS05-11456-1E
MB81EDS256445
3) Single Bank Operation
Current State
CS RAS CAS WE
IDLE
BANK ACTIVE
Address
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF
Auto Refresh *3
L
L
L
L
MODE
MRS
Mode Register Set *3, *4
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
Start Read; Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Start Write; Determine AP
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF
L
L
L
L
MODE
MRS
NOP
Illegal *1
Bank Active
NOP *2
NOP
Illegal *1
Precharge; Determine
Precharge Type
Illegal
(Continued)
DS05-11456-1E
13
MB81EDS256445
Current State
READ
WRITE
CS
RAS CAS WE
Address
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
Interrupt burst read by new
burst read; Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
Interrupt burst write by new
burst read; Determine AP *5
L
H
L
L
BA, CA, AP
WRIT/WRITA
Interrupt burst write by new
burst write; Determine AP
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF
L
L
L
L
MODE
MRS
NOP
Burst Terminate →
BANK ACTIVE
Illegal *1
Terminate burst read by
precharge → IDLE
Illegal
NOP
Burst terminate →
BANK ACTIVE
Illegal *1
Illegal
(Continued)
14
DS05-11456-1E
MB81EDS256445
Current State
READ WITH
AUTO
PRECHARGE
WRITE WITH
AUTO PRECHARGE
CS
RAS CAS WE
Address
Command
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF
L
L
L
L
MODE
MRS
Function
NOP
Illegal
Illegal *1
Illegal
NOP
Illegal
Illegal *1
Illegal
(Continued)
DS05-11456-1E
15
MB81EDS256445
Current State
Write
Recovering
Precharging
CS
RAS CAS WE
Address
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
Illegal
L
H
L
L
BA, CA, AP
WRIT/WRITA
Start Write; Determine AP
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF
L
L
L
L
MODE
MRS
NOP
Illegal *1
Illegal
NOP
Illegal
Illegal *1
NOP *2
Illegal
(Continued)
16
DS05-11456-1E
MB81EDS256445
(Continued)
Current State
Bank
Activating
Refreshing/
Mode Register
Setting
CS
RAS CAS WE
Address
Command
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
X
X
READ/READA/
WRIT/WRITA
L
L
X
X
X
ACT/PRE/PALL/
REF/SELF/MRS
RA = Row Address
CA = Column Address
Function
NOP
Illegal *2
Illegal
NOP
Illegal
BA = Bank Address
AP = Auto Precharge
Note: Assuming CKE = H during the previous clock cycle and the current clock cycle. After illegal commands are
asserted, following command and stored data should not be guaranteed.
*1: Illegal to bank in the specified state. Command entry may be legal depending on the state of bank selected by BA.
*2: NOP to bank in precharging or in idle state. Bank in active state may be precharged depending on BA.
*3: Illegal if any bank is not idle.
*4: MRS command should be issued on condition that all DQ are in High-Z.
*5: Requires appropriate DM masking.
DS05-11456-1E
17
MB81EDS256445
■ BANK OPERATION COMMAND TABLE
Minimum clock latency or delay time for single bank operation
MRS
ACT
READ
READA
WRIT
WRITA
BST
PRE
PALL
REF
SELF
1st Command
2nd Command (same bank)
MRS
tMRD
tMRD
⎯
⎯
⎯
⎯
tMRD
tMRD
tMRD
tMRD
tMRD
ACT
⎯
⎯
tRCD
*4
tRCD
*5
tRCD
tRCD
⎯
tRAS
tRAS
⎯
⎯
READ
⎯
⎯
*6
*6
1
1
BL/2
+CL
BL/2
+CL
1
*3
*3
1
1
⎯
⎯
READA
*1, *2
BL/2
+ tRP
⎯
⎯
⎯
⎯
BL/2
+ tRP
BL/2
+ tRP
BL/2
+ tRP
*1
*1, *2
BL/2
+ tRP
BL/2
+ tRP
BL/2
+ tRP
⎯
*6
*3
⎯
*6
*3
WRIT
2
+ tWTR
2
+ tWTR
1
1
1
BL/2
+1
+ tWR
BL/2
+1
+ tWR
⎯
⎯
*1, *2
⎯
⎯
⎯
⎯
BL/2
+1
+ tDAL
BL/2
+1
+ tDAL
BL/2
+1
+ tDAL
*1, *2
BL/2
+1
+ tDAL
BL/2
+1
+ tDAL
*1
WRITA
BL/2
+1
+ tDAL
BL/2
+1
+ tDAL
READ BST
⎯
⎯
1
1
CL
CL
*3
*3
1
1
⎯
⎯
1
WRIT BST
⎯
⎯
1
+ tWTR
1
+ tWTR
1
1
PRE
*1, *2
RP
tRP
⎯
⎯
⎯
⎯
PALL
*2
tRP
tRP
⎯
⎯
⎯
REF
tREFC
tREFC
⎯
⎯
SELFX
tREFC
tREFC
⎯
⎯
t
*3
*3
1
+ tWR
1
+ tWR
⎯
⎯
tRP
1
1
*1
tRP
*1, *2
RP
⎯
tRP
1
1
tRP
tRP
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
t
*2
“ - ” : illegal
*1: Assume all banks are in IDLE state.
*2: Assume output is in High-Z state.
*3: Assume tRAS (Min.) is satisfied.
*4: ACT to READA interval must be longer than tRAS - BL/2.
*5: ACT to WRITA interval must be longer than tRAS - (1 + BL/2 + tWR).
*6: Assume appropriate DM masking.
18
DS05-11456-1E
MB81EDS256445
MRS
ACT
READ
READA
WRIT
WRITA
BST
PRE
PALL
REF
SELF
1st Command
Minimum clock latency or delay time for multi bank operation
2nd Command (other bank)
MRS
tMRD
tMRD
⎯
⎯
⎯
⎯
tMRD
tMRD
tMRD
tMRD
tMRD
ACT
⎯
tRRD
1
1
1
1
1
1
tRAS
⎯
⎯
READ
⎯
*1, *3
*5
*5
1
1
BL/2
+CL
BL/2
+CL
1
1
*4
1
⎯
⎯
READA
*1, *3
*5
*5
*1
*1
BL/2
BL/2
BL/2
+CL
BL/2
+CL
BL/2
+ tRP
*4
BL/2
+ tRP
1
BL/2
+ tRP
BL/2
+ tRP
BL/2
+ tRP
WRIT
⎯
*1, *3
*5
*5
2
+ tWTR
2
+ tWTR
1
1
1
1
BL/2
+1
+ tWR
⎯
⎯
*1
*1
BL/2
+1
+ tDAL
BL/2
+1
+ tDAL
*4
WRITA
1
BL/2
+1
+ tDAL
BL/2
+1
+ tDAL
BL/2
+1
+ tDAL
READ BST
⎯
*4
⎯
⎯
*1, *2
1
1
*1, *3
1
*4
*5
*5
BL/2
+1
+ tWTR
BL/2
+1
+ tWTR
BL/2
BL/2
1
1
CL
CL
*1
*1, *3
⎯
PRE
*1, *2
RP
*1, *3
PALL
*1
1
*4
1
+ tWTR
1
+ tWTR
1
1
1
1
1
1
1
tRP
tRP
⎯
⎯
⎯
REF
tREFC
tREFC
⎯
⎯
SELFX
tREFC
tREFC
⎯
⎯
t
1
1
1
WRIT BST
1
1
1
+ tWR
⎯
⎯
1
1
1
*1
tRP
*1, *2
RP
⎯
tRP
1
1
tRP
tRP
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
t
“ - ” : illegal
*1: Assume other bank is in IDLE state.
*2: Assume output is in High-Z state.
*3: Assume tRRD is satisfied.
*4: Assume tRAS is satisfied.
*5: Assume appropriate DM masking.
DS05-11456-1E
19
MB81EDS256445
■ COMMAND DESCRIPTION
1. DESELECT (DESL)
When CS is High at the CK rising edge, all input signals are neglected. Internal operation such as burst cycle is
held.
2. NO OPERATION (NOP)
NOP disables address and data input and internal operation such as burst cycle is held.
3. BANK ACTIVE (ACT)
ACT activates the bank selected by BA and latch the row address through A0 to A11.
4. READ (READ)
READ initiates burst read operation to an activated row address. Address inputs of A[7:0] determine starting
column address and A10 determines whether Auto Precharge is used or not. Initially DQS output Low level
then start toggling together with data output with respect to CL and BL. The read data output is edge-aligned
with first rising edge of DQS and successive read data output are edge-aligned to the successive edge of
DQS. The CK drives the rising edge of DQS and Even data, and the CK drives the falling edge of DQS and
Odd data.
20
DS05-11456-1E
MB81EDS256445
Data Output Timing
CK
CK
CAS Latency
Command
READ
NOP
tDQSCK
tAC (Min.)
tDQSCK
DQS
tLZ
DQ
tQH
tQH
Qeven
Qodd
tDQSQ
Qodd
Qeven
tDQSQ
tAC
tAC
tAC (Max.)
tDQSCK
tDQSCK
DQS
tLZ
DQ
tQH
tQH
Qeven
Qodd
tDQSQ
tDQSQ
tAC
tAC
Read Preamble and Postamble @CL = 3
CK
CK
CL = 3
Command
READ
NOP
DQS
tRPST
tRPRE
DQ
DS05-11456-1E
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
21
MB81EDS256445
5. READ with Auto Precharge (READA)
READA commands can be issued by READ command with AP (A10) = H. Auto precharge is a feature which
precharge the activated bank after the completion of burst read operation. The tRAS is defined from between
ACTIVE (ACT) command to the internal precharge which starts after BL/2 from READA command. READ with
Auto precharge operation should not be interrupted by subsequent READ, READA, WRITE, WRITEA commands.
Next ACTIVE (ACT) command can be issued after BL/2 + tRP after READA command.
22
DS05-11456-1E
MB81EDS256445
6. WRITE (WRIT)
WRIT initiates burst write operation to an active row address. Address inputs of A[7:0] determine starting column
address and AP(A10) determines whether Auto Precharge is used or not. DQS input must be provided in order
to latch the input data. DQS must be brought to Low to satisfy the specified time duration of the Write Preamble
Setup Time to CK (tWPRES). Input data window must be guaranteed with specified minimum setup and hold time
against edge of DQS input (tDS, tDH). The input data appearing on DQ is written into memory cell array subject
to the DM input logic level appearing coincident with the input data. If a given signal on DM is registered Low,
the corresponding data will be written into the cell array. And if a given signal on DM is registered High, the
corresponding data will be masked and write will not be executed to that byte. After data input with respect to
BL is completed, DQS must be kept low for the specified minimum value of Write Postamble Time (tWPST).
Data Input Timing
CK
CK
Command
tDQSS (Min.)
NOP
WRIT
tDQSS
tDQSH
tDQSL
DQS
tDSS
DQ
Qeven
tDSH
Qodd
Mask
tDSS
Qodd
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
DM
tDQSS (Max.)
tDQSS
tDQSH
tDQSL
DQS
tDSS
DQ
Qeven
Qodd
tDSS
tDSH
Mask
Qodd
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
DM
DS05-11456-1E
23
MB81EDS256445
Write Preamble and Postamble
CK
CK
Command WRITE
NOP
tWPRES
DQS
tWPRE
tWPST
Q0
DQ
Q1
Q2
Q3
Q4
Q5
Q6
Q7
7. WRITE with Auto Precharge (WRITA)
WRITA commands can be issued by WRIT command with AP (A10) = H. Auto precharge is a feature which
precharge the activated bank after the completion of burst write operation. The tRAS is defined from between
ACTIVE (ACT) command to the internal precharge which starts after 1+ BL/2 + tWR from WRITA command. WRIT
with Auto precharge operation should not be interrupted by subsequent READ, READA, WRIT, WRITA
commands. Next ACTIVE (ACT) command can be issued after 1+ BL/2 + tDAL after WRITA command.
8. BURST TERMINATE (BST)
BST terminates the burst read or write operation. When a burst read is terminated by BST command, the data
output will be in High-Z after CAS latency from the BST command. When a burst write is terminated by BST
command, the data input after 1 clock from BST command will be masked.
Terminate read by BST @CL=3
CK
CL = 3
Command
NOP
READ
NOP
BST
CL = 3
Q0
DQ (output)
Q1
Terminate write by BST
CK
1 clock
Command
NOP
WRIT
NOP
BST
Masked
by BST
DQ (input)
24
D0
D1
D2
D3
DS05-11456-1E
MB81EDS256445
9. PRECHARGE SINGLE BANK (PRE)
PRECHARGE SINGLE BANK (PRE) command starts precharge operation for a bank selected by BA. A selected
bank will be in IDLE state after specified time duration of tRP from PRE command. A10 determines whether one
or all banks are precharged. If AP(A10) = L, a bank to be selected by BA is precharged.
10. PRECHARGE ALL BANK (PALL)
PRECHARGE ALL BANKS (PALL) command starts precharge operation for all banks. All banks will be in IDLE
state after specified time duration of tRP from PALL command. A10 determines whether one or all banks are
precharged. If AP(A10) = H, all banks are precharged and BA input is a “don't care”.
11. AUTO REFRESH (REF)
AUTO REFRESH (REF) command starts internal refresh operation which uses the internal refresh address
counter. All banks must be precharged prior to the Auto-refresh command. Data retention capability depends
on the Junction Temperature (Tj). Total 4,096 AUTO REFRESH (REF) commands must be asserted within the
following refresh period of tREF.
Tj Max ( °C)
tREF (ms)
+ 105
16
+ 125
4
12. SELF-REFRESH ENTRY (SELF)
SELF REFRESH ENTRY (SELF) commands can be issued by AUTO REFRESH (REF) command in conjunction
with CKE = Low after last read data has been appeared on DQ. During Self Refresh mode, stored data can be
retained without external clocking and all inputs except for CKE will be “don't care”. Self refresh mode can be
used when Tj is less than + 85°C. Auto Refresh must be issued to retain data when Tj is greater than + 85 °C.
13. SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tIS after CKE brought High, and then the NO OPERATION command
(NOP) or the DESELECT command (DESL) should be asserted within one tREFC period. CKE should be held
High within one tREFC period after tIS. Refer to the “(15) Self Refresh Entry and Exit” in “■TIMING DIAGRAMS”
for the detail. It is recommended to assert an Auto-refresh command just after the tREFC period to avoid the
violation of refresh period.
14. MODE REGISTER SET (MRS)
MODE REGISTER SET (MRS) commands to program the mode registers. Once a mode register is programmed,
the contents of the register will be held until re-programmed by another MRS command. MRS command should
only be issued on conditions that all DQs are in High-Z and all banks are in IDLE state. The contents of the mode
registers is undefined after the power-up and Deep Power Down Exit. Therefore MRS must be issued to set
each content of mode registers after initialization. Refer to the “Power Up Initialization” in “ ■FUNCTIONAL
DESCRIPTION”.
15. POWER DOWN ENTRY (PD)
POWER DOWN ENTRY (PD) commands to drive the device in Power Down mode and maintains low power
state as long as CKE is kept Low. During Power Down state, all inputs signals are “don't care” except for CKE.
Power Down mode must be entered on condition that all DQs are in High-Z.
16. POWER DOWN EXIT (PDX)
POWER DOWN EXIT (PDX) commands to resume the device from Power Down mode. Any commands can be
detected 1 clock after PDX commands.
DS05-11456-1E
25
MB81EDS256445
17. DEEP POWER DOWN ENTRY (DPD)
DEEP POWER DOWN ENTRY (DPD) commands to drive the device in Deep Power Down mode which is the
lowest power consumption but all stored data and the contents of mode registers will be lost. During Deep Power
Down state, all inputs signals except for CKE are “don't care” and all DQs and DQS will be in High-Z. Deep
Power Down mode must be entered on conditions that all DQs are in High-Z and all banks are in IDLE state.
18. DEEP POWER DOWN EXIT (DPDX)
DEEP POWER DOWN EXIT (DPDX) commands to resume the device from Deep Power Down mode. Power
up initialization procedure must be performed after DPDX commands. Refer to the “Power Up Initialization” in
“■ FUNCTIONAL DESCRIPTION”.
26
DS05-11456-1E
MB81EDS256445
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Supply Voltage Relative to VSS
VDD,VDDQ
-0.5 to +2.3
V
Input / Output Voltage Relative to VSS
VIN, VOUT
-0.5 to +2.3
V
Short Circuit Output Current
IOUT
±50
mA
Power Dissipation
PD
1.0
W
TSTG
-55 to +125
°C
Storage Temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min.
Typ.
Max.
Unit
VDD, VDDQ
1.7
1.8
1.95
V
VSS, VSSQ
0
0
0
V
DC Input High Voltage*2
VIH (DC)
VDDQ × 0.7
⎯
VDDQ + 0.3
V
AC Input High Voltage*2
VIH (AC)
VDDQ × 0.8
⎯
VDDQ + 0.3
V
*3
VIL (DC)
-0.3
⎯
VDDQ × 0.3
V
AC Input Low Voltage*3
VIL (AC)
-0.3
⎯
VDDQ × 0.2
V
Junction Temperature
Tj
-10
⎯
+125
°C
Supply Voltage*1
DC Input Low Voltage
*1: VDDQ must be less than or equal to VDD.
*2: Maximum DC voltage on input or I/O pins is VDDQ + 0.3 V. During voltage transitions, inputs may positive
overshoot to VDDQ + 1.0V for periods of up to 3 ns.
*3: Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, inputs may negative overshoot
to VSSQ - 1.0V for periods of up to 3 ns.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
■ CAPACITANCE
Parameter
(Ta = + 25 °C, f = 1 MHz)
Max.
Unit
Symbol
Min.
Typ.
Input Capacitance, Except for DM
CIN1
3
⎯
5
pF
Input Capacitance for DM
CIN2
5
⎯
7
pF
I/O Capacitance
CI/O
5
⎯
7
pF
DS05-11456-1E
27
MB81EDS256445
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
(Under recommended operating conditions unless otherwise noted)
Value
Condition
Unit
Min.
Max.
Symbol
VDDQ − 0.2
⎯
V
IOL = 0.1 mA
⎯
0.2
V
Output High Voltage
VOH(DC) IOH = -0.1 mA
Output Low Voltage
VOL(DC)
Input Leakage
Current
ILI
0 V ≤ VIN ≤ VDDQ,
All other pins not under test = 0 V
−5
5
μA
Output Leakage
Current
ILO
0 V ≤ VIN ≤ VDDQ, Data out disabled
−5
5
μA
Operating One Bank
Active-Precharge
Current
IDD0
tRC = tRC min, tCK = tCK min, CKE = VIH, CS = VIH
addresses inputs are SWITCHING;
data bus inputs are STABLE
⎯
65
mA
⎯
3
IDD2P
All banks idle, CKE = VIL,
CS = VIH, tCK = tCK min,
address and control inputs are
SWITCHING;
data bus inputs are STABLE
Precharge Standby
Current
Operating Burst Read
Current
Operating Burst Write
Current
Auto Refresh Current
Tj ≤ + 105 °C
mA
Tj ≤ + 125 °C
IDD2N
All banks idle, CKE = VIH,
CS = VIH, tCK = tCK min,
address and control inputs are SWITCHING;
data bus inputs are STABLE
IDD4R
One bank active, BL = 4,
Tj ≤ + 105 °C
tCK = tCK min,
Output pin open, Gapless data,
address inputs are SWITCHING;
50% data change each burst transfer Tj ≤ + 125 °C
IDD4W
IDD5
Tj ≤ + 105 °C
One bank active, BL = 4,
tCK = tCK min, Gapless data,
address inputs are SWITCHING;
50% data change each burst transfer Tj ≤ + 125 °C
tRC = tRFC min, tCK = tCK min, CKE = VIH,
address and control inputs are SWITCHING;
data bus inputs are STABLE
⎯
5
⎯
15
⎯
300
mA
mA
⎯
280
⎯
330
mA
⎯
305
⎯
120
mA
(Continued)
28
DS05-11456-1E
MB81EDS256445
(Continued)
Parameter
Symbol
Self Refresh Current
IDD6
Deep Power Down
Current
IDD8
Condition
Value
Unit
Min.
Max.
CKE = VIL, CS = VIL,
address and control inputs are STABLE;
data bus inputs are STABLE
⎯
4
mA
address and control inputs are STABLE;
data bus inputs are STABLE
⎯
20
μA
Notes: • All voltages are referenced to VSS.
• After power on, initialization following power-up timing is required. DC characteristics are guaranteed
after the initialization.
• IDD depends on the output termination or load condition, clock cycle rate, signal clocking rate.
The specified values are obtained with the output open condition.
DS05-11456-1E
29
MB81EDS256445
2. AC Characteristics
(Under recommended operating conditions unless otherwise noted)*1, *2
Value
Symbol
Unit
Min.
Max.
Parameter
DQ Output Access Time from CK/CK (tCK = tCK min)*3, *4, *7
tAC
2
6
ns
tDQSCK
2
6
ns
tCH
2
⎯
ns
tCL
2
⎯
ns
tDC
0.45
0.55
tCK
⎯
ns
⎯
ns
0.4
⎯
ns
0.5
⎯
ns
tDIPW
0.35
⎯
tCK
tIS
0.9
⎯
ns
Address and Control Input Hold Time *
tIH
0.9
⎯
ns
Address and Control Input Pulse Width
tIPW
0.6
⎯
tCK
DQ Low-Z Time from CK/CK *3, *5
tLZ
0
⎯
ns
DQ High-Z Time from CK/CK *3, *5, *6
tHZ
⎯
6
ns
tDQSQ
⎯
0.4
ns
tQH
tDC − 0.5
⎯
ns
WRIT Command to 1st DQS Latching Transition
tDQSS
0.75
1.25
tCK
DQS Input High Level Width
tDQSH
0.35
⎯
tCK
DQS Input Low Level Width
tDQSL
0.35
⎯
tCK
DQS Falling Edge to CK Setup Time
tDSS
0.2
⎯
tCK
DQS Falling Edge Hold Time from CK
tDSH
0.2
⎯
tCK
MRS Command Period
tMRD
2
⎯
tCK
Write Preamble Setup Time
tWPRES
0
⎯
ns
Write Preamble Time
tWPRE
0.25
⎯
tCK
Write Postamble Time
tWPST
0.4
0.6
tCK
0.5
1.1
0.9
1.1
0.4
0.6
DQS Output Access Time from CK/CK *3, *4
Clock High Level Width *3
3
Clock Low Level Width *
4
Delay between CK and CK *
CL = 2
15
CL = 3
Clock Cycle Time
CL = 4
Tj ≤ + 105 °C
Tj ≤ + 125 °C
Tj ≤ + 105 °C
DQ and DM Input Setup Time
Tj ≤ + 125 °C
Tj ≤ + 105 °C
DQ and DM Input Hold Time
Tj ≤ + 125 °C
DQ and DM Input Pulse Width
Address and Control Input Setup Time *3
3
DQS to DQ Skew *
4
3,
4
DQ Output Hold Time from DQS * *
Read Preamble Time
Read Postamble Time
tCK
CL = 2
CL = 3, 4
7.4
4.6
5
tDS
tDH
tRPRE
tRPST
0.4
0.5
tCK
tCK
(Continued)
30
DS05-11456-1E
MB81EDS256445
(Continued)
Parameter
(Under recommended operating conditions unless otherwise noted)*1, *2
Value
Symbol
Unit
Min.
Max.
ACT to PRE, PALL Command Period *7
tRAS
37
8000
ns
ACT to ACT Command Period (Same Bank) *7
tRC
59.2
⎯
ns
REF to ACT, REF Command Period
tREFC
100
⎯
ns
ACT to READ or WRIT Command Period
tRCD
20
⎯
ns
Precharge Period *7
tRP
18
⎯
ns
ACT to ACT Command Period (Other Bank)
tRRD
9.2
⎯
ns
Write Recovery Time
tWR
12
⎯
ns
⎯
ns
⎯
ns
CL = 2
Data Input to ACT, REF Command Period
CL = 3
1 CLK + tRP
tDAL
CL = 4
Internal Write to READ Command Period
Average Refresh Period *8
Average Periodic Refresh Interval
Tj ≤ + 105°C
Tj ≤ + 125°C
Tj ≤ + 105°C
Tj ≤ + 125°C
Transition Time *9
2 CLK + tRP
3 CLK + tRP
tWTR
9.2
tREFI
⎯
tREF
⎯
tT
⎯
3.9
0.97
16
4
1
μs
ms
ns
* 1: AC characteristics are measured after the Power up initialization procedure.
* 2: VDD × 0.5 is the reference level for 1.8 V I/O for measuring timing of input/output signals.
* 3: If input signal transition time (tT) is longer than 1 ns; [(tT/2) − 0.5] ns should be added to tAC (Max), tDQSCK (Max)
and tHZ (max) spec values, [(tT/2) − 0.5] ns should be subtracted from tLZ (Min) and tQH (Min) spec values, and
(tT - 1.0) ns should be added to tCH (Min), tCL (Min), tIS (Min), tIH (Min), tDS (Min) and tDH (Min) spec values.
* 4: The data valid window is defined as tQH - tDQSQ. The data valid window depends on tDC which is defined between
rising edge of CK and rising edge of CK. The data valid window is guaranteed when tDC is satisfied.
* 5: tAC, tDQSCK, tLZ and tHZ, are measured under output load circuit shown in “ 3. Measurement Condition of AC
Characteristics” in “ ■ ELECRTRICAL CHARACTERISTICS” and Driver Strength (DS) = Normal, Pre Driver
Strength (PDS) = Fast are assumed.
* 6: Specified where output buffer is no longer driven.
* 7: The sum of actual clock count of tRAS and tRP must be equal or greater than specified minimum tRC.
* 8: This value is for reference only.
* 9: Transition times are measured between VIH (AC) min and VIL (AC) max.
DS05-11456-1E
31
MB81EDS256445
3. Measurement Condition of AC Characteristics
VDD × 0.5 V
50 Ω
VDD
0.1 μF
VSS
32
DEVICE
UNDER
TEST
OUT
10 pF
DS05-11456-1E
MB81EDS256445
■ TIMING DIAGRAMS
(1) Read* (Assuming CL = 4, BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
BA
BA
BA
RA
RA
CA
RA
DM
DQS
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
tRCD
tRAS
tRP
tRC
ACT
READ
PRE
ACT
Don’t care
* : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
DS05-11456-1E
33
MB81EDS256445
(2) Read to Read*1 (Assuming CL = 4, BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
0
1
AP
RA
RA
RA
RA
Address
0
1
1
0
N
N
M
M
DM
DQS
DQ
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CL = 4
tRCD
Q0 Q1
CL = 4
CL = 4
tRCD
CL = 4
ACT
Bank 0
ACT
Bank 1
READ *2
Bank 0,
CA = N
READ *2
Bank 1,
CA = N
READ *2
Bank 1,
CA = M
READ
Bank 0,
CA = M
Don’t care
*1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2: Previous burst read can be interrupted by subsequent burst read.
34
DS05-11456-1E
MB81EDS256445
(3) Read to Precharge *1(Assuming CL = 4, BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
BA
BA
BA
BA
BA
RA
RA
CA
RA
CA
DM
DQS
DQ
Q0 Q1 Q2 Q3
CL = 4
tRCD
CL = 4
tRCD
CL =
tRAS
Q0 Q1
4*2
tRP
tRAS
tRC
ACT
READ
PRE*2
ACT
READ
PRE
Don’t care
*1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2: Burst read operation can be terminated by PRE command. All DQ pins become High-Z after CL from PRE
command.
DS05-11456-1E
35
MB81EDS256445
(4) Read with Auto-Precharge *1 (Assuming CL = 4, BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
BA
BA
RA
RA
RA
CA
DM
DQS
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
tRCD
BL/2
tRP
tRAS
tRC
ACT
READA
Precharge
start*2
ACT*3
Don’t care
*1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2: Internal precharge operation starts after BL/2 from READA command. tRAS must be satisfied.
*3: Next ACT command can be issued after BL/2 + tRP from READA command. tRC must be satisfied.
36
DS05-11456-1E
MB81EDS256445
(5) Write *1 (Assuming BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
BA
BA
BA
RA
RA
RA
CA
DM
DQS
DQ
D0 D1 D2 D3 D4 D5 D6 D7
tRCD
tWR
tRP
tRAS
tRC
ACT
WRIT
PRE*2
ACT
Don’t care
*1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2: Burst write operation should not be terminated by PRE command. PRE can be issued after 1 + BL/2 + tWR from
WRIT command.
DS05-11456-1E
37
MB81EDS256445
(6) Write to Write *1 (Assuming BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
0
1
AP
RA
RA
RA
RA
Address
0
1
1
0
N
N
M
M
DM
DQS
DQ
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
tRCD
tRCD
ACT
Bank 0
ACT
Bank 1
WRIT
Bank 0,
CA = N
WRIT*2
Bank 1,
CA = N
WRIT*2
Bank 1,
CA = M
WRIT
Bank 0,
CA = M
Don’t care
*1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2 : Previous burst write can be interrupted by subsequent burst write.
38
DS05-11456-1E
MB81EDS256445
(7) Write with Auto-Precharge *1 (Assuming BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
BA
BA
RA
RA
CA
RA
DM
DQS
DQ
D0 D1 D2 D3 D4 D5 D6 D7
1 + BL/2
tRCD
tDAL
tRAS
tRC
ACT
WRITA
Precharge
start
ACT*2
Don’t care
*1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2 : Next ACT command can be issued after 1 + BL/2 + tDAL (Min) from WRITA command. tRC must be satisfied.
DS05-11456-1E
39
MB81EDS256445
(8) Read to Write *1 (Assuming CL = 4, BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
BA
BA
CA
CA
DM
DQS
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CL + BL/2*2
tRCD
ACT
D0 D1 D2 D3 D4 D5 D6 D7
READ
WRIT
Don’t care
*1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2 : WRIT command can be issued after CL + BL/2 after READ command.
40
DS05-11456-1E
MB81EDS256445
(9) Read to Write with BST Command *1 (Assuming CL = 4, BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
BA
BA
CA
CA
DM
DQS
DQ
Q0 Q1
CL*2
tRCD
ACT
D0 D1 D2 D3 D4 D5 D6 D7
READ
BST
WRIT
Don’t care
*1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2 : WRIT command can be issued after CL from burst read termination by BST command.
DS05-11456-1E
41
MB81EDS256445
(10) Write to Read *1 (Assuming CL = 4, BL = 4)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
BA
BA
CA
CA
DM
DQS
DQ
D0 D1 D2 D3
tRCD
ACT
1 + BL/2*2
WRIT
Q0 Q1 Q2 Q3
tWTR
CL
READ
Don’t care
*1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2 : READ command can be issued after 1 + BL/2 + tWTR from WRIT command.
42
DS05-11456-1E
MB81EDS256445
(11) Write to Read with BST Command *1 (Assuming CL = 4, BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
BA
BA
CA
CA
DM
DQS
DQ
D0 D1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Masked
by BST*2
ACT
CL
1 + tWTR
tRCD
WRIT
BST
READ*3
Don’t care
*1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2 : The data input after 1 clock from BST command will be masked.
*3 : READ command can be issued after 1 + tWTR from burst write termination by BST command.
DS05-11456-1E
43
MB81EDS256445
(12) Write to Read with DM Mask *1 (Assuming CL=4, BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
BA
BA
CA
CA
DM
DQS
DQ
D0 D1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Masked*2
tWTR
tRCD
ACT
WRIT
CL
READ
Don’t care
*1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2 : DM must be High during tWTR from last pair of input data.
44
DS05-11456-1E
MB81EDS256445
(13) DM Control Write *1 (Assuming BL = 8)
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
BA
BA
BA
RA
CA
RA
DM
DQS
DQ
D0 D1
tRCD
D3 D4 D5 D6 D7
tWR
Masked *2
tRP
tRAS
tRC
ACT
WRIT
PRE
ACT
Don’t care
*1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2 : When DM is registered High, the corresponding data will be masked.
DS05-11456-1E
45
MB81EDS256445
(14) Auto Refresh *1
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
DM
High-Z
DQS
High-Z
DQ
tRP
PALL*2
tREFC*3
REF
tREFC*3
REF
ACT*4
Don’t care
*1 : RA = Row Address, BA = Bank Address, AP = Auto Precharge
*2 : All banks must be precharged prior to the AUTO REFRESH command (REF).
*3 : Either NOP or DESL command should be asserted during tREFC period.
*4 : ACT or MRS or REF command should be asserted after tREFC from REF command.
46
DS05-11456-1E
MB81EDS256445
(15) Self Refresh Entry and Exit *1
CK
CK
tIS
CKE
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
DM
High-Z
DQS
High-Z
DQ
tRP
PALL*2
tREFC*4,*5
SELF
SELFX *3
ACT
Don’t care
*1 : RA = Row Address, BA = Bank Address, AP = Auto Precharge
*2 : All banks must be precharged prior to SELF REFRESH ENTRY (SELF) command.
*3 : SELF REFRESH EXIT (SELFX) command can be latched at the CK rising edge.
*4 : Either NOP or DESL command can be used during tREFC period.
*5 : CKE should be held High during tREFC period after SELFX command.
DS05-11456-1E
47
MB81EDS256445
(16) Mode Register Set*1
CK
CK
CKE
H
CS
RAS
CAS
WE
BA
Code
Code
Code
BA
AP
Code
Code
Code
RA
Address
Code
Code
Code
RA
DM
High-Z
DQS
High-Z
DQ
tRP
PALL*2
tREFC
REF
tREFC
REF
tMRD
MRS*2
tMRD
MRS*2
tMRD
MRS*2
ACT
Don’t care
*1 : RA = Row Address, BA = Bank Address, AP = Auto Precharge
*2 : MODE REGISTER SET (MRS) command must be asserted after all banks have been precharged and all
DQ are in High-Z.
48
DS05-11456-1E
MB81EDS256445
(17) Power Down Entry and Exit *1
CK
CK
tIS
CKE
CS
RAS
CAS
WE
BA
BA
AP
RA
Address
RA
DM
High-Z
DQS
High-Z
DQ
PALL
PD*2
PDX ACT*3
Don’t care
*1 : RA = Row Address, BA = Bank Address, AP = Auto Precharge
*2 : PD command can be issued after all DQ are in High-Z.
*3 : ACT command can be issued after 1 clock from POWER DOWN EXIT (PDX) command.
DS05-11456-1E
49
MB81EDS256445
(18) Deep Power Down Entry*
CK
CK
CKE
CS
RAS
CAS
WE
BA
AP
Address
DM
High-Z
DQS
High-Z
DQ
tRP
PALL
DPD
Don’t care
* : DEEP POWER DOWN ENTRY (DPD) Command can be issued after all banks have been precharged and all
DQ are in High-Z.
50
DS05-11456-1E
MB81EDS256445
(19) Deep Power Down Exit *1
CK
CK
tIS
CKE
CS
RAS
CAS
WE
BA
Code
Code
Code
BA
AP
Code
Code
Code
RA
Code
Code
Code
RA
Address
DM
High-Z
DQS
High-Z
DQ
300 µs
DPDX*2
tRP
PALL
tREFC
REF
tREFC
REF
tMRD
MRS
tMRD
EMRS
tMRD
EMRS
ACT
Don’t care
*1: RA = Row Address, BA = Bank Address, AP = Auto Precharge
*2: Power up initialization procedure must be performed after DPDX command.
DS05-11456-1E
51
MB81EDS256445
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department