FUJITSU MB86391

MPEG2 1chip Audio/Video Encoder
MB86391 Product Specification
Revision 1.1
12, November 2001
Copyright © FUJITSU LIMITED
ALL RIGHTS RESERVED
MB86391
Product Specification
Rev. 1.1
12, November 2001
FUJITSU LIMITED
Proprietary and Confidential
u
Information contained in this specification is subject to change without notice for improvement.
u
No part of this specification may be reproduced or transmitted in any form or by any means for any purpose
without the express written permission of Fujitsu Ltd.
u
The furnishing of this specification does not give users any license to Fujitsu's industrial property rights.
u
Fujitsu is not liable for infringement of third party patent rights, industrial property rights, or other rights that
might result from the use of contents provided in this specification.
u
Use of product in any manner that complies with the MPEG-2 standard is expressly prohibited without a license
under applicable patents in the MPEG-2 patent portfolio, which license is available from
MPEG LA, L.L.C., 250 steele street, suite 300, Denver, Colorado, USA 80206
MB86391
Product Specification
Rev. 1.1
12, November 2001
FUJITSU LIMITED
Proprietary and Confidential
Contents
1
Overview ......................................................................................................................................... 1
1.1 Product Overview ...................................................................................................................... 1
1.2 System Configuration................................................................................................................. 2
1.3 Specification Overview ............................................................................................................... 3
1.3.1
Major Items................................................................................................................... 3
1.3.2
Function List ................................................................................................................. 3
1.3.3
Package....................................................................................................................... 4
1.4 Block Diagram .......................................................................................................................... 5
2
Pin Description................................................................................................................................. 6
2.1 I/O Signals ............................................................................................................................... 6
2.2 Pin Arrangement ....................................................................................................................... 7
2.2.1
Pin Arrangement Diagram............................................................................................... 7
2.2.2
Pin Numbers ................................................................................................................. 8
2.3 Pin Functions............................................................................................................................ 9
3
2.3.1
Overall Control .............................................................................................................. 9
2.3.2
Host/SDRAM interface.................................................................................................. 10
2.3.3
Serial Interface...........................................................................................................111
2.3.4
SDRAM Interface for Video Encoding............................................................................122
2.3.5
Video Input Interface...................................................................................................133
2.3.6
Audio Input Interface...................................................................................................144
2.3.7
Bit Stream Output Port.................................................................................................155
2.3.8
Test Signals...............................................................................................................166
Functional Description....................................................................................................................177
3.1 Host/SDRAM Interface............................................................................................................177
3.1.1
Access by External Master...........................................................................................188
3.1.1.1 MB86391 Internal Resource Accessing..............................................................188
3.1.1.2 SDRAM Accessing........................................................................................... 20
3.1.1.3 External Resource Accessing...........................................................................244
3.1.2
Internal Controller Master Accessing .............................................................................266
3.1.2.1 External Resource Accessing...........................................................................266
3.1.2.2 External Boot ROM Read.................................................................................288
3.1.3
Interruption ................................................................................................................299
3.1.3.1 Internal Controller Interrupt Input (IRQ9:8)..........................................................299
3.1.3.2 Host Interrupt Output (XEXTIRPT) ....................................................................299
3.1.4
Address Map............................................................................................................... 30
3.2 Serial Interface.......................................................................................................................311
MB86391
Product Specification
Rev. 1.1
12, November 2001
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3.2.1
Serial Interface Receive Operations ..............................................................................311
3.2.2
Serial Interface Send Operations ..................................................................................322
3.3 SDRAM Interface for Video Encoding........................................................................................333
3.4 Video Input Interface...............................................................................................................344
3.4.1
Input Formats.............................................................................................................355
3.5 Audio Input Interface...............................................................................................................366
3.5.1
Master/Slave Mode...................................................................................................... 37
3.5.2
Input Formats.............................................................................................................377
3.6 Bit Stream Output Port ............................................................................................................388
3.7 Error Notification Function .......................................................................................................411
3.8 Boot Operations.....................................................................................................................422
4
3.8.1
Downloading from the External ROM.............................................................................433
3.8.2
Serial Download .......................................................................................................... 43
3.8.3
Direct SDRAM Downloading.........................................................................................433
Electrical Characteristics (Provisional Target Specifications)................................................................444
4.1 Maximum Ratings...................................................................................................................444
4.2 Recommended Operating Conditions ......................................................................................... 45
4.2.1
Recommended Operating Conditions ............................................................................. 45
4.2.2
Precautions When Connecting the Power ....................................................................... 45
4.3 DC Characteristics .................................................................................................................. 46
4.4 AC Characteristics................................................................................................................... 47
4.4.1
Overall Control ............................................................................................................ 47
4.4.1.1 Clock Input...................................................................................................... 47
4.4.1.2 Reset Input ..................................................................................................... 48
4.4.2
Host/SDRAM Interface................................................................................................. 49
4.4.2.1 Host Interface.................................................................................................. 49
4.4.2.2 SDRAM Interface Signals ................................................................................. 52
4.4.3
Serial Interface............................................................................................................ 54
4.4.4
SDRAM Interface for Video Encoding............................................................................. 56
4.4.5
Video Input Interface.................................................................................................... 58
4.4.6
Audio Input Interface.................................................................................................... 59
4.4.7
Bit Stream Output Port.................................................................................................. 63
MB86391
Product Specification
Rev. 1.1
12, November 2001
FUJITSU LIMITED
Proprietary and Confidential
1 Overview
1.1
Product Overview
The MB86391 (MPEG2 1chip Audio/Video Encoder) is an LSI that accomplishes all of video encoding, audio
encoding, and video and audio encode stream data multiplexing with a single chip rather than several LSIs as
in the past. This LSI enables you to minimize the size, cost and power consumption of MPEG2 application
systems, such as digital video recorders.
An easy control command interface is achieved by firmware dedicated to the internal controller.
MB86391
Product Specification
Rev. 1.1
12, November 2001
1
FUJITSU LIMITED
Proprietary and Confidential
1.2
System Configuration
Fig. 1.2 shows an example system configuration using the MB86391.
Serial interface
XMBREQ, XBREQ
System
Controller
XBGRNT
Bus
Switch
MB86391
16Mbit
SDRAM
(×16bit)
D31:0, ADRS27 :26, 17:2, control
XBUSEN, BUSDIR, XBGRNT
External
boot
ROM
MPEG2
Decoder
or
64Mbit
SDRAM
(×32bit)
SDRAM control
Bit stream output port
Video encoding SDRAM
16Mbit
SDRAM
( ×16bit)
D/A
64Mbit
SDRAM
(×32bit)
Audio I/F
Video I/F
Audio input
Video input
or
Video
output
Audio
output
Record/ com
mu nication
I/O
Controller/TBC SDRAM
Fig. 1.2 : System configuration (Example))
MB86391
Product Specification
Rev. 1.1
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1.3
Specification Overview
1.3.1 Major Items
Table 1.3.1 : Major items
Model
Function
Operating
frequency
Technology
Supply voltage
Power
consumption
Operating
temperature
Package
MB86391
MPEG2 1chip Audio/Video encoder
54MHz (27MHz for some)
[27MHz input clock frequency, 54MHz clock generated by internal PLL]
0.18µm, Al 4 layers
I/O 3.0 to 3.6V, Internal 1.65 to 1.95V
T.B.D
Ta = -20 to 85°C
208pin HQFP(FPT−208P−M04)
1.3.2 Function List
Table 1.3.2 : Function list
Encoding
Video encoder
Screen size
Video input
interface
Bit rate
Encoding method
Sampling
frequency
Audio encoder Channel count
Audio input
interface
Bit rate
Compliant to ISO/IEC13818− 2 (MPEG2 video)MP@ML and
ISO/IEC11172− 2 (MPEG1 video)
When interlacing at 29.97Hz
Compatible with size 32m×32n less than 720×480 (m, n : any integers)
When interlacing at 25Hz :
Compatible with size 32m×32n less than 720×576 (m, n : any integers)
D1 8bit parallel, YC multiplex 8bit parallel
Max. 15Mbps
ISO/IEC11172− 3 (MPEG1 audio) layer 1/2− compliant
32kHz, 44.1kHz, 48kHz
2 (mono, stereo, dual, joint stereo)
LR multiplex serial
Max. 448kbps
ISO/IEC11172− 1 (MPEG1 system)
Encoding method ISO/IEC13818− 1 (MPEG2 system PS/TS)
Multiplexer
[Can also output to mono media in ES and PES formats.]
Stream output
8bit parallel
Bit rate
Max. 20Mbps (CBR/VBR)
Overall controller
Internal 32bit RISC processor
External
SDRAM I/F for
Connects two 16Mbit (1M×16bits) or one 64Mbit (2M×32bits)
memory
video encoding
interface
Host/SDRAM I/F Connects two 16Mbit (1M×16bits) or one 64Mbit (2M×32bits)
Serial interface
One internal port for overall controller BOOT and command I/F
Absorbs timing errors due to disarrayed input video images by
Time base corrector
temporarily buffering before reading video input data on an SDRAM
connected to the host/SDRAM I/F.
MB86391
Product Specification
Rev. 1.1
12, November 2001
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1.3.3 Package
MB86391
Product Specification
Rev. 1.1
12, November 2001
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FUJITSU LIMITED
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1.4
Block Diagram
Fig. 1.4 shows a block outline diagram of this LSI and Table 1.4 lists the functional overviews of major blocks.
Serial interface
Host/SDRAM
interface
Host/SDRAM
interface
controller
Serial interface
controller
Boot
ROM
Controller
(32bit RISC
processor)
Video encoder
Video input interface
TBC controller
Bit stream output
port
Multiplexer
Video encoding
SDRAM
interface
Audio encoder
Audio input interface
SRAM
(8k× 8)
27MHz
Clock input
(27MHz)
PLL
54MHz
MB86391
Fig. 1.4 : MB86391 block diagram
Table 1.4 : Overview of major block functions
Block name
Functional overview
Video encoder
Encodes video data input from the TBC controller to create video streams.
Audio encoder
Multiplexer
Encodes audio data input from outside to create audio streams.
Multiplexes video and audio streams generated by video and audio
encoders to generate 8bit parallel stream data for output to outside.
Controller
TBC controller
Controls the entire MB86391 using dedicated firmware.
Stores video data input from outside in an external SDRAM and then input it
to the video encoder. The TBC (Time Base Corrector) function is
accomplished by buffering video data in the SDRAM.
Arbitrates SDRAM and MB86391 internal register access requests from
MB86391 internal blocks and external master devices. Also used as the
command interface with the host.
Downloads dedicated firmware to the external SDRAM via this interface at
the time of serial booting. Also used as a command interface with the host.
Host/SDRAM interface controller
Serial interface
controller
Video PES converter
DMA controller
Converts the format of video streams the video encoder has generated and
outputs to the multiplexer.
Controls DMA transfer among MB86391 blocks and external SDRAMs.
Boot ROM
Stores the boot program for the internal controller.
MB86391
Product Specification
Rev. 1.1
12, November 2001
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2 Pin Description
2.1
I/O Signals
Fig. 2.1 shows the I/O signals of this LSI.
12
CLKSEL
Overall control signals
(4 in total)
SDADRS11:0
32
MCLKI
SDDATA31:0
XRESET
SDDQM
PLLTHR
XSDWE
XSDCAS
BCLK
2
XSDRAS
16
XSDCS
32
SDCKE
2
SDCLK
ADRS27:26
Video encoding
SDRAM interfaces
(51 in total)
ADRS17:2
D31:0
IRQ9:8
XAS
VCLK
XRDWR
XVSYNC
XCS0
XHSYNC
2
XCS5:4
FIELD
XBMREQ
Host/SDRAM
interfaces
(71 in total)
XBREQ
Video input interfaces
(13 in total)
XVALID
MB86391
8
DVIDEO7:0
XBGRNT
ASCLK
XBUSEN
ALRCK
BUSDIR
ACLK
XREADY
Audio input interfaces
(4 in total)
ADATA
XEXTIRPT
XERROR
STCLK
XSPWE
STREQ
XSPCAS
STEN
8
XSPRAS
SPCKE
STDATA7:0
TSPSSYNC
SPSDCLK
47
SCLK
Serial interfaces
(3 in total)
Bit stream output ports
(12 in total)
Power/GND
(47 in total)
Test signals
(3 in total)
3
SDATAIN
SDATAOUT
Total external pin count :208
Fig. 2.1 : I/O signal diagram
MB86391
Product Specification
Rev. 1.1
12, November 2001
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FUJITSU LIMITED
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2.2
Pin Arrangement
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
SDDATA26
SDDATA25
SDDATA24
SDDATA0
SDDATA1
SDDATA2
VDDI
SDDATA3
SDDATA4
SDDATA5
SDDATA6
SDDATA7
SDDATA15
SDDATA14
VDDE
VSS
SDDATA13
SDDATA12
SDDATA11
SDDATA10
SDDATA9
SDDATA8
VSS
VDDE
VCLK
XHSYNC
XVSYNC
FIELD
XVALID
VDDI
DVIDEO7
DVIDEO6
DVIDEO5
DVIDEO4
DVIDEO3
DVIDEO2
DVIDEO1
DVIDEO0
VDDE
VSS
ADRS14
ADRS13
ADRS12
ADRS2
ADRS3
ADRS4
VSS
VDDE
VDDI
ADRS11
ADRS10
ADRS9
2.2.1 Pin Arrangement Diagram
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
MB86391
HQFP208(FPT-208P-M04)
INDEX
VDDI
TSPSSYNC
STEN
STDATA7
STDATA6
STDATA5
STDATA4
AVDD
AVSS
STDATA3
STDATA2
STDATA1
STDATA0
VSS
VDDE
STCLK
SDATAOUT
SDATAIN
SCLK
VDDI
XREADY
XRDWR
XAS
AVSS
AVDD
MCLKI
PLLTHR
CLKSEL
XBREQ
XBMREQ
IRQ8
IRQ9
XRESET
VDDE
VSS
XBGRNT
BUSDIR
XBUSEN
XEXTIRPT
XERROR
XCS0
XCS4
XCS5
BCLK
VSS
VDDE
D24
D25
VDDI
D26
D27
D28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VDDE
VSS
SDDATA27
SDDATA28
SDDATA29
SDDATA30
SDDATA31
SDDATA23
SDDATA22
VDDI
SDDATA21
SDDATA20
SDDATA19
SDDATA18
SDDATA17
SDDATA16
VSS
VDDE
SDDQM
XSDWE
XSDCAS
XSDRAS
XSDCS
SDCKE
SDCLK
VDDI
SDADRS3
SDADRS4
SDADRS5
SDADRS6
SDADRS7
SDADRS8
VDDE
VSS
SDADRS9
SDADRS2
SDADRS1
SDADRS0
SDADRS10
SDADRS11
VSS
VDDE
ASCLK
ADATA
VPDX
TESTMODE
ALRCK
ACLK
STREQ
XTST
VDDE
VSS
Fig. 2.2.1 : Pin arrangement diagram
MB86391
Product Specification
Rev. 1.1
12, November 2001
7
ADRS8
ADRS7
ADRS6
ADRS5
VDDE
VSS
SPCKE
SPSDCLK
VDDI
XSPWE
XSPCAS
XSPRAS
ADRS15
ADRS16
ADRS17
ADRS26
ADRS27
VSS
VDDE
D0
D1
D2
VDDI
D3
D4
D5
VDDE
VSS
D6
D7
D15
D14
D13
D12
D11
D10
D9
D8
VDDI
D16
D17
D18
VSS
VDDE
D19
D20
D21
D22
D23
D31
D30
D29
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2.2.2 Pin Numbers
Table 2.2.2 : Pin number list
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
−
O
O
O
O
O
O
−
−
O
O
O
O
−
−
I
O
I
I
−
I/O
I/O
I/O
−
−
I
I
I
I
I
I
I
I
−
−
O
O
O
O
O
O
O
O
O
−
−
I/O
I/O
−
I/O
I/O
I/O
Pin name
VDDI
TSPSSYNC
STEN
STDATA7
STDATA6
STDATA5
STDATA4
AVDD
AVSS
STDATA3
STDATA2
STDATA1
STDATA0
VSS
VDDE
STCLK
SDATAOUT
SDATAIN
SCLK
VDDI
XREADY
XRDWR
XAS
AVSS
AVDD
MCLKI
PLLTHR
CLKSEL
XBREQ
XBMREQ
IRQ8
IRQ9
XRESET
VDDE
VSS
XBGRNT
BUSDIR
XBUSEN
XEXTIRPT
XERROR
XCS0
XCS4
XCS5
BCLK
VSS
VDDE
D24
D25
VDDI
D26
D27
D28
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
−
I/O
I/O
I/O
−
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
−
I/O
I/O
I/O
−
I/O
I/O
I/O
−
−
I/O
I/O
I/O
I/O
I/O
O
O
O
−
O
O
−
−
I/O
I/O
I/O
I/O
Pin name
D29
D30
D31
D23
D22
D21
D20
D19
VDDE
VSS
D18
D17
D16
VDDI
D8
D9
D10
D11
D12
D13
D14
D15
D7
D6
VSS
VDDE
D5
D4
D3
VDDI
D2
D1
D0
VDDE
VSS
ADRS27
ADRS26
ADRS17
ADRS16
ADRS15
XSPRAS
XSPCAS
XSPWE
VDDI
SPSDCLK
SPCKE
VSS
VDDE
ADRS5
ADRS6
ADRS7
ADRS8
Pin No.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
I/O
I/O
I/O
I/O
−
−
−
I/O
I/O
I/O
I/O
I/O
I/O
−
−
I
I
I
I
I
I
I
I
−
I
I
I
I
I
−
−
I/O
I/O
I/O
I/O
I/O
I/O
−
−
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
I/O
I/O
I/O
I/O
I/O
I/O
Pin name
ADRS9
ADRS10
ADRS11
VDDI
VDDE
VSS
ADRS4
ADRS3
ADRS2
ADRS12
ADRS13
ADRS14
VSS
VDDE
DVIDEO0
DVIDEO1
DVIDEO2
DVIDEO3
DVIDEO4
DVIDEO5
DVIDEO6
DVIDEO7
VDDI
XVALID
FIELD
XVSYNC
XHSYNC
VCLK
VDDE
VSS
SDDATA8
SDDATA9
SDDATA10
SDDATA11
SDDATA12
SDDATA13
VSS
VDDE
SDDATA14
SDDATA15
SDDATA7
SDDATA6
SDDATA5
SDDATA4
SDDATA3
VDDI
SDDATA2
SDDATA1
SDDATA0
SDDATA24
SDDATA25
SDDATA26
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
I/O
−
−
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
I/O
I/O
I/O
I/O
I/O
I/O
−
−
O
O
O
O
O
O
O
−
O
O
O
O
O
O
−
−
O
O
O
O
O
O
−
−
I
I
I
I
I/O
I/O
I
I
−
−
Pin name
VDDE
VSS
SDDATA27
SDDATA28
SDDATA29
SDDATA30
SDDATA31
SDDATA23
SDDATA22
VDDI
SDDATA21
SDDATA20
SDDATA19
SDDATA18
SDDATA17
SDDATA16
VSS
VDDE
SDDQM
XSDWE
XSDCAS
XSDRAS
XSDCS
SDCKE
SDCLK
VDDI
SDADRS3
SDADRS4
SDADRS5
SDADRS6
SDADRS7
SDADRS8
VDDE
VSS
SDADRS9
SDADRS2
SDADRS1
SDADRS0
SDADRS10
SDADRS11
VSS
VDDE
ASCLK
ADATA
VPDX
TESTMODE
ALRCK
ACLK
STREQ
XTST
VDDE
VSS
VDDE : 3.3V power supply, VDDI : 1.8V power supply, AVDD : 1.8V power supply to PLL
VSS, AVSS : ground
MB86391
Product Specification
Rev. 1.1
12, November 2001
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2.3
Pin Functions
The pin functions of this LSI are shown below.
2.3.1 Overall Control
Table 2.3.1 : Overall control pins
Pin No.
Pin symbol
Pin name
Bit I/O Active
Pull up
/down
Internal
Clock
Select
1
I
−
−
Main Clock
Input
1
I
−
−
Description
Internal controller operating frequency
selection input pin. When the screen size
is D1, select 54MHz operations.
‘H’ = 54MHz operations
‘L’ = 27MHz operations
Operating clock (27MHz) input pin
28
CLKSEL
26
MCLKI
33
XRESET
Reset
1
I
L
−
Reset signal input pin
27
PLLTHR
PLL through
1
I
−
−
Internal PLL control signal input pin
(See figure on page 52)
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2.3.2 Host/SDRAM interface
Table 2.3.2 : Host/SDRAM interface pins
Pin No.
44
88,89
Pin symbol
BCLK
ADRS27:26
90 to 92,
116 to 114,
ADRS17:2
107 to 101,
111 to 113
55 to 50,48,47,
56 to 60,
63 to 65,
D31:0
74 to 67,75,76,
79 to 81,
83 to 85
32,31
IRQ9:8
23
XAS
22
XRDWR
41
XCS0
43,42
XCS5:4
Pin name
Bit I/O Active
Pull
up/down
Bus Clock
1
O
−
−
Address
27:26
2
I/O
−
−
Pin function
Host/SDRAM interface bus clock
(27MHz) output pin
Address (upper 2bits) I/O pins
Address (lower 16bits) I/O pins
Address
17:2
16
I/O
−
−
32bit data I/O pins
32
I/O
−
−
2
I
L
pullup
1
I/O
L
−
1
I/O
−
−
1
O
L
pullup
2
O
L
−
1
I
L
pullup
1
I
L
pullup
1
O
L
−
Bus grant output pin
1
O
L
−
Bus buffer enable output pin
1
O
−
−
Bus buffer direction control output pin
Ready
1
I/O
L
−
Ready I/O pin
Data31:0
Interrupt
Request 9:8
Address
Strobe
Read/Write
Chip Select
0
Chip Select
5:4
Burst Mode
Request
Bus
Request
Interrupt request input pins. When not in
use, connect to either OPEN or VDDE.
Address strobe I/O pin
Read/write I/O pin:
‘H’ = Read
‘L’ = Write
Chip select 0 output pin
Chip select 5:4 output pins
Burst transfer request input pin
30
XBMREQ
29
XBREQ
36
XBGRNT
38
XBUSEN
37
BUSDIR
21
XREADY
39
XEXTIRPT
External
Interrupt
1
O
L
−
External host interruption request pin
40
XERROR
Error
1
O
L
−
Error output pin
95
XSPWE
1
O
L
−
94
XSPCAS
1
O
L
−
93
XSPRAS
1
O
L
−
Write enable output pin to SDRAM
connected to host/SDRAM interface
Column address strobe output pin to
SDRAM connected to host/SDRAM
interface
Row address strobe output pin to SDRAM
connected to host/SDRAM interface
98
SPCKE
1
O
H
−
97
SPSDCLK
1
O
−
−
Bus Grant
Bus Buffer
Enable
Bus Buffer
Direction
Write
Enable
Column
Address
Strobe
Row
Address
Strobe
Clock
Enable
SDRAM
Clock
MB86391
Product Specification
Rev. 1.1
Bus privilege request input pin
Clock enable output pin to SDRAM
connected to host/SDRAM interface
Clock output pin to SDRAM connected to
hos t/SDRAM interface
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2.3.3 Serial Interface
Table 2.3.3: Serial interface pins
Pin No.
Pin symbol
19
SCLK
18
SDATAIN
17
SDATAOUT
Pin name
Serial Clock
Serial Data
Input
Serial Data
Output
Bit I/O Active
Pull
up/down
Pin function
1
I
−
−
Serial I/F serial clock input pin.
1
I
−
−
Serial I/F data input pin.
1
O
−
−
Serial I/F data output pin.
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2.3.4 SDRAM Interface for Video Encoding
Table 2.3.4: SDRAM interface pins for video encoding
Pin No.
196,195,191,
188 to 183,
192 to 194
163 to 159,
156 to 154,
164,165,
167 to 172,
144,143,
140 to 135,
145 to 149,
151 to 153
Pin symbol
SDADRS11:0
SDDATA31:0
Pin name
SDRAM
Address
SDRAM
Data
Bit I/O
Active
Pull
up/down
12
−
−
O
Address output (12bits) pins to SDRAM
connected to the video encoding SDRAM
interface
Data I/O (32bits) pins to SDRAM
connected to the video encoding SDRAM
interface
32 I/O
−
pullup
175
SDDQM
Input Mask
/Output
Enable
1
O
H
−
176
XSDWE
Write
Enable
1
O
L
−
177
XSDCAS
1
O
L
−
178
XSDRAS
1
O
L
−
179
XSDCS
Chip Select
1
O
L
−
180
SDCKE
Clock
Enable
1
O
H
−
181
SDCLK
SDRAM
Clock
1
O
−
−
Column
Address
Strobe
Row
Address
Strobe
MB86391
Product Specification
Rev. 1.1
Pin function
Data mask output pin to SDRAM
connected to the video encoding SDRAM
interface
Write enable output pin to SDRAM
connected to the video encoding SDRAM
interface
Column address strobe output pin to
SDRAM connected to the video encoding
SDRAM interface
Row address strobe output pin to SDRAM
connected to the video encoding SDRAM
interface
Chip select output pin to SDRAM
connected to the video encoding SDRAM
interface
Clock enable output pin to SDRAM
connected to the video encoding SDRAM
interface
Clock output pin to SDRAM connected to
the video encoding SDRAM interface
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2.3.5 Video Input Interface
Table 2.3.5: Video input interface pins
Pin No.
Pin symbol
132
VCLK
130
XVSYNC
131
XHSYNC
129
FIELD
128
XVALID
126 to 119
DVIDEO7:0
Pin name
Bit I/O Active
Pull
up/down
Pin function
1
I
−
−
Video clock input pin.
1
I
L
−
Vertical sync input pin.
1
I
L
−
Horizontal sync input pin.
Field
1
I
−
−
Field ID input pin.
Data Valid
1
I
L
−
Digital
Video
8
I
−
−
Input pin to indicate that valid data exists
at DVIDEO7:0.
Video input data input pin.
Video Clock
Vertical
Sync
Horizontal
Sync
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2.3.6 Audio Input Interface
Table 2.3.6:Audio input interface pins
Pin No.
Pin symbol
199
ASCLK
203
ALRCK
204
ACLK
200
ADATA
Pin name
Audio
System
Clock
Audio L/R
Clock
Audio Bit
Clock
Audio Serial
Data
Bit I/O Active
Pull
up/down
1
I
−
−
1
I/O
−
−
1
I/O
−
−
1
I
−
−
MB86391
Product Specification
Rev. 1.1
Pin function
System clock input pin for audio. Input
clock 256 times the audio sampling
frequency. Must be in sync with MCLKI.
Audio sampling clock pin. The pin outputs
in master mode and inputs in slave mode.
Audio bit clock pin. The pin outputs in
master mode and inputs in slave mode.
Audio serial data input pin.
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2.3.7 Bit Stream Output Port
Table 2.3.7: Bit stream output port pins
Pin No.
Pin symbol
16
STCLK
205
STREQ
3
STEN
4 to 7,10 to 13
STDATA7:0
2
TSPSSYNC
Pin name
Bit Stream
Transfer
Clock
Bit Stream
Transfer
Request
Bit Stream
Output
Enable
Bit Stream
Data7:0
TS/PS Sync
Bit I/O Active
Pull
up/down
1
I
−
pullup
1
I
H
−
1
O
H
−
8
O
−
−
1
O
H
−
MB86391
Product Specification
Rev. 1.1
Pin function
Bit stream transfer clock input pin. The
clock is for stream reading in transfer
clock sync mode.
Bit stream transfer request input pin.
When transferring streams in transfer
clock sync mode, connect to VDDE.
Bit stream output enable output pin.
Bit stream output port (8bit) pin. The error
code is output in case of an error.
This output pin indicates the leading data
of the TS/PS packet. 1cycle is set to 'H" at
the sync byte of the packet in the case of
TS and at the leading byte of the PACK
header or PS end code in the case of PS.
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2.3.8 Test Signals
Table 2.3.8: Test pins
Pin No.
Pin symbol
Pin name
Bit I/O Active
201
VPDX
−
1
I
H
202
TESTMODE
−
1
I
H
206
XTST
−
1
I
L
MB86391
Product Specification
Rev. 1.1
Pull
up/down
Pin function
A test pin. For typical usage, connect to
VSS.
A test pin. For typical usage, connect to
pull down
OPEN or VSS.
−
pull up
A test pin. For typical usage, connect to
OPEN or VDDE.
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3 Functional Description
3.1
Host/SDRAM Interface
The host/SDRAM interface arbitrates bus privilege between the external master connected to this interface and
MB86391 internal resources and also controls access to external resources (such as SDRAM, boot ROM, and
MPEG decoder). Fig. 3.1 shows an example host/SDRAM interface connection. The next and subsequent
chapters show timing diagrams for various accesses.
BCLK(O)[27MHz]
XAS(I/O)
XRDWR(I/O)
XREADY(I/O)
XCS5,4,0(O)
XCS4 or 5
XCS0
XBREQ(I)
XBMREQ(I)
External
master
XBGRNT(O)
B
A
ADRS27:26,17:2(I/O)
DIR
OE
Bus transceiver (equivalent to LVx245)
B
A
D31:0( I/O)
DIR
BUSDIR(O)
OE
XBUSEN(O)
CS
SDRAM
OE
MPEG
decoder
Boot
ROM
16Mbit×2
SPSDCLK(O)[54MHz]
(×16bit type)
D
A15:0
or
XSPRAS(O)
64Mbit×1
XSPCAS(O)
(×32bit type)
A18:16
XCS, DQM
XSPWE(O)
Fixed to "L"
STDATA2:0(O)
MB86391
Fig. 3.1: Host/SDRAM interface connection (Example)
Note: In the case of a 16Mbit SDRAM, connect ADRS13:2 to BA, A10:0. In the case of a 64Mbit
SDRAM, connect ADRS13:2 to BA1, A10:0. Keep BA0 fixed to ’H’ or ’L.’
Install the MB86391 and the SDRAM as physically close as possible.
Pull up the SPSDCLK signal line with a resistance of 200Ω in the vicinity of the SDRAM.
The SPSDCLK signal line must be in a pattern of a single stroke, from the MB86391, the
sending end, through the SDRAM CLK to the point of connection to the pull− up resistance.
Other signal lines do not require any particular handling such as pull− up. However, take
care to avoid unnecessary routing when designing patterns.
MB86391 can connect each bit width of boot ROM such as ×8bit, ×16bit and ×32bit.
(Recommended ×16bit) Recommended boot ROM size is over 4Mbit.
Fig. 3.1: Host/SDRAM interface connection (Example)
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3.1.1 Access by External Master
Shown below are diagrams of timing according to which the external master accesses MB86391
internal resources and SDRAM and peripheral chips (MPEG2 decoder LSI, for example)
connected to this interface.
3.1.1.1 MB86391 Internal Resource Accessing
(a) Write
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
All ‘H ’
All ‘ H’
XCS5,4,0(O)
XREADY( I/O)
D31:0( I/O)
All ‘H ’
All ‘ H’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.1.1a:MB86391 internal resource access timing (Write)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26, 17:2 and D31:0 to
Hi− Z and BUSDIR to 'L' (write direction) and asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XRDWR, ADRS27:26, 17:2 and D31:0 and asserts the
XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to
Hi− Z.
(5) After writing data, the MB86391 asserts XREADY and notifies the external master of write
completion.
(6) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state.
Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is
allowed.
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(b) Read
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
All ‘H ’
All ‘ H’
XCS5,4,0(O)
XREADY(I/O)
D31:0( I/O)
All ‘H ’
All ‘H ’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.1.1b: MB86391 internal resource access timing (Read))
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26, 17:2 and D31:0 to
Hi− Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XRDWR and ADRS27:26, 17:2 and asserts the XAS
signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to
Hi− Z.
(5) The MB86391 sets BUSDIR to ’H’ (read direction) to allow read data output.
(6) The MB86391 outputs valid data to D31:0 at the same time as it asserts XREADY (the external
master fetches read data at this timing).
(7) The MB86391 negates XBUSEN and resets to its normal state.
Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is
allowed.
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3.1.1.2 SDRAM Accessing
(a) Single write
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
All ‘H ’
All ‘H’
RA
CA
All ‘H ’
XCS5,4,0(O)
XREADY( I/O)
D31:0( I/O)
All ‘H ’
All ‘ H’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.1.2a:SDRAM access timing (Single write)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to
Hi− Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XRDWR, ADRS27:26, 17:2, and D31:0 and asserts the
XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to
Hi− Z.
(5) The MB86391 re− outputs the address fetched in (4) to the SDRAM at the command.
(6) The MB86391 asserts the XREADY signal during the cycle to write data to the SDRAM and
notifies it to the external master.
(7) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state.
Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is
allowed.
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(b) Single read
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
All ‘H ’
All ‘H’
RA
CA
All ‘H ’
XCS5,4,0(O)
XREADY( I/O)
D31:0( I/O)
All ‘H ’
All ‘ H’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.1.2b: SDRAM access timing (Single read)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to
Hi− Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XRDWR and ADRS27:26, 17:2 and asserts the XAS
signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26, 17:2 to
Hi− Z.
(5) The MB86391 re− outputs the address fetched in (4) to the SDRAM at the command.
(6) The MB86391 sets BUSDIR to ’H’ (read direction) to allow read data output.
(7) The MB86391 asserts the XREADY signal during the SDRAM data read cycle and notifies it to
the external master.
(8) The MB86391 negates XBUSEN and resets to its normal state.
Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is
allowed.
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(c) Burst write
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
All ‘H ’
All ‘H’
RA
CA
CA+1
CA+2
WD+1
WD+2
CA+3
All ‘H ’
XCS5,4,0(O)
XREADY( I/O)
D31:0( I/O)
All ‘H ’
WD
WD+3
All ‘ H’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.1.2c: SDRAM access timing (Burst write))
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to
Hi− Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XBMREQ, XRDWR, ADRS27:26, 17:2, and D31:0 and
asserts the XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to
Hi− Z.
(5) The MB86391 re− outputs the address fetched in (4) to the SDRAM at the command.
(6) The MB86391 asserts the XREADY signal during the cycle to write data to the SDRAM and
notifies it to the external master.
(7) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state.
Notes: The burst length is fixed to 4.
After negating XREADY, the next request for bus privilege (asserting XBREQ)
is allowed.
Burst access extending over 1 KB is not allowed.
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(d) Burst read
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS(I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
All ‘H ’
All ‘H’
RA
CA
CA+1
CA+2
CA+3
All ‘H ’
XCS5,4,0(O)
XREADY( I/O)
D31:0( I/O)
All ‘H ’
WD
WD+1
WD+2
WD+3
All ‘ H’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.1.2d: SDRAM access timing (Burst read)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to
Hi− Z and BUSDIR to 'L' (write direction and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XBMREQ, XRDWR and ADRS27:26, 17:2 and asserts
the XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to
Hi− Z.
(5) The MB86391 re− outputs the address fetched in (4) to the SDRAM at the command.
(6) The MB86391 sets BUSDIR to ’H’ (read direction) to allow SDRAM read data output.
(7) The MB86391 asserts the XREADY signal during the SDRAM data read cycle and notifies it to
the external master.
(8) The MB86391 negates XBUSEN and resets to its normal state.
Notes: The burst length is fixed to 4.
After negating XREADY, the next request for bus privilege (asserting XBREQ)
is allowed.
Burst access extending over 1 KB is not allowed.
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3.1.1.3 External Resource Accessing
(a) Write
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
All ‘H ’
WA
All ‘H’
WA
WA
All ‘ H’
XCS5,4(O)
XREADY( I/O)
D31:0( I/O)
All ‘H ’
WD
WD
All ‘H ’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.1.3a: External resource access timing (Write)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to
Hi− Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XRDWR, ADRS27:26, 17:2, and D31:0 and asserts the
XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT.
At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26, 17:2 to
Hi− Z.
(5) After setting XREADY to Hi− Z, the MB86391 asserts the appropriate XCSn(n = 5,4) and
re− outputs XAS, XRDWR, and ADRS27:26, 17:2 fetched in (4) to the external resource.
(6) The external resource asserts the XREADY signal and notifies that data write is complete.
(7) The MB86391 negates XBUSEN and XREADY, sets BUSDIR to ‘H’ (read direction) and resets to
its normal state.
Notes: After negating XREADY, the next request for bus privilege (asserting XBREQ)
is allowed.
The external resource needs to be set to Hi− Z after setting XREADY to 'H.'
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(b) Read
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XAS( I/O)
XRDWR( I/O)
ADRS27:26, 17:2(I/O)
All ‘H ’
RA
All ‘H’
RA
RA
All ‘ H’
XCS5,4(O)
XREADY( I/O)
D31:0( I/O)
All ‘H ’
RD
All ‘H ’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.1.3b: External resource access timing (Read)
(1) The external master asserts XBREQ and requests for bus privilege.
(2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26, 17:2 and D31:0 to
Hi− Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus
privilege to the external master.
(3) The external master outputs valid data to XRDWR and ADRS27: 26, 17:2 at the same as it
asserts the XAS signal. Note that XBREQ must be asserted up to this cycle.
(4) After fetching the address and control signal statuses in (3), the MB86391 negates XBGRNT. At
negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26, 17:2 to
Hi− Z.
(5) After setting XREADY to Hi− Z, the MB86391 asserts the appropriate XCSn(n = 5,4) and
re− outputs XAS, XRDWR, and ADRS27:26,17:2 fetched in (4) to the external resource.
(6) The external resource asserts the XREADY signal and notifies that valid data is output to D31:0.
(7) The MB86391 negates XBUSEN and XREADY, sets BUSDIR to 'H' (read direction), and resets to
normal state.
Notes: After negating XREADY, the next request for bus privilege (asserting XBREQ)
is allowed.
The external resource needs to be set to Hi− Z after setting XREADY to 'H."
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3.1.2 Internal Controller Master Accessing
Shown below are diagrams of timing according to which the MB86391 internal controller
accesses peripheral chips (such as the MPEG2 decoder LSI) connected to this interface.
3.1.2.1 External Resource Accessing
(a) Write
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XRDWR( I/O)
XAS( I/O)
ADRS27:26, 17:2(I/O)
All ‘ H’
WA
WA
All ‘ H’
XCS5,4(O)
XREADY( I/O)
D31:0( I/O)
All ‘H ’
WD
WD
All ‘ H’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.2.1a: External resource access timing (Write)
(1) The MB86391 sets XREADY to Hi− Z and asserts XBUSEN to prepare for accessing.
(2) With XCSn (n = 5,4) asserted, the controller selects an external resource and, in conjunction with
XAS assertion, outputs valid data to XRDWR, ADRS27:26, 17:2 and D31:0.
(3) When the external resource asserts the XREADY signal, the MB86391 negates XCSn (n = 5,4)
and sets XRDWR to ’H’ (read, normal state) at the same time as the selection is cancelled
(4) The controller negates the XBUSEN and XREADY signals to reset to its normal state.
Note: The external resource needs to be set to Hi− Z after setting XREADY to 'H.'
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(b) Read
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XRDWR( I/O)
XAS( I/O)
ADRS27:26, 17:2(I/O)
All ‘ H’
RA
RA
All ‘ H’
XCS5,4(O)
XREADY( I/O)
D31:0( I/O)
All ‘ H’
RD
All ‘H ’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.2.1b: External resource access timing (Read)
(1) The MB86391 sets BUSDIR to 'L' (read direction) and XREADY to Hi− Z and asserts XBUSEN to
prepare for accessing.
(2) With XCSn (n = 5,4) asserted, the MB86391 selects an external resource and, in conjunction with
XAS, outputs valid data to ADRS27:26, 17:2.
(3) When the external resource outputs valid data to D31: 0 and asserts the XREADY signal in the
next cycle, the MB86391 reads the data, negates XCSn(n = 5,4), and cancels the selection.
(4) The controller sets BUSDIR to ‘H’ (write direction), negates the XBUSEN and XREADY signals,
and resets to its normal state.
Note: The external resource needs to be set to Hi− Z after setting XREADY to 'H.'
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3.1.2.2 External Boot ROM Read
BCLK(O)
XBREQ(I)
XBMREQ(I)
XBGRNT(O)
XRDWR( I/O)
XAS( I/O)
ADRS27:26, 17:2(I/O)
All ‘ H’
RA
RA
All ‘ H’
XCS0(O)
XREADY( I/O)
D31:0( I/O)
All ‘ H’
RD
All ‘ H’
XBUSEN(O)
BUSDIR(O)
Fig. 3.1.2.2: External boot ROM access timing (Read)
(1) With XCS0 asserted, the MB86391 selects the external boot ROM, sets BUSDIR to 'L' (read
direction) and XREADY to Hi− Z, and asserts XBUSEN to prepare for accessing.
(2) In conjunction with XAS, the MB86391 outputs valid data to ADRS27:26, 17:2 (let the external
boot ROM output read data to the data bus after confirming XCS0).
(3) After proper wait cycles, the MB86391 reads data and negates XCSO to cancel the selection.
(4) The MB86391 sets BUSDIR to ‘H’ (write direction), negates the XBUSEN and XREADY signals,
and resets to its normal state.
Note: The number of read wait cycles can be set in the boot program according to the
ROM in use. When defaulted, accessing is done with 30 wait cycles.
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3.1.3 Interruption
3.1.3.1 Internal Controller Interrupt Input (IRQ9:8)
This is the interrupt input to the internal controller. Use this input, for example, to control (using
dedicated firmware) the MB86373 (MPEG2 decoder LSI) with the internal controller. When not in
use, connect the input to either OPEN or VDDE (fixed to High).
3.1.3.2 Host Interrupt Output (XEXTIRPT)
This is the interrupt output from the internal controller to the external host. The firmware
dedicated to the internal controller notifies the external host of the end of command processing,
for example. (For more information, see "MB86391 Control Protocol Command Specification
(Parallel I/F)").
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3.1.4 Address Map
Table 3.1.4: MB86391 address map
Address
*1
Size (byte)
CSn
Description
0x0000000 to 0x0000FFF
0x0001000 to 0x003FFFF
0x4000000 to 0x401FFFF
4K
252K
128K
CS0
CS0
CS4
Internal boot ROM (for internal boot)
External ROM (for external boot)
External chip select 4
0x4020000 to 0x403FFFF
0x8000000 to 0x87FFFFF
0xC000000 to 0xC00FFFF
128K
8M
64K
CS5
−
−
External chip select 5
External SDRAM (8Mbytes)*2
TBC controller & filter
0xC010000 to 0xC01FFFF
0xC020000 to 0xC02FFFF
0xC100000 to 0xC10FFFF
64K
64K
64K
−
−
−
SDRAM controller
DMA controller
Video encoder
0xC200000 to 0xC20FFFF
0xC300000 to 0xC30FFFF
0xC400000 to 0xC40FFFF
64K
64K
64K
−
−
−
PES converter
Multiplexing controller
AUDIO buffer
0xC800000 to 0xC80FFFF
64K
−
Internal controller (internal register)
*1: Any space with no description is reserved.
*2: An area of 4 Mbytes is actually used.
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3.2
Serial Interface
The serial interface is provided for serial boot and serial API. Since this interface does not control flow with
hardware, you need to control the flow with firmware such as a driver. The firmware dedicated to the internal
controller uses ASCII mode.
3.2.1 Serial Interface Receive Operations
The serial interface supports the following receive data formats:
MODE
FM1
FM2
Data section
bit count (N)
Description
ASCII
Data32
0
1
MSB
0
7
32
ASCII code 0x00 to 0x7F and others
32−bit binary data
Fig. 3.2.1a-b shows serial interface receive timings.
SCLK
SDATAIN
FM 1=0
FM 2=
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Parity
Format
Start Bit
Stop Bit
Fig. 3.2.1a: Serial interface receive timings (ASCII mode)
SCLK
SDATAIN
FM1=1
FM2=0
Bit31
Bit30
Bit29
Bit28
Bit27
Bit0
Parity
Format
Start Bit
Stop Bit
Fig.3.2.1b: Serial interface receiver timing (Dara32 mode)
There are 2 type transport mode (SCLK synchronization mode and start-stop synchronization
mode). When using start − stop synchronization mode, pull the SDATAOUT pin down with about
3.3kΩ. When using SCLK synchronization mode, pull the SDATAOUT pin up with about 3.3kΩ. It
is not possible to change the transport mode during working.
In SCLK synchronization mode, data is taken on raising edge of SCLK.
In start − stop synchronization mode, data is taken according to 9600bps with reference to the
StartBit falling edge of the SDATAIN signal regardless of SCLK.
Use even parity from FM1 through DataN. After the parity bit, 1 is needed as StopBit. However,
if 0 is received at this point, it is recognized as a break signal and invalidates receive data.
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3.2.2 Serial Interface Send Operations
The serial interface supports the following send data formats
MODE
FM1
FM2
Data section
bit count (N)
Description
ASCII
Data32
0
1
MSB
0
7
32
ASCII code 0x00 to 0x7F and others
32−bit binary data (for others)
Fig. 3.2.2a-b shows serial interface send timings.
SCLK
SDATA OUT
FM1=0
FM 2=
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Parity
Format
Start Bit
Stop Bit
Fig. 3.2.2a: Serial interface send timings (ASCII mode)
SCLK
SDATA OUT
FM1=1
FM2=0
Bit31
Bit30
Bit29
Bit28
Bit27
Bit0
Parity
Format
Start Bit
Stop Bit
Fig. 3.2.2b: Serial interface send timings (DATA32 mode)
There are 2 type transport mode (SCLK synchronization mode and start-stop synchronization
mode). When using start − stop synchronization mode, pull the SDATAOUT pin down with about
3.3kΩ. When using SCLK synchronization mode, pull the SDATAOUT pin up with about 3.3kΩ. It
is not possible to change the transport mode during working.
Use even parity from FM1 through DataN.
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3.3
SDRAM Interface for Video Encoding
The SDRAM interface for video encoding controls access to an external SDRAM that the video encoder built
into this LSI uses to encode video input data.
Connect either two 16Mbit (512K×16bit×2bank configuration) SDRAMs or one 64Mbit (512K×32bit×4bank
configuration) SDRAM. Fig. 3.3 shows an example 64Mbit SDRAM connection.
64Mbit SDRAM
(MB81F643242B and others)
BA0
‘Fixed to H’ or ‘L’
BA1, A10:0
MB86391
SDADRS11:0
DQ31:0
SDDATA31:0
DQM3:0
SDDQM
WE
XSDWE
CAS
XSDCAS
RAS
XSDRAS
CS
XSDCS
CKE
SDCKE
CLK
SDCLK
Video encoding
SDRAM
interface
Note: Install the MB86391 and the SDRAM as physically close as possible.
Pull up the SDCLK signal line with a resistance of 200Ω in the vicinity of the SDRAM. The
SDCLK signal line must be in a pattern of a single stroke, from the MB86391, the sending
end, through the SDRAM CLK to the point of connection to the pull− up resistance.
Other signal lines do not require any particular handling such as pull− up. However, take
care to avoid unnecessary routing when designing patterns.
Fig. 3.3: Example video encoding SDRAM interface connection
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3.4
Video Input Interface
The video input interface is a dedicated interface between the MB86391 and an external device (such a an
NTSC decoder) connected to the MB86391. Fig. 3.4 shows an example connection.
MB86391
NTSC decoder (SAA7113)
VDO7:0
DVIDEO7:0
LCC
VCLK
“H”
XVSYNC
RTS0
XHSYNC
RTS1
FIELD
“H”
Video input
interface
XVALID
Fig. 3.4: Example video input interface connection
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3.4.1 Input Formats
The video input interface is compatible with the following data input formats:
(a) D1 parallel input mode
Input D1 format data to the DVIDEO7:0 pin.
The XVSYNC, XHSYNC, FIELD and XVALID pins are not used (keep them fixed to H.) since synchronization
information is extracted from the SAV/EAV signal in the D1 data.
(b) Y/C multiplex input mode
Input video data multiplexed in 4:2:2 format (CbYCr in that order) to DVIDEO7:0 pin as well as sync and valid
pixel signals to the XVSYNC, XHSYNC, FIELD and XVALID pins.
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3.5
Audio Input Interface
The audio input interface is a dedicated audio data interface between the MB86391 and the audio A/D
converter connected to the MB86391. Fig. 3.5 shows an example connection.
MB86391
ASCLK
LR_clock
Bit_clock
Audio A D C
Data
Audio input
interface
ALRCK
ACLK
ADATA
256fs
PLL
27MHz oscillation
Note:
MCLKI
MCLKI must be in sync with ASCLK.
Fig. 3.5: Example audio input interface connection (Master mode)
MB86391
ASCLK
LR_clock
Bit_clock
Audio A D C
Data
Audio input
interface
ALRCK
ACLK
ADATA
256fs
PLL
27MHz oscillation
Note:
MCLKI
MCLKI must be in sync with ASCLK.
Fig. 3.5: Example audio input interface connection (Slave mode)
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3.5.1 Master/Slave Mode
Master (the MB86391 outputs ACLK and ALRCK) and slave (input of ACLK and ALRCK from the
audio A/D converter to the MB86391) modes can be switched.
3.5.2 Input Formats
Setting each of the following parameters allows compatibility with various input formats:
(1) MSB first/LSB first of data
(2) Packing ALRCK with data (left/right packing))
(3) ALRCK polarity (‘H’=Lch, ’L’=Rch / ‘L’=Lch ’H’=Rch)
(4) Phase relationship between ALRCK and data (compatible with I2S interface)
The phase relationship between ALRCK and ACLK is adjustable by 256 fs in master mode.
ACLK(I/O)
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
ALRCK(I/O)
D
ADATA(I) MSB/LSB
D
D
D
16bit
D
D
D
LSB/MSB
D
MSB/LSB
D
D
MSB/LSB
D
D
D
16bit
D
LSB/MSB
D
D
16bit
D
D
D
D
LSB/MSB
D
MSB/LSB
D
D
D
16bit
D
D
LSB/MSB
Fig. 3.5.2: Input formats
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3.6
Bit Stream Output Port
The bit stream output port is compatible with various transfer modes described next:
(a) 27 MHz sync mode
This mode is for storage function products. The PCR(SCR) is made by the calculated value from
bit-stream and datasize.
BCLK(O)
STREQ(I)
STEN(O)
STDATA(O)
Valid
Valid
Valid
Valid
TSPSSYNC(O)
Fig. 3.6a: 27 MHz sync mode timings
(1) When ready to receive streams, set STREQ to 'H.'
(2) When valid data exists, the MB86391 sets STEN to ’H’ at STDATA to instruct data fetching. It
also sets the TSPSSYNC signal simultaneously to 'H' at the sync byte "0x47" if the stream is TS,
and at pack start code "0x000001BA" or at the leading byte of the program end code
"0x000001B9" if the stream is PS.
Notes: There is an instance during which two pieces of data are output at maximum
even if STREQ is set 'L.'
Limit the duration during which STREQ is set to ’L’ while encoding to a few tens
of clocks. The bit rate must also be maintained on the average (The MB86391
is equipped with an internal buffer to temporarily store bit streams. However,
the buffer fails if bit streams are not read for a lengthy period of time.)
(b) Handshake mode
This mode is for storage function products. The PCR(SCR) is made by the calculated value from
bit-stream and datasize.
BCLK(O)
STREQ(I)
STEN(O)
STDATA(O)
Valid
Valid
TSPSSYNC(O)
Fig. 3.6b: Handshake mode timings
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(1) When ready to receive streams, set STREQ to 'H.'
(2) When valid data exists, the MB86391 changes STEN ’H’→’L’ →’H’ at STDATA. It simultaneously
sets the TSPSSYNC signal to 'H' at the sync byte "0x47" if the stream is TS, and at the pack start
code "0x000001BA" or at the leading byte of the program end code "0x 000001B9" if the stream is
PS.
Note: Limit the duration during which STREQ is set to ’L’ while encoding to a few tens
of clocks. The bit rate must also be maintained on the average (The MB86391 is
equipped with an internal buffer to temporarily store bit streams. However, the
buffer fails if bit streams are not read for a lengthy period of time.)
(c) External clock sync mode(CBR)
This mode is for real time transfer function products. The PCR(SCR) is made by STCLK.
STCLK(I)
STREQ(I)
STEN(O)
STDATA(O)
Valid
Valid
Valid
Valid
TSPSSYNC(O)
Fig. 3.6c: External clock mode (CBR)
(1) Input the transfer clock to STCLK according to the bit and set STREQ to 'H.'
(2) While transferring, the MB86391 outputs 'H' to STEN at all times and outputs valid data according
to the external clock STCLK. It also simultaneously sets the TSPSSYNC signal to 'H' at the sync
byte "0x47" if the stream is TS, and at the pack start code "0x000001BA" or at the leading byte of
the program end code "0x000001B9" if the stream is PS.
Note: STCLK should be input over 1/8 x system bit-rate. (EX: When the system bit-rate
is 8Mbps, STCLK should be over 1MHz.) When STCLK is more high frequency
than system bit-rate which is setted, stuffing is implemented.
(d) External clock sync mode (VBR)
This mode is for real time transfer function products. The PCR(SCR) is made bySTCLK.
STCLK(I)
STREQ(I)
STEN(O)
STDATA(O)
Valid
Valid
Valid
Valid
TSPSSYNC(O)
Fig. 3.6d: External clock mode (VBR)
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(1) Input the transfer clock to STCLK according to the bit and set STREQ to 'H.'
(2) While transferring, the MB86391 outputs 'H' to STEN at all times and outputs valid data according
to the external clock STCLK. It also simultaneously sets the TSPSSYNC signal to 'H' at the sync
byte "0x47" if the stream is TS, and at the pack start code "0x000001BA" or at the leading byte of
the program end code "0x000001B9" if the stream is PS.
Note: Stuffing is implemented as necessary.
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3.7
Error Notification Function
The MB86391 has a built− in function to notify outside of an error when it occurs. In case of an error, it sets the
XERROR pin to 'L' to output error information from the bit stream output port. When the error information is
output, the STEN and TSPSSYNC pins are set to 'L' (Fig.3.7). Tables 3.7a and 3.7b list the pins and error
descriptions related to occurrence of errors.
Table 3.7a: Error list
7
6
Pin status
STDATA
5 4 3 2 1
1
−
−
−
0
0
0
0
0
1
0
1
0
1
0
0
XERROR
−
−
−
−
Sub−error code
Sub−error code
Sub−error code
0
−
Error description
STEN
TSPSSYNC
−
−
No error (normal stream output)
0
0
0
0
0
0
Timeout error
External illegal access error
Program error
Table 3.7b: Sub− error code list
Sub− error code
Description
0
0
0
0
0
0
0
0
0
1
Reset status
Firmware startup
0
0
1
0
0
1
0
to
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
Boot complete
Boot in progress
Boot mode error
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
Boot header keyword error
Boot header checksum error
Data block header keyword error
1
1
1
0
0
1
1
1
0
1
1
0
0
1
0
Data block header checksum error
Data block checksum error
1
1
to
1
1
1
Reserved
Reserved
Note: Being dependent on the firmware, this code is
subject to change and addition.
BCLK(O)
TSPSSYNC(O)
STEN(O)
STDATA(O)
ERROR
XERROR(O)
2cycle(max.)
Fig. 3.7: Error information output timings
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3.8
Boot Operations
The MB86391 starts booting operations when the internal controller starts the boot program of the internal
ROM. The program required for the operation is downloaded to the SDRAM interface connected to the
host/SDRAM according to the processing flow in Fig. 3.8. Each downloading procedure is described in the next
and subsequent chapters.
Start boot
Initialize
Check external
ROM keyword
Keyword OK?
YES
External ROM download
YES
Serial download
YES
Immediately start
SDRAM.
NO
Check serial API
Data exists?
NO
Check parallel API
Startup request?
NO
Fig. 3.8: Booting flow
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3.8.1 Downloading from the External ROM
This mode downloads the program from an external ROM to the SDRAM. When the boot
program of the internal ROM confirms of the external ROM, start downloading from the external
ROM to SDRAM via MB86391. After downloading, MB86391 starts the program on SDRAM.
When the existence of an external ROM is confirmed, the program re− sets the wait count
specified with "wait" in the header to download the data to be downloaded. The download data
configuration is not dependent on the ROM bus width.
3.8.2 Serial Download
The internal ROM boot program of the MB86391 sets to either serial API or SDRAM direct
download mode (see Chapter 3.8.3) if it confirms that there is no external ROM.
Upon arrival of an interrupt from the serial interface, the internal ROM boot program of the
MB86391 receives the data transferred with the serial interface and, if the header of this data is
configured as shown in Table 3.8.2a, downloads it as serial API.
The internal serial interface of the MB86391 supports Data32 and ASCII send and receive data
formats (see Chapter 3.2). Since data can also be sent with SCLK synchronization or
Asynchronization (9,600bps), four types of serial booting are available (Data32/SCLK
synchronization, ASCII/SCLK synchronization, Data32/Asynchonization, and
ASCII/Asynchronization).
3.8.3 Direct SDRAM Downloading
The SDRAM connected to the MB86391 host/SDRAM is assigned in the CS1 space by the
internal ROM boot initialization routine. From the host interface with the parallel API, the entire
SDRAM area is accessible if used with a bank register. This enables to write the program and
data (including the header in Table 3.8.3) from the host/SDRAM interface to the SDRAM by
directly accessing the memory.
During this period, the internal ROM boot program of the MB86391 is in an infinite loop waiting for
interruption. Therefore, from the host/SDRAM interface, instruct to start the program by
executing parallel API interruption (by writing to the register) after direct downloading to the
SDRAM is complete.
The internal ROM boot program of the MB86391 verifies that the appropriate header is in from
the SDRAM leading address and then jumps to the Entry Address to start executing the program.
MB86391
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Rev. 1.1
12, November 2001
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4 Electrical Characteristics
4.1
Maximum Ratings
Table 4.1: Maximum ratings
Item
Symbol
Max. ratings
Unit
Supply voltage*1
VDDI
VDDE
AVDD
−0.5 to 2.5
−0.5 to 4.0
−0.5 to 2.5
V
Input voltage
Output voltage
Output current
VI
VO
IO
−0.5 to VDDE+0.5 (≤4.0)
−0.5 to VDDE+0.5 (≤4.0)
+13/−13
V
V
mA
Operating temperature
Storage temperature
Ta
TST
-20 to 85
−55 to 125
°C
°C
*1: VDDI – Internal logic power supply, VDDE – External I/O power supply, AVDD −
PLL power supply
MB86391
Product Specification
Rev. 1.1
12, November 2001
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FUJITSU LIMITED
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4.2
Recommended Operating Conditions
4.2.1 Recommended Operating Conditions
Table 4.2.1: Recommended operating conditions
Min.
Ratings
Typical
Max.
VDDI
VDDE
1.65
3.0
1.8
3.3
1.95
3.6
AVDD
1.65
1.8
1.95
3.3V
VIH
2.0
−
VDDE+0.3
V
3.3V
VIL
−0.3
−
0.8
V
Ta
-20
25
85
°C
Item
Symbol
Supply voltage
H−level
input
voltage
L−level
input
voltage
Operating temperature
Unit
V
4.2.2 Precautions When Connecting the Power
• Although VDDI, VDDE and AVDD can be turned on and off in any order, Fujitsu recommends
the following order:
Turning on:VDDI, AVDD(internal) → VDDE(external) → signals
Turning off:signals → VDDE(external) → VDDI, AVDD(internal)
Do not keep VDDE (external) alone pressed (for more than a few seconds) with VDDI and
AVDD (internal) disconnected.
• The following power supply sequence applies to 5V tolerant I/O
Before turning on the device, never input 5V input signals (observe the maximum ratings at
all times). Otherwise, you might destroy the device.
• After turning on the power, keep the PLLTHR pin set to the L level for more than 2µs. Next,
set the PLLTHR pin to the H level and then input the L level to the XRESET signal for more
than 300µs.
MB86391
Product Specification
Rev. 1.1
12, November 2001
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FUJITSU LIMITED
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4.3
DC Characteristics
Measurement conditions:VDDI=1.65 to 1.95V, VDDE=3.0 to 3.6, VSS=0.0V, Ta=-20 to 85°C
Min.
Ratings
Typical
Max.
VOH
VDDE−0.2
−
VDDE
V
VOL
IOH1 *6
IOH2 *5
0.0
−4.0
−8.0
−
0.2
V
−
−
mA
4.0
8.0
−
−
−
mA
Input leakage current
IOL1 *6
IOL2 *5
IL
−
+5 / −5
µA
Pull up/down resistance
Pin capacity
Rp
C
10
−
25
−
70
16
kΩ
PF
Item
Symbol
H−level output voltage*1
L−level output voltage*2
H−level output current*3
L−level output current*4
*1: Condition IOH=−100µA
*2: Condition IOL=100µA
*3: Condition VOH=VDDE−0.4V
*4: Condition VOL=0.4V
*5: BCLK, SPSDCLK, and SDCLK signal output characteristics
*6: Output characteristics of signals other than those in *5
MB86391
Product Specification
Rev. 1.1
Unit
12, November 2001
46
FUJITSU LIMITED
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4.4
AC Characteristics
4.4.1 Overall Control
4.4.1.1 Clock Input
1/f MCLKI
t HMCLKI
t LMCLKI
MCLKI
Item
MCLKI frequency
MCLKI H duration
MCLKI L duration
Symbol
fMCLKI
tHMCLKI
tLMCLKI
MB86391
Product Specification
Rev. 1.1
Condition
Min.
Standard
Typical
Max.
−
14
14
27
−
−
−
−
−
12, November 2001
47
Unit
MHz
ns
ns
FUJITSU LIMITED
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4.4.1.2 Reset Input
(a) After turning the power on
PLLTHR
tLPLLTHR
XRESET
tLRESET
Item
PLLTHR L duration
XRESET L duration
Symbol
Condition
tLPLLTHR
tLRESET
Min.
2
300
Standard
Typical
−
−
Max.
−
−
Min.
Standard
Typical
Max.
500
−
−
Unit
µs
µs
(b) Other than after turning the power on
XRESET
tLRST
Item
XRESET L duration
Symbol
tLRST
MB86391
Product Specification
Rev. 1.1
Condition
12, November 2001
48
Unit
ns
FUJITSU LIMITED
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4.4.2 Host/SDRAM Interface
4.4.2.1 Host Interface
Clock (BCLK)
1/fBCLK
tHBCLK
tLBCLK
BCLK
Item
BCLK frequency
BCLK H duration
BCLK L duration
Symbol
fBCLK
tHBCLK
tLBCLK
MB86391
Product Specification
Rev. 1.1
Condition
Min.
Standard
Typical
Max.
−
13
13
27
−
−
−
−
−
12, November 2001
49
Unit
MHz
ns
ns
FUJITSU LIMITED
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Input sigals
BCLK
ADRS, D, IRQ, XAS,
XRDWR, XBMREQ,
XBREQ, XREADY
t IADRSS, tIDS, tIRQS , t IASS, t IRWS,
t BMRQS, t BRQS, tIRDYS
tIADRSH, tIDH, t IRQH, t IASH, tIRWH,
tBMRQH, t BRQH, t IRDYH
Output signals
BCLK
ADRS, D, XAS,
XRDWR, XCS,
XBGRNT, XBUSEN,
BUSDIR, XREADY,
XEXTIRPT, XERROR
t OADRSD, t ODD, tOASD , t ORWD, t CSD,
t BGRNTD, tBED, t BDD, tORDYD , tEID, tERRD
MB86391
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Rev. 1.1
12, November 2001
50
FUJITSU LIMITED
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Item
Address input setup time
Address input hold time
Address output delay time
Data input setup time
Data input hold time
Data output delay time
IRQ setup time
IRQ hold time
XBREQ setup time
XBREQ hold time
XBMREQ setup time
XBMREQ hold time
XBGRNT delay time
XRDWR input setup time
XRDWR input hold time
XRDWR output delay time
XAS input setup time
XAS input hold time
XAS output delay time
XCS delay time
XREADY input setup time
XREADY input hold time
XREADY output delay time
XBUSEN delay time
BUSDIR delay time
XEXTIRPT delay time
XERROR delay time
Symbol
tIADRSS
tIADRSH
tOADRSD
tIDS
tIDH
tODD
tIRQS
tIRQH
tBRQS
tBRQH
tBMRQS
tBMRQH
tBGRNTD
tIRWS
tIRWH
tORWD
tIASS
tIASH
tOASD
tCSD
tIRDYS
tIRDYH
tORDYD
tBED
tBDD
tEID
tERRD
MB86391
Product Specification
Rev. 1.1
Condition
Min.
7
0.5
3
7.5
0
3
7
0
7
0
7
0
3
7
0
3
7
0
3
3
7
0
3
3
3
3
3
Standard
Typical
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max.
−
−
12
−
−
12
−
−
−
−
−
−
12
−
−
12
−
−
12
12
−
−
12
12
12
12
12
12, November 2001
51
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FUJITSU LIMITED
Proprietary and Confidential
4.4.2.2 SDRAM Interface Signals
Clock (SPSDCLK)
1/f SPSDCLK
tHSPSDCLK
tLSPSDCLK
SPSDCLK
Item
Symbol
SPSDCLK frequency
SPSDCLK H duration
SPSDCLK L duration
fSPSDCLK
tHSPSDCLK
tLSPSDCLK
Condition
Min.
Standard
Typical
Max.
−
6.5
6.5
54
−
−
−
−
−
Input signals
SPSDCLK
D31:0
t RDS
t RDH
Output signals
SPSDCLK
D31:0, ADRS14:2,
XSPWE, XSPCAS,
XSPRAS, SPCKE
tWDD, tADRSD , tSPWED,
tSPCASD , tSPRASD , tSPCKED
MB86391
Product Specification
Rev. 1.1
12, November 2001
52
Unit
MHz
ns
ns
FUJITSU LIMITED
Proprietary and Confidential
Item
Address output delay time
Read data setup time
Read data hold time
Data output delay time
SPWE delay time
SPCAS delay time
SPRAS delay time
SPCKE delay time
Symbol
tADRSD
tRDS
tRDH
tWDD
tSPWED
tSPCASD
tSPRASD
tSPCKED
MB86391
Product Specification
Rev. 1.1
Condition
Min.
3
7
0
3
3
3
3
3
Standard
Typical
−
−
−
−
−
−
−
−
Max.
12
−
−
12
12
12
12
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
12, November 2001
53
FUJITSU LIMITED
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4.4.3 Serial Interface
Clock (SCLK)
1/fSCLK
tHSCLK
tLSCLK
SCLK
Item
SCLK frequency
SCLK H duration
SCLK L duration
Symbol
Condition
fSCLK
tHSCLK
tLSCLK
Min.
−
200
200
Standard
Typical
−
−
−
Max.
2
−
−
Unit
MHz
ns
ns
Input signals
SCLK
SDATAIN
t SDIS
t SDIH
Output signals
SCLK
SDATAOUT
tSDOD
MB86391
Product Specification
Rev. 1.1
12, November 2001
54
FUJITSU LIMITED
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Item
Serial data input setup time
Serial data input hold time
Serial data output delay time
Symbol
tSDIS
tSDIH
tSDOD
MB86391
Product Specification
Rev. 1.1
Condition
Min.
100
100
−
Standard
Typical
−
−
−
Max.
−
−
160
12, November 2001
55
Unit
ns
ns
ns
FUJITSU LIMITED
Proprietary and Confidential
4.4.4 SDRAM Interface for Video Encoding
Clock (SDCLK)
1/fSDCLK
tHSDCLK
tLSDCLK
SDCLK
Item
SDCLK frequency
SDCLK H duration
SDCLK L duration
Symbol
Condition
fSDCLK
tHSDCLK
tLSDCLK
Min.
−
6.5
6.5
Standard
Typical
−
−
−
Max.
54
−
−
Unit
MHz
ns
ns
Input signals
SDCLK
SDDATA31:0
t RSDS
t RSDH
Output signals
SDCLK
SDDATA31:0,
SDADRS11:0,
SDDQM, XSDWE,
XSDCAS, XSDRAS,
XSDCS, SDCKE
tWSDD, t SADRSD, t SDDQM, tSDWED ,
tSDCASD , t SDRASD, t SDCSD , t SDCKED
MB86391
Product Specification
Rev. 1.1
12, November 2001
56
FUJITSU LIMITED
Proprietary and Confidential
Item
Address output delay time
Read data setup time
Read data hold time
Data output delay time
XSDDQM delay time
XSDWE delay time
XSDCAS delay time
XSDRAS delay time
XSDCS delay time
XSDCKE delay time
Symbol
tSADRSD
tRSDS
tRSDH
tWSDD
tSDDQM
tSDWED
tSDCASD
tSDRASD
tSDCSD
tSDCKED
MB86391
Product Specification
Rev. 1.1
Condition
Min.
3.5
5.5
0
3.5
3.5
3.5
3.5
3.5
3.5
3.5
Standard
Typical
−
−
−
−
−
−
−
−
−
−
Max.
13
−
−
13
13
13
13
13
13
13
12, November 2001
57
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FUJITSU LIMITED
Proprietary and Confidential
4.4.5 Video Input Interface
Clock (VCLK)
1/f VCLK
tHVCLK
t LVCLK
VCLK
Item
VCLK frequency
VCLK H duration
VCLK L duration
Symbol
Condition
fVCLK
tHVCLK
tLVCLK
Min.
27
11
11
Standard
Typical
−
−
−
Max.
36
−
−
Unit
MHz
ns
ns
Input signal
VCLK
XVSYNC,
XHSYNC, FIELD,
XVALID, DVIDEO
tVSYNCS , t HSYNCS,
tFLDS, t VLDS, tDVDS
Item
XVSYNC setup time
XVSYNC hold time
XHSYNC setup time
XHSYNC hold time
FIELD setup time
FIELD hold time
XVALID setup time
XVALID hold time
DVIDEO setup time
DVIDEO hold time
Symbol
tVSYNCS
tVSYNCH
tHSYNCS
tHSYNCH
tFLDS
tFLDH
tVLDS
tVLDH
tDVDS
tDVDH
MB86391
Product Specification
Rev. 1.1
tVSYNCH , tHSYNCH,
tFLDH, tVLDH, tDVDH
Condition
Min.
10
0
10
0
10
0
10
0
10
0
Standard
Typical
−
−
−
−
−
−
−
−
−
−
Max.
−
−
−
−
−
−
−
−
−
−
12, November 2001
58
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FUJITSU LIMITED
Proprietary and Confidential
4.4.6 Audio Input Interface
(a) In master mode
System clock input (ASCLK)
tASCLK
t HASCLK
tLASCLK
ASCLK
Item
Symbol
ASCLK frequency
ASCLK H duration
ASCLK L duration
Condition
tASCLK
tHASCLK
tLASCLK
Min.
−
30
30
Standard
Typical
1/256fs
−
−
Max.
−
−
−
Unit
ns
ns
ns
Note: fs: Audio sampling frequency
Audio bit clock output (ACLK)
ASCLK
t ACLKD
tACLKO
t HACLKO
t LACLKO
ACLK
Item
ACLK frequency
ACLK H duration
ACLK L duration
ACLK delay time
Symbol
tACLKO
tHACLKO
tLACLKO
tACLKD
Condition
Min.
−
135
135
3
Standard
Typical
1/64fs
−
−
−
Max.
−
−
−
15
Note: fs: Audio sampling frequency
MB86391
Product Specification
Rev. 1.1
12, November 2001
59
Unit
ns
ns
ns
ns
FUJITSU LIMITED
Proprietary and Confidential
Serial audio data input signals
ACLK
ADATA
t ADS
t ADH
Audio sampling clock output signals
ASCLK
ALRCK
tALRCKD
t ALRCKO
Item
ADATA setup time
ADATA hold time
ALRCK cycle time
ALRCK delay time
Symbol
tADS
tADH
tALRCKO
tALRCKD
MB86391
Product Specification
Rev. 1.1
Condition
Min.
50
50
20
3
Standard
Typical
Max.
15
12, November 2001
60
Unit
ns
ns
µs
ns
FUJITSU LIMITED
Proprietary and Confidential
(b) In slave mode
Audio bit clock input (ACLK)
t ACLKI
tHACLKI
tLACLKI
ACLK
Item
Symbol
ACLK cycle duration
ACLK H duration
ACLK L duration
Condition
Min.
−
135
135
tACLKI
tHSDCLK
tLSDCLK
Standard
Typical
1/64fs
−
−
Max.
−
−
−
Unit
ns
ns
ns
Note: fs: Audio sampling frequency
Serial audio data input signals
ACLK
ADATA
t ADS
t ADH
Audio sampling clock input signals
ACLK
ALRCK
t ALRCKH
t ALRCKS
tALRCKI
MB86391
Product Specification
Rev. 1.1
12, November 2001
61
FUJITSU LIMITED
Proprietary and Confidential
Item
ADATA setup time
ADATA hold time
ALRCK cycle time
ALRCK setup time
ALRCK hold time
Symbol
tADS
tADH
tALRCKI
tALRCKS
tALRCKH
MB86391
Product Specification
Rev. 1.1
Condition
Min.
50
50
20
50
50
Standard
Typical
Max.
Unit
ns
ns
µs
ns
ns
12, November 2001
62
FUJITSU LIMITED
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4.4.7 Bit Stream Output Port
(a) 27 MHz sync/handshake mode
Input singnals
BCLK
STREQ
t BSTRQS tBSTRQH
Output signals
BCLK
STEN, STDATA,
TSPSSYNC
t BSTED, tBSTDTD,
t BTPSYNCD
Item
STREQ setup time
STREQ hold time
STEN delay time
STDATA delay time
TSPSSYNC delay time
Symbol
tBSTRQS
tBSTRQH
tBSTED
tBSTDTD
tBTPSYNCD
MB86391
Product Specification
Rev. 1.1
Condition
Min.
8
0
5
5
5
Standard
Typical
Max.
15
15
15
12, November 2001
63
Unit
ns
ns
ns
ns
ns
FUJITSU LIMITED
Proprietary and Confidential
(b) Transfer clock sync mode
Clock (STCLK)
tSTCLK
t HSTCLK
t LSTCLK
STCLK
Item
STCLK cycle duration
STCLK H duration
STCLK L duration
Symbol
Condition
tSTCLK
tHSTCLK
tLSTCLK
Min.
150
60
60
Standard
Typical
Max.
Unit
ns
ns
ns
Input signals
STCLK
STREQ
t STRQS
t STRQH
Output signals
STCLK
STEN, STDATA,
TSPSSYNC
t STED, t STDTD,
t TPSYNCD
MB86391
Product Specification
Rev. 1.1
12, November 2001
64
FUJITSU LIMITED
Proprietary and Confidential
Item
STREQ setup time
STREQ hold time
STEN delay time
STDATA delay time
TSPSSYNC delay time
Symbol
tSTRQS
tSTRQH
tSTED
tSTDTD
tTPSYNCD
MB86391
Product Specification
Rev. 1.1
Condition
Min.
0
60
Standard
Typical
Max.
103
103
103
Unit
ns
ns
ns
ns
ns
12, November 2001
65