Ordering number : ENA2081A
LC786961W
CMOS LSI
Compact Disc Player IC
http://onsemi.com
Overview
The LC786961W integrates ARM7TDMI-S™, CD servo control, CD signal processing, compressed audio decode
processing, audio signal processing, USB host processing, SD memory card host processing and a flash memory to
store the program for ARM7TDMI-S™ and various data in a package. Furthermore, various kinds of interface
functions such as SIO, UART etc. reduce the external main controller’s processing load and make high performance
and much functional CD player system, using with less components.
Features
RF signal processing for CD-DA/R/RW, servo control, EFM signal processing, and anti-shock processing
MP3*, WMA*, AAC* decoder processing
Sampling rate convertor, High frequency compensation filter and other various audio signal processing
USB host function (Full speed as 12Mbps), SD memory card host function
ARM7TDMI-S™ as internal CPU core, flash memory for program and various data storage
Operating voltage: 3.3V typical
Operating temperature: 40C to +85C
Packages: SQFP144 (20 20)
ORDERING INFORMATION
See detailed ordering and shipping information on page 29 of this data sheet.
SQFP144(20X20)
is a registered trademark of ARM Limited.
* MP3(MPEG Layer-3 Audio Coding)
MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer Gesellschaft nor imply
any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required.
For details, please visit http://mp3licensing.com/.
* Windows Media Audio
Windows MediaTM is a trademark and a registered trademark in the United States and other countries of United States Microsoft Corporation.
* AAC
Advanced Audio Coding
* This product is licensed from Silicon Storage Technology Inc. (USA).
Semiconductor Components Industries, LLC, 2013
September, 2013 Ver. 1.0.0
72413HK/80112HKPC 20120531-S00006 No.A2081-1/29
LC786961W
Detail of Functions
CD DSP functions
<Playback functions>
Playback mode: CLV playback/Jitter free playback (VCEC)
Playback speed: Normal speed, double speed , Quadruple speed
<RF Processing block>
RF system:AGC, CD-R and CD-R/W playback support, peak hold, bottom hold
Error system: TE signal generation, FE signal generation
Detection: Track count signal, Jitter, Defect (black, mirror)
LASER power controller (APC)
DC offset voltage cancellation
<Servo control block>
All servo systems as tracking, focus, sled and spindle are implemented with digital processing.
Automatic adjustment functions: focus gain, focus bias, focus offset,
tracking gain, tracking offset and tracking balance
Shock detection / Interruption detection
<CD signal processing block>
EFM signal synchronization detection, protection and interpolation
Error detection, correction (C1=double, C2=quadruple/double)
Jitter margin ±19 frames
<CD TEXT processing block>
Buffers CD-TEXT data to the desired area of SDRAM
Starts buffering desired ID3/ID4 of CD-TEXT data.
<CD-DA Anti-shock processing block>
Anti-shock processing using with SDRAM
Maximum about 10 seconds with 16M bit SDRAM and about 40 seconds with 64M bit SDRAM
<CD-ROM processing block>
CD-ROM decoding (Mode1, Mode2 <form1, form2>)
Outputs CD-ROM decoded data
Compressed audio decode functions
MP3 decode (ISO/IEC 11172-3, ISO/IEC 13818-3)
Sampling rate support:
MPEG1-Layer1/2/3 (32kHz, 44.1kHz, 48kHz)
MPEG2-Layer1/2/3 (16kHz, 22.05kHz, 24kHz)
MPEG2.5-Layer3 ( 8kHz, 11.025kHz, 12kHz)
Bit rate support:
All Bit Rate (Variable Bit Rate support)
MPEG header read support
WMA decode (Version 9 standard)
Sampling rate support:
8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz, 48kHz
Bit rate support:
5kbps to 384kbps (Variable Bit Rate support)
AAC decode (ISO/IEC 14496-3, ISO/IEC 13818-7)
Profile:
MPEG4-AAC-LowComplexity
Sampling rate support:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz,
48kHz
Bit rate support:
Monaural 8kbps to 160kbps (Variable bit rate support)
Stereo
16kbps to 320kbps (Variable bit rate support)
Decodes both the compressed data read from the disc and input from outside through the interface pins
No.A2081-2/29
LC786961W
Audio processing functions
<Audio processing block>
Sampling rate converter (SRC) for compressed audio data playback
High frequency compensation filter for compressed audio data playback
Interpolation (CD-DA only)
Mute function (-12dB, -∞)
Digital attenuator
De-emphasis filter
Bilingual function
Bass / Treble filter
<Digital filter and D/A convertor processing block>
Eight-fold over-sampling digital filter (24bit)
One bit DAC (tertiary noise shaper type)
Secondary LPF for audio output
<Interface block>
Allows external audio data supply to the digital filter and D/A converter (Uses four signals)
Various external audio data output format
IIS (48fs/64fs), MSB first right justified (32fs/48fs/64fs), 16 bit data length
External interface functions
<USB host control block>
Open Host Controller Interface 1.0a
Universal Serial Bus Specification 1.1
Supports up to Full speed (12MHz)for USB2.0
Supports four kinds of transfer type (Control/Bulk/Interrupt/Isochronous)
<SD memory card host control block>
Multimedia Card Specification v2.11
Secure Digital Memory Card Physical Layer Specification v0.96
* Individual contract is necessary to use SD memory card controller. For detail, please contact to us.
Internal Microcontroller functions
<Sequencer control>
CD, USB, SD memory card playback control
Servo control, CD anti-shock playback control, CD-ROM/USB/SD file analysis, etc.
<Communication control between main controller>
Communication format: SIO
<Peripheral interface block>
GPIO port
30ports maximum (Shared with other functions. Several pins are 5V tolerant.)
External interrupt pins 4pins maximum (Shared with other functions.)
Serial interface
SIO
clock synchronized full duplex (3 lines) 2 channel
UART
full duplex
2 channel
IIC
master function
1 channel
<Program memory block>
Flash memory
Program version up from the external media (CD-ROM/USB)or main controller is available.
<Others>
Watch Dog Timer
Notify to outside from the pin or reset internally.
Power management
2 kinds of sleep mode
(1) Only CPU core operates at slow clock and clocks for other blocks are stopping.
(2) All clocks are stopping.
No.A2081-3/29
LC786961W
Others
<External memory>
External SDRAM
Memory size : 16Mbit or 64Mbit
Data width : 16bit
CAS latency : 2
Burst length : Full
Used for CD-DA anti-shock control, CD-ROM decoding, USB data temporary storage, etc.
<Internal power supply>
1.5V regulator for internal blocks
No.A2081-4/29
LC786961W
Specifications
Absolute Maximum Ratings at Ta = 25C, DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Maximum supply voltage
Symbol
Pin names
VDD max
DVDD, AVDD, LRVDD, XVDD1,
Input voltage 1
VIN1
XVDD2, UVDD, VVDD1, VVDD2,
VVDD3
Input pins other than VIN2
Input voltage 2
VIN2
RESB, SIFCK, SIFDI, SIFDO,
Conditions
Ratings
Unit
-0.3 to +3.95
V
-0.3 to DVDD+0.3
V
-0.3 to +5.6
V
-0.3 to DVDD+0.3
V
SIFCE, BUSYB, GP03, GP04,
GP05, GP06, GP07, GP10,
GP11, GP12, GP14, GP15,
GP16, GP26, GP27, JTRSTB,
JTCK, JTDI, JTMS
Output voltage
VOUT
Allowable power dissipation
Pd max
Ta 85C
540
Mounted reference PCB (*)
mW
Operating temperature
Topr
-40 to +85
C
Storage temperature
Tstg
-40 to +125
C
(*)Reference PCB: 114.3mm×76.1mm×1.6mm, glass epoxy resin
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85C, DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 =
VVSS2 = 0V
Parameter
Supply voltage
High-level input voltage
Symbol
VDD1
VIH(1)
Pin names
Conditions
DVDD, AVDD, LRVDD, XVDD1,
XVDD2, UVDD, VVDD1, VVDD2,
min
typ
max
Unit
3.00
3.60
V
Schmitt
2.00
5.50
V
Schmitt
2.00
VDD1
V
Schmitt
0
0.80
V
Schmitt
0
0.80
V
VVDD3
RESB, SIFCK, SIFDI, SIFDO,
SIFCE, BUSYB, GP03, GP04,
GP05, GP06, GP07, GP10,
GP11, GP12, GP14, GP15,
GP16, GP26, GP27, JTMS,
JTRSTB, JTCK, JTDI
VIH(2)
GP13, GP17, GP20, GP21,
GP22, GP23, GP24, GP25,
GP60, GP61, GP62, GP63,
GP64, GP65,
SDDAT00 to SDDAT15,
PMODE0, PMODE1
Low-level input voltage
VIL(1)
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP14, GP15, GP16, GP26,
GP27, JTMS, JTRSTB,
JTCK, JTDI
VIL(2)
GP13, GP17, GP20, GP21,
GP22, GP23, GP24, GP25,
GP60, GP61, GP62, GP63,
GP64, GP65,
SDDAT00 to SDDAT15,
MODE0, MODE1, MODE2
Crystal oscillator frequency
FX1
XIN
XOUT
FX2
Oscillator circuit
12.0
MHz
Oscillator circuit
16.9344
MHz
X16IN
X16OUT
No.A2081-5/29
LC786961W
Electrical Characteristics at Ta = -40 to +85C, VDD1 = 3.0V to 3.6V,
DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Current drain
Symbol
IDD1
Pin names
Conditions
min
DVDD, AVDD, LRVDD, XVDD1,
XVDD2, UVDD, VVDD1,
IIH(1)
max
125
VVDD2,
VVDD3
High-level input current
typ
Unit
150
mA
10.00
A
10.00
A
RESB, SIFCK, SIFDI, JTMS,
JTRSTB, JTCK, JTDI,
Schmitt,
PMODE0, PMODE1, SIFDO,
SIFCE, BUSYB, GP03, GP04,
VIN = 5.50V
Built-in
GP05, GP06, GP07, GP10,
Pull-down
GP11, GP12, GP14, GP15,
resistor OFF
GP16, GP26, GP27
IIH(2)
Low-level input current
IIL(1)
GP13, GP17, GP20, GP21,
Schmitt,
GP22, GP23, GP24, GP25,
GP60, GP61, GP62, GP63,
VIN = VDD1
Built-in
GP64, GP65,
Pull-down
SDDAT00 to SDDAT15
resistor OFF
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, GP16,
GP17, GP20, GP21, GP22,
Schmitt,
GP23, GP24, GP25, GP26,
VIN = 0V
-10.00
A
VDD1-0.6
V
VDD1-0.6
V
GP27, GP60, GP61, GP62,
GP63, GP64, GP65,
SDDAT00 to SDDAT15, JTMS,
JTRSTB, JTCK, JTDI,
MODE0, MODE1, MODE2
High-level output voltage
VOH(1)
GP04, GP05, GP06, GP07,
GP12, GP13, GP14, GP15,
GP16, GP17, GP20, GP21,
GP22, GP23, GP24, GP25,
GP26, GP27, GP60, GP61,
CMOS,
GP62, GP63, GP64, GP65,
IOH = -2mA
SDBA, SDDAT00 to SDDAT15,
SDADRS00 to SDADRS12,
SDCSB, SDRASB, SDCASB,
SDWEB, SDCKE, SDDQM
VOH(2)
SIFDI, SIFDO, SIFCE, BUSYB,
GP03, GP10, GP11,
SDCLK, JTDO, JTRTCK
Low-level output voltage
VOL(1)
CMOS,
IOH = -4mA
GP04, GP05, GP06, GP07,
GP12, GP13, GP14, GP15,
GP16, GP17, GP20, GP21,
GP22, GP23, GP24, GP25,
GP26, GP27, GP60, GP61,
CMOS,
GP62, GP63, GP64, GP65,
IOL = 2mA
0.40
V
0.40
V
10.00
A
10.00
A
SDBA, SDDAT00 to SDDAT15,
SDADRS00 to SDADRS12,
SDCSB, SDRASB, SDCASB,
SDWEB, SDCKE, SDDQM
VOL(2)
SIFDI, SIFDO, SIFCE, BUSYB,
GP03, GP10, GP11,
SDCLK, JTDO, JTRTCK
Output off-leakage current
CMOS,
IOL = 4mA
IOFF(1)
PDOUT0, PDOUT1, AFILT
Hi-Z Out
-10.00
IOFF(2)
SIFDO
Hi-Z Out
-10.00
Continued to the next page.
No.A2081-6/29
LC786961W
Continued from the previous page.
Parameter
Symbol
Built-in pull down resistor
Pin names
RPD
Conditions
min
typ
max
Unit
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, GP16,
GP17, GP20, GP21, GP22,
50
100
200
k
42.50
50.00
57.50
A
-57.50
-50.00
-42.50
A
GP23, GP24, GP25, GP26,
GP27, GP60, GP61, GP62,
GP63, GP64, GP65,
SDDAT00 to SDDAT15
Charge pump output current
IPDOH
PDOUT1, PDOUT0
PCKIST = 100k
Current value
IPDOL
PDOUT1, PDOUT0
IAFILH
AFILT
15.0
A
IAFILL
AFILT
15.0
A
setting: 1x
<Note>
Put a internal pull down resistor or external pull down resistor or external pull up resistor to the SIFDO pin if its
output condition is set to 3-State mode.
Package Dimensions
unit : mm (typ)
3214A
22.0
0.5
20.0
73
72
144
37
20.0
109
1
36
0.5
0.2
22.0
108
0.145
0.1
1.6max
(1.4)
(1.25)
SANYO : SQFP144 (20X20)
No.A2081-7/29
LC786961
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
EFMIN
RFOUT
LPF
PHLPF
AIN
CIN
BIN
DIN
SLCISET
RFMON
VREF
JITTC
EIN
FIN
TE
TEIN
LDD
LDS
AVSS
AVDD
YAD01
YAD02
FDO
TDO
SLDO
SPDO
VVDD1
PDOUT1
PDOUT0
PCNCNT
PCKIST
VVSS1
PMODE0
PMODE1
GP26
GP27
GP10
GP11
GP12
GP13
SDDAT15
SDDAT14
SDDAT13
SDDAT12
DVDD
DVSS
SDDAT11
SDDAT10
SDDAT09
SDDAT08
SDDQM
SDCLK
SDCKE
SDADRS11
SDADRS09
DVDD
DVSS
DVDD15
SDADRS08
SDADRS07
SDADRS06
SDADRS05
SDADRS04
SDADRS03
SDADRS02
SDADRS01
SDADRS00
SDADRS10
SDBA
SDADRS12
SDCSB
SDRASB
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
SLCO
LRVSS
RCHO
LRREF
LCHO
LRVDD
XVDD2
X16IN
X16OUT
XVSS2
GP65
GP64
GP63
GP62
GP61
GP60
GP17
GP16
GP15
GP14
DVDD15
DVSS
DVDD
GP25
GP24
GP23
GP22
GP21
GP20
JTRTCK
JTDO
JTMS
JTDI
JTCK
JTRSTB
MODE2
LC786961W
Pin Assignment
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VVDD3
AFILT
VVSS2
VVDD2
UVDD
UDP
UDM
XVSS1
XOUT
XIN
XVDD1
GP07
GP06
GP05
GP04
GP03
BUSYB
SIFCE
SIFDO
SIFDI
SIFCK
RESB
DVSS
DVDD
MODE1
MODE0
SDDAT00
SDDAT01
SDDAT02
SDDAT03
SDDAT04
SDDAT05
SDDAT06
SDDAT07
SDWEB
SDCASB
Top view
No.A2081-8/29
LC786961W
Pin Description
Pin
Pin name
No.
I/O
State when
Function
"Reset"
1
EFMIN
AI
Input
2
RFOUT
AO
Undefined
RF signal input
RF signal output
3
LPF
AO
Undefined
RF signal DC level detection low-pass filter capacitor connection
4
PHLPF
AO
Undefined
5
AIN
AI
Input
6
CIN
AI
Input
C signal input
7
BIN
AI
Input
B signal input
8
DIN
AI
Input
D signal input
SLCO output current setting resistor connection
Defect detection low-pass filter capacitor connection
A signal input
9
SLCISET
AI
Input
10
RFMON
AO
Undefined
11
VREF
AO
AVDD/2
12
JITTC
AO
Undefined
13
EIN
AI
Input
E signal input
14
FIN
AI
Input
F signal input
15
TE
AO
Undefined
IC internal analog signal monitor 1
VREF voltage output
Jitter detection capacitor connection
TE signal output
16
TEIN
AI
Input
17
LDD
AO
Undefined
Laser power control signal output
TE signal input used for TES signal generation
18
LDS
AI
Input
Laser power detection signal input
19
AVSS
-
-
Analog system ground. This pin must be connected to the 0V level.
20
AVDD
-
-
Analog system power supply
21
YADO1
AI/AO
Input
22
YADO2
AI/AO
Input
23
FDO
AO
AVDD/2
Focus control signal output
24
TDO
AO
AVDD/2
Tracking control signal output
25
SLDO
AO
AVDD/2
Sled control signal output
26
SPDO
AO
AVDD/2
Spindle control signal output
27
VVDD1
-
-
28
PDOUT1
AO
Undefined
EFMPLL charge pump output 1
29
PDOUT0
AO
Undefined
EFMPLL charge pump output 0
30
PCNCNT
AI
Input
EFMPLL charge pump control voltage input
31
PCKIST
AI
Input
EFMPLL charge pump current setting resistor connection pin
32
VVSS1
-
-
EFMPLL ground. This pin must be connected to the 0V level.
33
PMODE0
I
Input
Must be connected to the DVDD.
34
PMODE1
I
Input
Must be connected to the DVDD.
35
GP26
I/O
Input (L)
General purpose I/O port with pull down resistor
36
GP27
I/O
Input (L)
General purpose I/O port with pull down resistor
37
GP10
I/O
Input (L)
38
GP11
I/O
Input (L)
39
GP12
I/O
Input (L)
AD input 1/FE signal monitor output
AD input 2/IC internal analog signal monitor 2
EFMPLL power supply
General purpose I/O port with pull down resistor
UART1 data transmit
General purpose I/O port with pull down resistor
UART1 data receive
General purpose I/O port with pull down resistor
Clock control input 1
General purpose I/O port with pull down resistor
Clock control input 2
40
GP13
I/O
Input (L)
Watch Dog Timer state monitor output
SDRAM lower byte data mask control output
SDRAM-DQML (LDQM) pin should be connected for
64Mbit-SDRAM (Only when “byte access” is enabled.)
41
SDDAT15
I/O
Input (L)
SDRAM data input/output 15 (pull down resistor)
42
SDDAT14
I/O
Input (L)
SDRAM data input/output 14 (pull down resistor)
43
SDDAT13
I/O
Input (L)
SDRAM data input/output 13 (pull down resistor)
44
SDDAT12
I/O
Input (L)
45
DVDD
-
-
Digital system power supply
46
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
SDRAM data input/output 12 (pull down resistor)
Continued to the next page.
No.A2081-9/29
LC786961W
Continued from the previous page.
Pin
No.
Pin name
I/O
State when
Function
"Reset"
47
SDDAT11
I/O
Input (L)
SDRAM data input/output 11 (pull down resistor)
48
SDDAT10
I/O
Input (L)
SDRAM data input/output 10 (pull down resistor)
49
SDDAT09
I/O
Input (L)
SDRAM data input/output 9 (pull down resistor)
50
SDDAT08
I/O
Input (L)
SDRAM data input/output 8 (pull down resistor)
SDRAM data mask control output
51
SDDQM
O
Low
52
SDCLK
O
Low
53
SDCKE
O
Low
SDRAM-DQMH(UDQM) pin should be connected
both for 16M and 64Mbit-SDRAM.
SDRAM clock output
SDRAM clock enable output
SDRAM address output 11
54
SDADRS11
O
Low
No use (NC) for 16Mbit-SDRAM
55
SDADRS09
O
Low
56
DVDD
-
-
Digital system power supply
57
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
AO
High
Capacitor connection pin for internal regulator
SDRAM-ADRS11 pin connection for 64Mbit-SDRAM
SDRAM address output 9
58
DVDD15
59
SDADRS08
O
Low
SDRAM address output 8
60
SDADRS07
O
Low
SDRAM address output 7
61
SDADRS06
O
Low
SDRAM address output 6
62
SDADRS05
O
Low
SDRAM address output 5
63
SDADRS04
O
Low
SDRAM address output 4
64
SDADRS03
O
Low
SDRAM address output 3
65
SDADRS02
O
Low
SDRAM address output 2
66
SDADRS01
O
Low
SDRAM address output 1
67
SDADRS00
O
Low
SDRAM address output 0
68
SDADRS10
O
Low
SDRAM address output 10
SDRAM bank select address output
69
SDBA
O
Low
SDRAM-BANK pin connection for 16Mbit-SDRAM
SDRAM-BANK1 pin connection for 64Mbit-SDRAM
SDRAM address output 12
70
SDADRS12
O
Low
SDRAM-DQML (LDQM) pin connection for 16Mbit-SDRAM. SDRAM-BANK0 pin
71
SDCSB
O
Low
SDRAM Chip Select output
72
SDRASB
O
Low
SDRAM Row Address Strobe output
73
SDCASB
O
Low
SDRAM Column Address Strobe output
74
SDWEB
O
Low
SDRAM Write Enable output
75
SDDAT07
I/O
Input (L)
SDRAM data input/output 7 (pull down resistor)
76
SDDAT06
I/O
Input (L)
SDRAM data input/output 6 (pull down resistor)
77
SDDAT05
I/O
Input (L)
SDRAM data input/output 5 (pull down resistor)
78
SDDAT04
I/O
Input (L)
SDRAM data input/output 4 (pull down resistor)
79
SDDAT03
I/O
Input (L)
SDRAM data input/output 3 (pull down resistor)
80
SDDAT02
I/O
Input (L)
SDRAM data input/output 2 (pull down resistor)
81
SDDAT01
I/O
Input (L)
SDRAM data input/output 1 (pull down resistor)
82
SDDAT00
I/O
Input (L)
SDRAM data input/output 0 (pull down resistor)
83
MODE0
I
Input
84
MODE1
I
Input
85
DVDD
-
-
Digital system power supply
86
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
87
RESB
I
-
88
SIFCK
I
Input
connection for 64Mbit-SDRAM
89
SIFDI
I/O
Input
LSI mode set pin 0 This pin must be connected to the 0V level.
LSI mode set pin 1 This pin must be connected to the 0V level.
IC reset input ("L"-active)
This pin must be set low once after power is first applied.
Host-I/F
Data transmit clock input for serial communication 1
Host-I/F
Data input for serial communication 1
Continued to the next page.
No.A2081-10/29
LC786961W
Continued from the previous page.
Pin
Pin name
No.
90
91
92
SIFDO
SIFCE
BUSYB
I/O
I/O
I/O
I/O
State when
Function
"Reset"
Input
Input
Input (L)
Host-I/F
Data output for serial communication 1 (CMOS or 3-State output)
Host -I/F
Enable signal input for serial communication 1 ("H"-active)
Host -I/F
System busy signal output ("L"-active)
General purpose I/O port with pull down resistor
93
GP03
I/O
Input (L)
94
GP04
I/O
Input (L)
95
GP05
I/O
Input (L)
96
GP06
I/O
Input (L)
General purpose I/O port with pull down resistor
97
GP07
I/O
Input (L)
General purpose I/O port with pull down resistor
98
XVDD1
-
-
USB device detection flag output
General purpose I/O port with pull down resistor
IIC (master) clock output
General purpose I/O port with pull down resistor
IIC (master) data input/output
Oscillator power supply
99
XIN
I
Oscillation
100
XOUT
O
Oscillation
101
XVSS1
-
-
Oscillator ground. This pin must be connected to the 0V level.
102
UDM
I/O
-
USB data input/output D- signal connection
103
UDP
I/O
-
USB data input/output D+ signal connection
104
UVDD
-
-
USB power supply
105
VVDD2
-
-
System PLL power supply
106
VVSS2
-
-
System PLL ground. This pin must be connected to the 0V level.
107
AFILT
AO
Undefined
108
VVDD3
-
-
109
MODE2
I
Input
110
JTRSTB
I
Input
111
JTCK
I
Input
112
JTDI
I
Input
113
JTMS
I
Input
114
JTDO
O
Low
115
JTRTCK
O
Low
12MHz oscillator connection
12MHz oscillator connection
Audio PLL charge pump output
Audio PLL power supply
LSI mode set pin 2 This pin must be connected to the 0V level.
JTAG reset input
(Connect to pll-down resister or 0V level in normal mode.)
JTAG clock input
(Connect to pll-down resister or 0V level in normal mode.)
JTAG data input
(Connect to pll-down resister or 0V level in normal mode.)
JTAG mode input
(Connect to pll-up resister or DVDD level in normal mode.)
JTAG data output (Leave open in normal mode.)
JTAG return clock output (Leave open in normal mode.)
General purpose I/O port with pull down resistor
116
GP20
I/O
Input (L)
117
GP21
I/O
Input (L)
118
GP22
I/O
Input (L)
119
GP23
I/O
Input (L)
120
GP24
I/O
Input (L)
121
GP25
I/O
Input (L)
122
DVDD
-
-
Digital system power supply
123
DVSS
-
-
Digital system ground. This pin must be connected to the 0V level.
124
DVDD15
AO
High
125
GP14
I/O
Input (L)
General purpose I/O port with pull down resistor
126
GP15
I/O
Input (L)
General purpose I/O port with pull down resistor
127
GP16
I/O
Input (L)
General purpose I/O port with pull down resistor
128
GP17
I/O
Input (L)
General purpose I/O port with pull down resistor
129
GP60
I/O
Input (L)
General purpose I/O port with pull down resistor
130
GP61
I/O
Input (L)
General purpose I/O port with pull down resistor
Data 1 input/output for SD memory card
General purpose I/O port with pull down resistor
Data 0 input/output for SD memory card
General purpose I/O port with pull down resistor
Clock output for SD memory card
General purpose I/O port with pull down resistor
Command input/output for SD memory card
General purpose I/O port with pull down resistor
Data 3 input/output for SD memory card
General purpose I/O port with pull down resistor
Data 2 input/output for SD memory card
Capacitor connection pin for internal regulator
Continued to the next page.
No.A2081-11/29
LC786961W
Continued from the previous page.
Pin
No.
Pin name
I/O
State when
Function
"Reset"
131
GP62
I/O
Input (L)
General purpose I/O port with pull down resistor
132
GP63
I/O
Input (L)
General purpose I/O port with pull down resistor
133
GP64
I/O
Input (L)
General purpose I/O port with pull down resistor
134
GP65
I/O
Input (L)
General purpose I/O port with pull down resistor
135
XVSS2
-
-
136
X16OUT
O
Oscillation
16.9344MHz oscillator connection
137
X16IN
I
Oscillation
16.9344MHz oscillator connection
138
XVDD2
-
-
Oscillator ground. This pin must be connected to the 0V level.
Oscillator power supply
139
LRVDD
-
-
140
LCHO
AO
LRVDD/2
Audio Lch data output
Audio LPF power supply
141
LRREF
AO
LRVDD/2
Reference voltage for audio LPF
142
RCHO
AO
LRVDD/2
Audio Rch data output
143
LRVSS
-
-
144
SLCO
AO
Undefined
Audio LPF ground. This pin must be connected to the 0V level.
Slice Level Control output
<Note>
(1) For unused pins:
The unused input pins must be connected to the GND (0V) level if there is no individual note in the above table.
The unused output pins must be left open (No connection) if there is no individual note in the above table.
The unused input/output pins must be connected to the GND (0V) or power supply pin for I/O block with internal
pull down resistor OFF or be left open with internal pull down resistor ON when input pin mode or must be left
open (No connection) when output pin mode if there is no individual note in the above table.
When you connect an I/O pin which is an input pin without internal pull-down resistor at reset mode to the GND
or power supply level, we recommend you to use pull-down resistor or pull-up resistor individually as fail-safe.
(2) For power supply pins:
Same voltage level must be supplied to DVDD, AVDD, XVDD1, XVDD2, VVDD1, VVDD2, VVDD3, UVDD
and LRVDD power supply pins.
(Refer to“Allowable operating ranges”.)
(3) For “Reset” condition:
This LSI is not reset only by making the RESB pin “Low”.
Refer to “Power on and Reset control” for detail of “Reset” condition.
No.A2081-12/29
LC786961W
Block Diagram
External
SDRAM
CDROM
Decoder
CD
Servo
Controller
CD
RF Signal
Processor
AD/DA
DATA Trans
Controller
CDTEXT
Decoder
CD
EFM/ECC
Decoder
CD PLL
CDDA
Anti Shock
ARM7 Core
Cache
Flash
memory
USB
Host
Controller
BUFRAM
I/F
Boot
ROM
MP3/WMA/AAC
Decoder
Audio
Data-I/F
Audio Control
DeEMPHASIS/
MUTE/ATT
External-IN/OUT
Work
RAM
8Fs Digital Filter
1bit DAC
WatchDog
Timer
USB-I/F
Analog LPF
Interrupt
SD
Memory Card
Controller
SRC
&
HFC-Filter
UART
Host-I/F
(SIO/IIC)
APLL
X’tal-2
(16.9344MHz)
SYSPLL
X’tal-1
(12MHz)
IIC
SIO
GPIO
1.5V
Regulator
3.3V
No.A2081-13/29
LC786961W
Power on and Reset control
Attention when power on
The RESB pin must be set to “Low” level to initialize the operating state of internal flash memory.
If the power is on during the RESB pin is “High” level, this LSI may operate incorrectly because the internal flash
memory is not initialized. In this case, this LSI is not initialized even if a low level supplied to RESB pin.
Therefore, the RESB pin must be set to “Low” level when power is first supplied.
You may input the voltage of 3.6V or less to each input pin when the power supply is off. However, it is necessary
to supply a regulated voltage to the power supply pin beforehand when more than 3.6V voltage is input to the 5V
tolerant input pins.
Power ON/Power Down/Reset timing
3.3V Power
VDD1
vBOT
0V
tPWD
3.3V Power
VDD1
tRESW1
tRESW2
RESB
During normal operation
(Oscillation clock is valid)
Power on stage
Parameter
Symbol
min
typ
max
unit
Power down time
tPWD
10
Power down voltage
vBOT
0
ms
Reset time (Power on)
tRESW1
20
ms
Reset time (Normal) (*1)
tRESW2
1
ms
0.2
V
*1: The specification of tRESW2 above is the time defined while steady the X16 clock and having oscillated.
When the X16 clock has been stopped by the command etc. , the specification of tRESW2 could be larger than the
value shown above, because it takes time that the X16 oscillator becomes stable.
No.A2081-14/29
LC786961W
Host interface
The data transmission between this LSI and Host controller is performed with SPI type synchronous SIO protocol.
The transmission procedure is as follows.
Refer to the internal software specification of this LSI about M5 to M0 code in Mode code transmission.
When the input data of M5 to M0 coincide to the data in the internal register, the SIFDO pin becomes to “Low”
level (Ack) then the transmission is enabled.
When not coincide, the SIFDO pin keeps “High” level (Nack) then the transmission is not enabled.
The seventh data in Mode code transmission shows whether the following procedure is the Command transmission
or the Data reception. When the seventh data is “Low”, the following procedure is Command transmission. When
the seventh data is “High”, the following procedure is Data reception.
Attention because the specifications of transmission timings are different depending on the internal CPU’s operating
speed modes (Low speed or Normal speed). Refer to the table in next page.
Communication Interface format between Host controller
SIFCE
SIFCK
SIFDI
MODE
(Send)
SIFDO
Command
1
Command
2
MODE
(Receive)
Command
N
Ack
Data
1
Ack
Data
2
Data
N
BUSYB
Transmission/Reception format between Host controller
(1) Host: Command Transmission
SIFCE
1
2
3
4
5
6
7
M5
M4
M3
M2
M1
M0
WR
8
1
2
3
6
7
8
D2
D1
D0
SIFCK
SIFDI
D7
Mode Code
byte
D6 D5
1st-data
byte
Last-data
byte
Nack
Ack
SIFDO
BUSYB
(2) Host: Data Reception
SIFCE
1
2
3
4
5
6
7
M5
M4
M3
M2
M1
M0
RD
8
1
2
3
6
7
8
D2
D1
D0
SIFCK
SIFDI
Mode Code
byte
SIFDO
Nack
Ack D7
D6 D5
1st-data
byte
Last-data
byte
BUSYB
No.A2081-15/29
LC786961W
Communication Timing specification between Host controller
SIFCE
(Input)
1/fCLK
tCSU
tCKH
tCKL
tCHD
SIFCK
(Input)
tCE
tCWSU tCWHD
SIFDI
(Input)
tCRAS
tCDOF
SIFDO
(Output)
BUSYB
(Output)
tCDON
tCDOH
tCBST
Parameter
Symbol
Pin names
SIFCK clock frequency
fCLK
SIFCK
SIFCK clock "H" level width
tCKH
SIFCK
SIFCK clock "L" level width
tCKL
SIFCK
Transfer start enable time
tCE
BUSYB, SIFCE
Setup time for transfer start
tCSU
SIFCE, SIFCK
Hold time for transfer end
tCHD
SIFCE, SIFCK
Setup time for SIFDI
tCWSU
SIFDI, SIFCK
Hold time for SIFDI
tCWHD
SIFDI, SIFCK
Output delay time for SIFDO “H”
tCDOH
SIFDO, SIFCK
Output delay time for SIFDO
tCRAS
SIFDO, SIFCK
Turn on time for SIFDO *1
tCDON
SIFDO, SIFCE
Turn off time for SIFDO *1
tCDOF
SIFDO, SIFCE
BUSYB "L" level output delay time
tCBST
BUSYB
min
typ
max
unit
3.3
0.725
150
MHz
ns
690
150
ns
690
0
ns
0
100
ns
200
100
ns
200
75
ns
75
75
ns
200
100
350
100
350
100
100
150
150
150
350
ns
ns
ns
ns
ns
Internal CPU operating speed mode
Upper step : Normal speed
Lower step : Low speed
*1: The tCDON and tCDOF specifications are for when the SIFDO pin is set to the 3-State mode.
No.A2081-16/29
LC786961W
USB Specification at Ta = -40C to +85C, VDD1 = 3.0V to 3.6V,
DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Symbol
High-level input voltage
VIH (USB)
Low-level input voltage
VIL (USB)
Pin names
Conditions
min
typ
max
unit
2.0
0.8
ILI
Output driver: OFF
Differential input sensitivity
VDI
|(UDP) - (UDM)|
0.2
0.8
2.5
V
2.8
3.6
V
0
0.3
V
1.3
2.0
V
4.0
20.0
4.0
20.0
VCM
Includes VDI range
High-level output voltage
VOH (USB)
Connect 15k ±5% pull-down
UDM, UDP
resistor to GND (0V).
Low-level output voltage
VOL (USB)
Connect 1.5k ±5% pull-up
resistor to VDD1.
Crossover voltage
VCR
USB data rising time
TUR
USB data falling time
TUF
CL = 50pF
10.0
A
Input leakage current
Common mode voltage range
-10.0
V
V
ns
Example circuit for USB application
LC786961
VDD1
UVDD
UDP
15
5pF
UDM
15k
* The value of resistors and capacitors in this
circuit might be needed to be adjusted for each
application.
15
5pF
15k
No.A2081-17/29
LC786961W
SD Memory Card Interface
SD Memory Card Input/Output Timing specification
tSDCKL tSDCKH
1/fSDCKF
SDCCLK
(Output)
SDCMDIO
(Inout)
tSDCMS
tSDCMH
tSDCMO
tSDCDH
tSDCDO
SDCDAT[3:0]
(Inout)
tSDCDS
* Relationship between signal name and pin name
SDCCLK
: GP22
SDCMDIO
: GP23
SDCDAT [2] : GP25
SDCDAT [1] : GP20
Parameter
Symbol
SDCDAT [3] : GP24
SDCDAT [0] : GP21
Pin names
min
typ
max
unit
SDCCLK clock frequency
fSDCKF
SDCCLK
6.0
SDCCLK clock "H" level width
tSDCKH
SDCCLK
83.3
MHz
ns
SDCCLK clock "L" level width
tSDCKL
SDCCLK
83.3
ns
Setup time for command input
tSDCMS
SDCMDIO, SDCCLK
30.0
ns
Hold time for command input
tSDCMH
SDCMDIO, SDCCLK
30.0
ns
Command output valid time
tSDCMO
SDCMDIO, SDCCLK
Setup time for data input
tSDCDS
SDCDAT [3:0], SDCCLK
30.0
ns
Hold time for data input
tSDCDH
SDCDAT [3:0], SDCCLK
30.0
ns
Data output valid time
tSDCDO
SDCDAT [3:0], SDCCLK
30.0
30.0
ns
ns
Note: Internal CPU (ARM7) must be set to normal mode. Never use the SD Memory Card interface at the internal
CPU’s Low speed mode.
No.A2081-18/29
LC786961W
Internal Voltage Regulator at Ta = -40C to +85C,
DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Symbol
Condition
Output voltage
DVDD15
VDD1 = 3.0V to 3.6V
Load current
Iope
VDD1 = 3.3V
min
typ
1.35
max
1.50
unit
1.65
V
200
mA
Note : The spec. of “load current” above is sum of the load current of two internal voltage regulator.
Example circuit for Regulator
* Same circuit need to be mounted both for two regulator pins.
(No.58 and No.124)
* The capacitor C1 must be greater than 50F and low Secure
50F or more for low ESR and the capacity value in the range
of the operating temperature so that there is a possibility of the
oscillation when the capacity value changes by the temperature
change etc.
(The recommended value is 100F.)
LC786961
DVDD
DVSS
DVDD15
100F
C1
A/D, D/A converter Characteristics for servo
at Ta = -40C to +85C, VDD1 = 3.3V, DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Symbol
Resolution
Res
Maximum input/output range
Minimum input/output range
Condition
min
typ
max
unit
8
bit
Vaio1
4/5 VDD1
V
Vaio2
1/5 VDD1
V
1-Bit D/A converter Characteristics
at Ta = 25C, VDD1 = 3.3V, DVSS = AVSS = LRVSS = XVSS1 = XVSS2 = VVSS1 = VVSS2 = 0V
Parameter
Symbol
Output level
LEVEL
Pin names
Conditions
LCHO,
min
typ
With a 1kHz, 0dB data signal
0.63
RCHO
Total harmonics distortion
THD+N
max
LCHO,
With a 1kHz, 0dB data signal,
RCHO
Using the 20kHz Low-pass filter (built-in
0.008
unit
Vrms
0.012
%
AD725D)
Dynamic range
DR
LCHO,
With a 1kHz, -60dB data signal,
RCHO
Using the 20kHz Low-pass filter and A-filter
92
96
dB
95
98
dB
82
85
dB
(built-in AD725D)
Signal to noise ratio
S/N
LCHO,
With a 1kHz, 0dB data signal,
RCHO
Using the 20kHz Low-pass filter and A-filter
(built-in AD725D)
Cross talk
CT
LCHO,
With a 1kHz, 0dB data signal,
RCHO
Using the 20kHz Low-pass filter
(built-in AD725D)
Note : Measured in normal speed playback mode in Ours 1-bit D/A converter block reference circuit.
1-Bit D/A converter output reference circuit
LC786961
LRVDD
Analog output
Left channel
680
LCHO
LRREF
LPF
10F
100F
1000pF
100k
Shibasoku Co., Ltd.
AD725D
RCHO
LRVSS
RCHO :Same circuit as for LCHO
No.A2081-19/29
LC786961W
Oscillator
Example circuit for Oscillator
LC786961
XVDD2
X16IN
X16OUT
Rd2
XVSS2
C2
XVDD1
XIN
XOUT
C2
XVSS1
Rd1
C1
C1
(1) XIN/XOUT: 12.0000MHz
For System Main clock, USB control
Recommended Oscillator
Nihon Dempa Kogyo Co., Ltd.
Type
Recommended value
NX5032GA
Rd1 = 0, C1 = 4pF
NX8045GB
Rd1 = 0, C1 = 4pF
(2) X16IN/X16OUT: 16.9344MHz
For CD control, Audio control
Recommended Oscillator
Murata Manufacturing Co., Ltd.
Type
Recommended value
CSTCE16M9V53-R0
Rd2 = 0, C2 = open
CSTCW16M9X51008-R0
Rd2 = 0, C2 = open
CSTLS16M9X53-B0
Rd2 = 0, C2 = open
Nihon Dempa Kogyo Co., Ltd.
Type
Recommended value
AT51-CD2
Rd2 = 0, C2 = 8pF
Notes
Because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the
individual original circuit board to the oscillator maker.
The accuracy of 12MHz oscillator (XIN/XOUT) must be in ±500ppm when this oscillator clock is used for USB
Host function.
Concerning about internal circuit for XIN/XOUT and X16IN/X16OUT, refer to the “Analog Pin Internal Equivalent
Circuits” section.
No.A2081-20/29
LC786961W
SDRAM Interface
(1) Required specification for external SDRAM
Memory size :16Mbit or 64Mbit
Data width
:16bit
CAS latency :2
Burst length :Full
(2) Interface pins to external SDRAM
Pin Name
Function at 16Mbit-SDRAM
SDDAT15 to SDDAT00
Data input/output (16bit)
Data input/output (16bit)
SDADRS10 to SDADRS00
Address output (11bit)
Address output (11bit)
SDADRS11
SDADRS12
SDBA
SDDQM
Not used
DQML (LDQM) output
Lower byte data mask control
Signal name in
Function at 64Mbit-SDRAM
Address (A11) output
Address (A12) or bank0 output
Cf. P24, P25
DDAT[15:0]
DDAT[15:0]
DADD[10:0]
DADD[10:0]
DADD[11]
SDDQML
DADD[12]
DADD[11]
Bank output
Bank or bank1 output
DQMH (UDQM) output
DQMH (UDQM) output
Upper byte data mask control
Upper byte data mask control
SDDQMU
DQML (LDQM) output
-
Lower byte data mask control
SDDQML
GP13
Not used
SDCSB
CSB output
CSB output
SDRASB
RASB output
RASB output
SDCASB
CASB output
CASB output
SDWEB
WEB output
WEB output
SDCKE
Clock enable output
Clock enable output
SDCLK
Clock output
Clock output
DADD[13]
SDDQMU
SDCSB
SDCSB
SDRASB
SDRASB
SDCASB
SDCASB
SDWEB
SDWEB
SDCKE
SDCKE
SDCLK
SDCLK
Notes
SDADRS11 and GP13 in 16Mbit-SDRAM using mode should be treated as described below.
SDADRS11 : Open (No connect)
GP13
: Use as other function or Open
SDDAT00 to SDDAT15 pins can have internal pull down resistor optionally. Those pull down resistors are set
to ON mode in initialization.
When setting the SDRAM using mode, those pull down resistors will be set to OFF mode.
Some signals named in P22 to P23 use different pins according to the using SDRAM. The signal name in P22 to
P23 for the actual pin is shown at the most right column in above table.
Upper step : Signal name in 16Mbit-SDRAM using mode
Lower step : Signal name in 64Mbit-SDRAM using mode
No.A2081-21/29
LC786961W
(3) SDRAM Access Timing
SDRAM Read Timing
TS2
TS3
TS5
TS6
SDCSB
1/FS1
TS7
SDCLK
TS4
SDCKE
TS5
TS6
TS7
SDRASB
TS5
TS6
TS7
SDCASB
SDWEB
TS8 TS9
DADD[13:0]
Row
ALL-PRE
Column
Row
Column
SDDQMU
SDDQML
TS10
TS11
DDAT[15:0]
Read-Data
CAS-Latency 2
SDRAM Write Timing
TS2
TS3
TS5
TS6
SDCSB
1/FS1
TS7
SDCLK
SDCKE
TS5
TS6
TS7
SDRASB
TS5
TS6
TS7
SDCASB
SDWEB
DADD[13:0]
TS8 TS9
Column ALL-PRE
Row
Row
Column ALL-PRE
TS5
SDDQMU
TS6
TS7
TS12
TS13
SDDQML
DDAT[15:0]
Write-Data
Data Latch Timing (SDRAM)
Write-Data
No.A2081-22/29
LC786961W
SDRAM Refresh Timing (Auto Refresh)
TS14
TS5
TS6
SDCSB
1/FS1
TS15
TS7
SDCLK
SDCKE
TS5
TS6
TS7
SDRASB
SDCASB
SDWEB
DADD[13:0]
SDDQMU
SDDQML
DDAT[15:0]
Symbol
FS1
Parameter
min
typ
SDRAM clock (SDCLK) frequency
max
16.9344
unit
MHz
TS2
Row (SDRASB) cycle time
(1/FS1)×5
ns
TS3
Row (SDRASB) active time
(1/FS1)×3
ns
TS4
RASB-CASB delay time (SDRASB-SDCASB)
(1/FS1)×2
ns
TS5
Command "L" level width
40
ns
10
ns
10
ns
(SDCSB, SDCKE, SDRASB, SDCASB, SDWEB)
TS6
Command setup time
(SDCSB, SDCKE, SDRASB, SDCASB, SDWEB, SDDQMU, SDDQML)
TS7
Command hold time
(SDCSB, SDCKE, SDRASB, SDCASB, SDWEB, SDDQMU, SDDQML)
TS8
Address (DADD) setup time
10
ns
TS9
Address (DADD) hold time
10
ns
TS10
SDRAM read data setup time (Data read from SDRAM)
20
ns
TS11
SDRAM read data hold time (Data read from SDRAM)
TS12
SDRAM write data hold time before rising edge of SDCLK
0
ns
10
ns
10
ns
(Data write to SDRAM)
TS13
SDRAM write data hold time after rising edge of SDCLK
(Data write to SDRAM)
TS14
Row (SDRASB) pre-charge time
(1/FS1)×3
ns
TS15
Row (SDRASB) active time after refresh
(1/FS1)×5
ns
Notes
Setup time and Hold time specifications in above table are measured from the rising edge of SDCLK signal.
All the specifications in above table are applied to Read mode, Write mode and Refresh mode.
No.A2081-23/29
LC786961W
Analog Pin Internal Equivalent Circuits
Pin Name (Pin No.)
Equivalent circuit
AVDD
EFMIN (1)
AVSS
AVDD
AVDD
AVSS
AVSS
AVDD
AVDD
AVSS
AVSS
RFOUT (2)
LPF (3)
AVDD
PHLPF (4)
AVSS
AVDD
AIN (5)
CIN (6)
BIN (7)
DIN (8)
AVSS
AVDD
SLCISET (9)
AVSS
AVDD
AVDD
RFMON (10)
AVSS
AVSS
Continued to the next page.
No.A2081-24/29
LC786961W
Continued from the previous page.
Pin Name (Pin No.)
Equivalent circuit
AVDD
AVDD
AVSS
AVSS
VREF (11)
AVDD
JITTC (12)
AVSS
AVDD
EIN (13)
FIN (14)
AVSS
AVDD
AVDD
AVSS
AVSS
TE (15)
AVDD
TEIN (16)
AVSS
AVDD
AVDD
AVDD
LDD (17)
AVSS
AVSS
AVDD
LDS (18)
AVSS
Continued to the next page.
No.A2081-25/29
LC786961W
Continued from the previous page.
Pin Name (Pin No.)
Equivalent circuit
AVDD
YADO1 (21)
YADO2 (22)
AVSS
AVDD
AVDD
AVSS
AVSS
VVDD1
VVDD1
VVSS1
VVSS1
VVDD1
VVDD1
VVSS1
VVSS1
FDO (23)
TDO (24)
SLDO (25)
SPDO (26)
PDOUT1 (28)
PDOUT0 (29)
VVDD1
VVDD1
PCNCNT (30)
VVSS1
VVDD1
PCKIST (31)
VVSS1
XVDD1
XIN (99)
VVSS1
XVDD1
XIN
XOUT
XOUT (100)
XVSS1
XVSS1
Continued to the next page.
No.A2081-26/29
LC786961W
Continued from the previous page.
Pin Name (Pin No.)
Equivalent circuit
VVDD3
VVDD3
AFILT (107)
VVSS3
XVDD2
X16OUT (136)
VVSS3
XVDD2
XIN
XOUT
X16IN (137)
XVSS2
XVSS2
LRVDD
LRVDD
LRVSS
LRVSS
LRVDD
LRVDD
LRVSS
LRVSS
AVDD
AVDD
AVSS
AVSS
LHCO (140)
RCHO (142)
LRREF (141)
SLCO (144)
No.A2081-27/29
LC786961W
Sample Application Circuit
SLCO
VDD1
To PICKUP
A
B
C
D
Vref
(Reference
voltage)
E
F
LDD
LDS
AVSS
AVDD
YADO1
YADO2
FDO
TDO
SLDO
SPDO
To Driver
LD
MD
VVDD3
AFILT
VVSS2
VVDD2
UVDD
UDP
UDM
From/To
USB-Device
D+
D-
LC786961
EFMIN
RFOUT
LPF
PHLPF
AIN
CIN
BIN
DIN
SLCISET
RFMON
VREF
JITTC
EIN
FIN
TE
TEIN
VVDD1
PDOUT1
PDOUT0
PCNCNT
PCKIST
VVSS1
GND
* This sample circuit is only for CD servo block, each PLL block and USB block.
The value of each component needs to be adjusted under the target conditions.
The circuit for CD servo shown above could be changed depending on the CD mechanism used.
Concerning to the application circuit for Regulator, Audio DAC and Oscillator, refer to the page 19 and 20
respectively.
No.A2081-28/29
LC786961W
ORDERING INFORMATION
Device
LC786961W-H
Package
SQFP144(20X20)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
200 / Tray Foam
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PS No.A2081-29/29