FUJITSU MB88141APFV

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-13213-1E
Linear IC Converter
CMOS
D/A Converter for Digital Tuning
(Compatible with I2C Bus)
MB88141A
■ DESCRIPTION
The FUJITSU MB88141A is an 8-bit D/A converter with 12 built−in channels.
The 12 analog output channels have built-in OP Amps, providing large current drive capability.
Data input is compatible with I2C specifications, and is controlled by two control lines.
The built-in I/O expander function allows the MB88141A to be controlled by devices incompatible with I2C bus
specifications (provides conversion between I2C serial and 8- or 4-bit parallel I/O).
The MB88141A is ideal for replacing electronic knob or pre-set variable resistance tuning devices.
■ FEATURES
•
•
•
•
•
Ultra-low power consumption (0.9 mW/channel Typ.)
Ultra-compact package
Built-in 12-channel R-2R type 8-bit D/A converter
Built-in analog output amplifier (maximum sink current 1.0 mA, maximum source current 1.0 mA)
Analog output range 0 V to VCC
(Continued)
■ PACKAGES
24-pin plastic DIP
24-pin plastic SOP
24-pin plastic SSOP
(DIP-24P-M02)
(FPT-24P-M01)
(FPT-24P-M03)
“Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.”
MB88141A
(Continued)
• 5 V single power supply
• Power supply/GND for MCU interface and OP Amp is separate from power supply/GND for D/A converter
• Power supply for D/A converter is divided into two systems for VDDI/VSSI (AO1 to AO4) and VDD2/VSS2 (AO5 to
AO12) , allowing separate level settings for each system
• Compatible with serial data input, I2C specifications
• Built-in I/O expander function (converts between I2C serial and 8-or 4-bit parallel)
• CMOS process
• Packages : DIP 24-pin, SOP 24-pin, SSOP 24-pin
2
MB88141A
■ PIN ASSIGNMENT
(Top View)
AO1
1
24
GND
AO2
2
23
VSS1
AO3
3
22
VDD1
AO4
4
21
SDA
AO5/D7
5
20
SCL
AO6/D6
6
19
MOD
AO7/D5
7
18
CS2
AO8/D4
8
17
CS1
AO9/D3
9
16
CS0
AO10/D2
10
15
VDD2
AO11/D1
11
14
VSS2
AO12/D0
12
13
VCC
(DIP-24P-M02)
(FPT-24P-M01)
(FPT-24P-M03)
3
MB88141A
■ PIN DESCRIPTION
Pin no.
Symbol
Circuit Type
I/O
21
SDA
C
I/O
I2C bus data input/output pin (hysteresis input).
Outputs the acknowledge signal.
20
SCL
B
I
I2C bus shift clock input pin (hysteresis input) .
I
D/A converter and I/O expander mode switching pin. *1, *2
Input “L” to operate as a D/A converter, “H” to operate as I/O
expander and D/A converter.
A
Description
19
MOD
16
17
18
CS0
CS1
CS2
A
I
These pins set the lower 3 bits of the slave address. *1
This allows up to eight MB88141A chips to be used on the same
bus line.
1
2
3
4
AO1
AO2
AO3
AO4
D
O
8-bit D/A outputs with OP Amp. *2
5
6
7
8
9
10
11
12
AO5/D7
AO6/D6
AO7/D5
AO8/D4
AO9/D3
AO10/D2
AO11/D1
AO12/D0
E
I/O
8-bit D/A outputs with OP Amp. *2
In I/O expander operation, these pins function as parallel data input/output pins.
13
VCC
Power supply

Power supply pin for digital circuits and OP Amp.
24
GND
GND

GND pin for digital circuits and OP Amp.
22
VDD1
Power supply

Reference power supply pin for D/A converter (H) . AO1 to AO4.
23
VSS1
Power supply

Reference power supply pin for D/A converter (L) . AO1 to AO4.
15
VDD2
Power supply

Reference power supply pin for D/A converter (H) . AO5 to AO12.
14
VSS2
Power supply

Reference power supply pin for D/A converter (L) . AO5 to AO12.
*1: The MOD and CS0-CS2 pins should be used with fixed level input.
*2: When using the I/O expander function together with the D/A converter function, take care that D/A converter
output precision is within a range that will not affect overall system operation.
4
MB88141A
■ BLOCK DIAGRAM
SDA
SCL
CS2
CS1
CS0
MOD
I2C Bus Interface
D/A & I/O Control Logic
D0
1 ch
VDD1
VSS1
D7
8-bit latch
R-2R
ladder circuit
−
+
D0
4 ch
D7
8-bit latch
R-2R
ladder circuit
−
+
D0
5 ch
D7
8-bit latch
R-2R
ladder circuit
−
+
D0
12 ch
D7
8-bit latch
VDD2
VSS2
R-2R
ladder circuit
−
+
8
VCC
GND
AO1
AO4
D7/AO5
D0/AO12
5
MB88141A
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Pch Tr
A
Input dedicated pin
Nch Tr
Digital input
Pch Tr
B
Nch Tr
Input dedicated pin
• I2C bus pin
• Hysteresis input
Digital input
Pch Tr
C
Digital output
Nch Tr
Input/output pin
• I2C bus pin
• Hysteresis input
• N-ch open drain output
Digital input
Pch Tr
D
Analog output
Analog output
Analog output pin
Nch Tr
Analog feedback
(Continued)
6
MB88141A
(Continued)
Type
Circuit
Pch Tr
E
Nch Tr
Remarks
Analog/digital
output
Analog/digital
output
Analog/digital input/output pin
Analog feedback
Digital input
Mode control
Note : Circuit types B and C are I2C bus pins. Caution should be taken in using these pins because when the VCC
power is off current from the I2C bus line power supply VCCS can enter the VCC side of the device power
supply.
VCCS
VCCS
SDA (I2C bus line)
SCL (I2C bus line)
VCC
VCC
VCC
MB88141A
7
MB88141A
■ DATA CONFIGURATION
The MB88141A has the following data configuration the two operating modes (D/A converter (12-channel) and
I/O expander plus D/A converter), selected by the MOD pin.
1. For D/A Converter (12-channel) Operation (MOD = “L”)
(1) I2C Bus Format
First S6
S
S0 R/W
Slave address (7 bits)
0
: Sent from master device
S
: “Start” condition
C7
A
C0
D7
Channel selection
(8 bits)
A
D0
Last
D/A data (8 bits)
A
P
: Sent from MB88141A (slave device)
P
: “Stop” condition
A
(2) Slave Address Comparison (7 bits)
Slave address input (7 bits)
: “Acknowledge” output
Internally fixed
Externally set
S6
S5
S4
S3
S2
S1
S0
CS6 CS5 CS4 CS3 CS2 CS1 CS0
1
0
0
1
0
0
0
=
1
0
0
1
0
0
0
1
0
0
1
0
0
1
=
1
0
0
1
0
0
1
1
0
0
1
0
1
0
=
1
0
0
1
0
1
0
1
0
0
1
0
1
1
=
1
0
0
1
0
1
1
1
0
0
1
1
0
0
=
1
0
0
1
1
0
0
1
0
0
1
1
0
1
=
1
0
0
1
1
0
1
1
0
0
1
1
1
0
=
1
0
0
1
1
1
0
1
0
0
1
1
1
1
=
1
0
0
1
1
1
1
Address comparison: Operates only for devices whose own slave address (internally fixed CS6 to CS3 and
externally set CS2 to CS0) matches the slave address input value.
(3) R/W Selection (1 bit)
Fixed at “0” (the D/A converter performs write operations only) .
8
MB88141A
(4) Channel Selection (8 bits)
C7 C6 C5 C4 C3 C2
C1
C0
Channel select
×
×
×
×
0
0
0
1
AO1 selected
∼
All channels selected *1
∼
0
∼
0
∼
0
∼
0
∼
×
∼
×
∼
×
∼
×
×
×
×
×
1
1
0
0
AO12 selected
×
×
×
×
1
1
0
1
Don’t Care
×
×
×
×
1
1
1
0
Don’t Care
×
×
×
×
1
1
1
1
All channels selected *2
× : Don’t Care
*1: The 1 byte of data following the channel selection is set on all channels (all channels set to same data value) .
S
Slave address (7 bits)
0
A
XXXX0000
A
D/A data (8 bits)
A
P
*2: The 12 bytes of data following the channel selection are set on all channels (all channels set to separate data
values) .
S
Slave
address
0
A
X X X X1 1 1 1
: Sent from master device
S
: “Start” condition
A
AO1 data
A
AO12 data
A
P
: Sent from MB88141A (slave device)
P
: “Stop” condition
A
: “Acknowledge” output
Note: Setting will repeat, continuing in order from ch1, until the start and stop conditions are acknowledged.
(5) D/A Data (8 bits)
D7 D6 D5 D4 D3
D2
D1
D0
D/A output
0
0
0
0
0
0
0
1
≅ (VREF / 256) × 1 + VSS
0
0
0
0
0
0
1
0
≅ (VREF / 256) × 2 + VSS
∼
≅ VSS
∼
0
∼
0
∼
0
∼
0
∼
0
∼
0
∼
0
∼
0
1
1
1
1
1
1
1
0
≅ (VREF / 256) × 254 + VSS
1
1
1
1
1
1
1
1
≅ (VREF / 256) × 255 + VSS
Note: VREF = VDD − VSS
9
MB88141A
2. For D/A Converter + I/O Expander Operation (MOD = “H”)
(1) I2C Bus Format
First S6
S
S0 R/W
Slave address (7 bits)
First S6
S
1
A
S0 R/W
Slave address (7 bits)
0
: “Start” condition
D0
Digital data (8 bits)
C7
A
: Sent from master device
S
D7
Last
A
C0
Channel selection
(8 bits)
P
D7
A
D0
Digital data (8 bits)
Last
A
P
: Sent from MB88141A (slave device)
P
: “Stop” condition
A
: “Acknowledge” output
(2) Slave Address Comparison (7 bits)
Slave address comparison is the same as for D/A converter (12-channel) operation (see “1. (2) “Slave Address
Comparison”), with the exception that the CS2 setting determines the number of D/A converter channels and
the number of I/O expander bits.
CS2
D/A converter
I/O expander
0
4 channels (AO1 to AO4)
8 bits (D7 to D0)
1
8 channels (AO1 to AO8)
4 bits (D3 to D0)
When CS2 = “1” is selected, the upper 4 bits (D7 to D4) of write operations (I2C bus to parallel interface) are
ignored, and the upper 4 bits of read operations (parallel interface to I2C bus) are output at “0” (low) .
(3) R/W Selection (1 bit)
10
R/W
I/O expander operation
D/A converter operation
0
I2C bus input → parallel data output
I2C bus input → analog output
1
Parallel data input → I2C bus output

MB88141A
(4) Channel Selection (8 bits)
×
×
×
×
0
0
0
0
I/O expander operation
×
×
×
×
0
0
0
1
AO1 selected
AO4 selected
×
×
×
×
0
1
0
1
Don’t care (AO5 selected)
Don’t care (AO8 selected)
×
×
×
×
1
0
0
1
Don’t Care
∼
0
∼
0
∼
0
∼
1
∼
×
∼
×
∼
×
∼
×
∼
∼
0
∼
0
∼
1
∼
0
∼
×
∼
×
∼
×
∼
×
∼
∼
Channel select
∼
C0
∼
C1
∼
C2
∼
C3
∼
C4
∼
C5
∼
C6
∼
C7
×
×
×
×
1
1
1
0
Don’t Care
×
×
×
×
1
1
1
1
I/O expander continuous operation
( ): When using D/A converter 8 channel, I/O expander 4 bit operation.
× : Don’t Care
(5) D/A Data (8 bits)
Same as “1 (5) D/A Data (8 bits)”.
(6) I/O Expander Continuous Operation
I2C bus input → parallel data output
S
Slave
address
0
A
X X X X1 1 1 1
A
Digital data
A
Digital data
A
P
A
P
Note: In continuous operation, operation continues until start and stop conditions are acknowledged.
Parallel data input → I2C bus output
Slave
S
1
A
Digital data
address
: Sent from master device
S
: “Start” condition
A
Digital data
A
Digital data
: Sent from MB88141A (slave device)
P
: “Stop” condition
A
: “Acknowledge” output
11
MB88141A
■ TIMING DIAGRAM (I2C BUS SPECIFICATIONS)
"Start"
condition
Data
change
"Acknowledge"
response
SDA
input
S6
S5
S4
S3
S2
S1
SCL
input
1
2
3
4
5
6
S0 R/W ACK C7
7
8
9
10
"Acknowledge"
response
C6
C5
C0 ACK D7
11
12
17
18
19
"Acknowledge" "Stop"
response
condition
D6
20
D0 ACK
26
27
Delay
AO1
to
AO12
Analog output
Delay
D0 to D7
output
HiZ state
D0 to D7
input
HiZ input
Digital output
Load data
SDA
output
HiZ state
Load data
DX
"Acknowledge"
response
ACK D7
D6
D5
D0
D7
D6
D0
D7
Note:
• The SDA input acknowledge response (ACK) is an output signal from the MB88141A.
• The D0-D7 input and output timing represent the timing of switching to write and read operations respectively.
Also, D0-D7 input remains in HiZ state between the end of a read operation and the acknowledgment of the
next I/O write signal.
■ ANALOG OUTPUT VOLTAGE RANGE
R-2R ladder circuit
VDD1&VDD2
Operating Amp circuit
VCC ( = VDD1, VDD2)
Analog output range
VSS1&VSS2
12
GND ( = VSS1, VSS2)
MB88141A
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Max.
−0.3
+7.0 *
V
−0.3
+7.0 *
V
−0.3
+7.0 *
V
VIN
−0.3
VCC + 0.3
V
VOUT
−0.3
VCC + 0.3
V
VDD
VSS
Input voltage
Output voltage
Unit
Min.
VCC
Supply voltage
Rating
With reference to GND,
at Ta = +25 °C
Power consumption
PD


250
mW
Operating temperature
Ta

−20
+85
°C
Tstg

−55
+120
°C
Storage temperature
*: VCC ≥ VDD1 ≥ VSS1, VCC ≥ VDD2 ≥ VSS2
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage 1
Supply voltage 2
Supply voltage 3
Symbol
Conditions
VCC
GND
VDD1
VSS1
VDD2
VSS2
Value
Unit
Min.
Typ.
Max.

4.50
5.00
5.50
V


0

V
VCC ≥ VDD1 > VSS1
VDD1 − VSS1 ≥ 2.0 V
2.00

VCC
V
0.00

3.50
V
VCC ≥ VDD2 > VSS2
VDD2 − VSS2 ≥ 2.0 V
2.00

VCC
V
0.00

3.50
V
IAL
Source current
0

1.00
mA
IAH
Sink current
0

1.00
mA
Oscillator limit output capacitance
COL



1.00
µF
Digital data setting range


#00

#FF

Operating temperature
Ta

−20

+85
°C
Analog output current
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
13
MB88141A
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(1) Digital Circuits
Parameter
(VCC = +5 V ± 10%, GND = 0 V, Ta = −20 °C to +85 °C)
Symbol
Pin name
VCC
Supply current
ICC
Input leak current
IILK
“L” level input voltage
VIL
“H” level input voltage
VIH
SDA, SCL
CS0, CS1
CS2, MOD
D0 to D7
Input hysteresis width
VHYS
SDA, SCL
“H” level output voltage
VOH
“L” level output voltage
VOL2
VOL3
D0 to D7
SDA
(2) Analog Circuits 1
Parameter
Current consumption
Resolution
Monotonic increase
14
Max.
4.50
5.00
5.50
V

1.00
3.70
mA
−10

+10
µA

0

0.30 VCC
V

0.70 VCC

VCC
V

0.05 VCC


V
VCC − 0.4


IOL = 2.5 mA


0.40
IOL = 3.0 mA


0.40
IOL = 6.0 mA


0.60
VIN = 0 to VCC
IOH = −400 µA
V
V
(VCC = +5 V ± 10%, GND = 0 V, Ta = −20 °C to +85 °C)
Symbol Pin name
IDD
VDD
Analog voltage
Unit
Typ.
SCL = 400 kHz,
no load
VCC
Value
Min.

Supply voltage
VOL1
Conditions
VSS
VDD1,
VDD2
VSS1,
VSS2
Conditions
No load
IDD = IDD1 + IDD2
VDD1 − VSS1 ≥ 2.0 V
VDD2 − VSS2 ≥ 2.0 V
Res
Rem
Non-linearity error
LE
Differential linearity error
DLE
AO1
to
AO12
No load
VDD1,VDD2 ≤ VCC − 0.1 V
VSS1,VSS2 ≥ 0.1 V
Value
Unit
Min.
Typ.
Max.

1.20
2.50
2.0

VCC
GND

3.5

8

bit

8

bit
−1.5

+1.5
LSB
−1.0

+1.0
LSB
mA
V
MB88141A
Non-linearity error :
Error in the input/output curve with respect to a straight line connecting output voltage at “00” and output voltage
at “FF” levels.
Differential linearity error :
Deviation from ideal voltage with respect to a 1-bit increase in digital value.
Analog output
Ideal linearity
VAOH
Non-linearity error
VAOL
#00
#FF
Digital setting
Note: VAOH and VDD, as well as VAOL and Vss are not necessarily the same values.
(3) Analog Circuits 2
Parameter
(VCC = VDD1 = VDD2 = +5 V, GND = VSS1 = VSS2 = 0 V, Ta = −20 °C to +85 °C)
Symbol Pin name
Conditions
Unit
Min.
Typ.
Max.
VSS

VSS + 0.1
V
VSS − 0.2
Digital data
IAH = 500 µA
VSS
“00”
IAL = 1.0 mA
VSS − 0.3
VSS
VSS + 0.2
V

VSS + 0.2
V
VSS
VSS + 0.3
V
IAH = 1.0 mA
VSS

VSS + 0.3
V
VDD − 0.1

VDD
V

VDD
V
VDD
VDD + 0.2
V

VDD
V
VDD
VDD + 0.3
V
Output minimum voltage 1
VAOL1
IAL = 0 µA
Output minimum voltage 2
VAOL2
IAL = 500 µA
Output minimum voltage 3
VAOL3
Output minimum voltage 4
VAOL4
AO1
to
AO12
Value
Output minimum voltage 5
VAOL5
Output maximum voltage1
VAOH1
Output maximum voltage2
VAOH2
Output maximum voltage3
VAOH3
Output maximum voltage4
VAOH4
VDD − 0.2
Digital data
IAH = 500 µA
VDD − 0.2
“FF”
IAL = 1.0 mA
VDD − 0.3
Output maximum voltage5
VAOH5
IAH = 1.0 mA
IAL = 0 µA
IAL = 500 µA
VDD − 0.3
15
MB88141A
2. AC Characteristics
Value
ConSymbol
dition
Parameter
Standard mode
High-speed mode
Min.
Max.
Min.
Max.
SCL clock frequency
fSCL

0
100
0
400
Bus free time between “stop” condition
and “start” condition
tBUF

4.7

1.3

Hold time (resend) “start” condition.
The first clock pulse is generated after
this interval.
tHD ; STA

4.0

0.6

SCL clock low hold time
tLOW

4.7

1.3

SCL clock high hold time
tHIGH

4.0

0.6

Resend “start” condition setup time
tSU ; STA

4.7

0.6

Data hold time
tHD ; DAT

0

0
0.9
Data setup time
tSU ; DAT

250

100

SDA and SCL signal fall time
tR


1000
20 + 0.1 Cb
300
SDA and SCL signal rise time
tF


300
20 + 0.1 Cb
300
tSU ; STO

4.0

0.6

tSP



0
50


250
20 + 0.1 Cb
250



20 + 0.1 Cb
250
“Stop” condition setup time
Pulse width of spike suppressed by input
filter
Unit
kHz
µs
ns
µs
Output fall time when Sink current 3mA
bus capacitance is
between 10 pF and
Sink current 6mA
400 pF
tOF
I2C bus line capacitance load
Cb


400

400
pF
Analog output settling time
tDL ; AO
*1

100

100
µs
Digital output delay time
tDL ; DO
*2

300

300
tDZ ; DI
*3
200

200

tSU ; DI

250

100

tHD ; DI

0.9

0.9

D/A
Input open time
I/O
expander Digital input setup time
Digital input hold time
*1: Load condition 1
ns
ns
µs
*2: Load condition 2
Measurement point
Measurement point
DUT
DUT
RAL = 10 kΩ
CAL = 50 pF
CAL = 50 pF
*3 : The I/O expander input open time value applies to a read operation following an I/O write operation, or to an
I/O write operation following a read operation.
16
MB88141A
• Input/Output Timing
tHD ; STA
tBUF
SDA
Acknowledge
Acknowledge
tSU ; DAT
SCL
P
tHD ; DAT
S
tLOW
9
tHIGH
tR
tDZ ; DI
D0
to
D7
18
tHD ; STA
Sr
tSU ; DI
P
tSU ; STO
tF
tHD ; DI
Digital input
tDZ ; DI
D0
to
D7
tSU ; STA
tSP
Digital input
tDL ; DO
Digital output
tDL ; AO
AO1
to
AO12
90%
10%
Analog output
Note: The discrimination levels are 70% and 30% of VCC.
17
MB88141A
■ ORDERING INFORMATION
Part number
MB88141AP
24-pin plastic DIP
(DIP-24P-M02)
MB88141APF
24-pin plastic SOP
(FPT-24P-M01)
MB88141APFV
18
Package
24-pin plastic SSOP
(FPT-24P-M03)
Remarks
MB88141A
■ PACKAGE DIMENSIONS
24-pin plastic DIP
(DIP-24P-M02)
+0.20
+.008
30.20 –0.30 1.189 –.012
INDEX-1
13.55±0.25
(.533±.010)
INDEX-2
0.51(.020)MIN
4.96(.195)
MAX
3.00(.118)
MIN
0.25±0.05
(.010±.002)
0.98
.039
+0.50
–0
+.020
–0
1.27(.050)
MAX
C
1.50
.059
+0.50
–0
+.020
–0
2.54(.100)
TYP
0.45±0.08
(.018±.003)
15.24(.600)
TYP
15°MAX
1994 FUJITSU LIMITED D24015S-2C-3
Dimensions in mm (inches)
(Continued)
19
MB88141A
(Continued)
24-pin plastic SOP
(FPT-24P-M01)
+0.25
2.25(.089)MAX
(Mounting height)
+.010
15.24 –0.20 .600 –.008
0.05(.002)MIN
(STAND OFF)
5.30±0.30
(.209±.012)
INDEX
1.27(.050)
TYP
0.45±0.10
(.018±.004)
+0.40
6.80 –0.20
7.80±0.40
(.307±.016)
+.016
.268 –.008
+0.05
Ø0.13(.005)
M
0.15 –0.02
+.002
.006 –.001
0.50±0.20
(.020±.008)
Details of "A" part
0.20(.008)
"A"
0.10(.004)
13.97(.550)REF
0.50(.020)
0.18(.007)MAX
0.68(.027)MAX
C
2000 FUJITSU LIMITED F24007S-3C-5
Dimensions in mm (inches)
(Continued)
20
MB88141A
(Continued)
24-pin plastic SSOP
(FPT-24P-M03)
Note) * marked dimensions do not include resin residues.
+0.20
* 7.75±0.10(.305±.004)
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.10(.004)
* 5.60±0.10
INDEX
0.65±0.12(.0256±.0047)
(.220±.004)
+0.10
C
6.60(.260)
NOM
"A"
+0.05
0.22 –0.05
0.15 –0.02
+.004
–.002
.006 –.001
.009
7.15(.281)REF
7.60±0.20
(.299±.008)
Details of "A" part
+.002
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
2000 FUJITSU LIMITED F24018S-2C-3
Dimensions in mm (inches)
21
MB88141A
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
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applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.