FUJITSU MB88146AP

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-13513-1E
Linear IC Converter
CMOS
D/A Converter for Digital Tuning
(12-channel, 8-bit, on-chip OP amp., low-voltage)
MB88146A
■ DESCRIPTION
The MB88146A is an 8-bit D/A converter with twelve built-in channels. The 12 analog outputs each have a builtin OP amplifier with large current drive-capability.
The data input/output format is CS (chip select) with serial bus connection available.
A built-in 12-bit I/O expander enables serial ↔ parallel conversion (8 of the 12 bits can also be used for analog
output).
This product can be used for microcontroller port expansion, electronic level adjustment, replacement of semifixed resistance for tuning, etc.
■ FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Ultra low power consumption (1.2 mW/chl: typical)
Ultra compact package
Built-in 12-channel R-2R type 8-bit D/A converter
Built-in 12-bit I/O expander (8 bits also function as analog output)
Built-in analog output amplifier (sink current 1.0 mA maximum, source current 1.0 mA maximum)
Built-in power-on detection circuit (initialized at detection of VccD power-on)
MCU interface compatible with 3 V to 5 V systems
Power divided into MCU interface power supply (VccD) and OP amplifier power supply (VccA), D/A converter
power supply (VccD)
Analog output capability from 0 V to VccA
Serial data I/O operates to maximum of 2.5 MHz (in cascade connection, up to 2.5 MHz when VccD = 5 V, up
to 1.5 MHz when VccD = 3 V)
CMOS process
Choice of two packages: SDIP-24 pin and SSOP-24 pin.
■ PACKAGES
24-pin Plastic DIP
24-pin Plastic SSOP
(DIP-24P-M02)
(FPT-24P-M03)
MB88146A
■ PIN ASSIGNMENT
(TOP VIEW)
AO1
1
24
GND
AO2
2
23
VCCA
AO3
3
22
CS
AO4
4
21
SO
D11/AO5
5
20
SI
D10/AO6
6
19
CLK
D9/AO7
7
18
D0
D8/AO8
8
17
D1
D7/AO9
9
16
D2
D6/AO10
10
15
D3
D5/AO11
11
14
VCCD
D4/AO12
12
13
VDD
DIP-24, SSOP-24
2
MB88146A
■ PIN DESCRIPTION
Pin no.
Pin name
Description
1 to 4
AO1 to AO4
D/A converter analog output pins (VDD to GND output).
(Default: output #00 setting level)
5 to 12
D11/AO5 to
D4/AO12
These pins may be used either as I/O expander parallel input/output (VCCA/
GND output 0.5 VCCA/0.2 VCCA input) or D/A converter analog output (VDD to
GND output).
Pin status is controlled by input data.
See “■Data Configuration”. (Default: Input mode, Hi-Z state)
13
VDD*1
14
VCCD*1
MCU interface power supply pin (power supply for I/O expander).
15 to 18
D3 toD0
I/O expander parallel input/output pins.
(VCCD/GND output: When VCCD
4.0 V, 0.5 VCCD/0.2 VCCD input,
When VCCD < 4.0 V, 2 V/0.2 VCCD input)
Pin status is controlled by input data.
See “■Data Configuration.” (Default: Input mode, Hi-Z state)
19
CLK*2
Shift clock signal input pin.
When CS = “L,” SI data is loaded into the shift register at the rising edge of the
shift clock.
20
SI*2
Data input pin (serial input pin).
Used for 16-bit serial data input.
21
SO
Data output pin (serial output pin).
The first bit (LSB) data of the 16-bit shift register is output simultaneously with
the falling edge of the shift clock.
When CS output = “H,” this pin goes to high impedance state.
22
CS*2
Chip select signal input pin.
Input to shift registers is enabled when the CS signal falling edges. Shift register
contents can be executed when the CS signal rising edges.
23
VCCA*1
24
GND
D/A converter reference power pin.
Analog unit power supply pin (OP amplifier power supply).
Common GND pin.
*1: Be sure that VCCA
VCCD, and that VCCA
*2: Do not leave this pin in floating state.
VDD.
3
MB88146A
■ BLOCK DIAGRAM
CS
SO
SI
16-bit shift register and controller
CLK
VCCD
DF
DF
DE
DE
DD
DD
DC
DC
DB
DB
BA
D9
BA
D9
I/O expander
D8
D7
D8
D7
DF
DE
D6
D6
D5
CNTL
D4
D5
D4
D5
D4
D0
D1
D2
D3
12
DF
D8
DF
D8
8-bit latch
DF
VDD
VCCA
D8
8-bit latch
D8
DF
R-2R
rudder circuit
−
−
+
DF
D8
8-bit latch
D8
R-2R
rudder circuit
+
DF
DF
8-bit latch
D8
R-2R
rudder circuit
−
+
DF
D8
R-2R
rudder circuit
−
GND
+
8
AO1
4
AO4
D11/AO5
D4/AO12
MB88146A
■ DATA CONFIGURATION
1. Data Configuration
MSB (last)
LSB (first)
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Setting data
Channel select
2. Channel Select
D3
D2
D1
D0
Function
0
0
0
0
Don’t Care/special function
0
0
0
1
AO1 selected
0
0
1
0
AO2 selected
to
to
to
to
to
1
0
1
1
AO11 selected
1
1
0
0
AO12 selected
1
1
0
1
I/O expander (serial → parallel)
1
1
1
0
I/O expander (parallel → serial)
1
1
1
1
Expander status register (ESR)
5
MB88146A
3. Setting Data
• Don’t Care/special function (Channel select = “0000”)
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4
Analog output voltage level
×
×
×
×
×
×
×
×
0
0
0
0
Don’t Care
to
to
to
to
to
to
to
to
to
to
to
to
Don’t Care
×
×
×
×
×
×
×
×
1
0
1
1
Don’t Care
0
0
0
0
0
0
0
0
1
1
0
0
GND (all channels)
0
0
0
0
0
0
0
1
1
1
0
0
VDD/256 × 1 (all channels)
0
0
0
0
0
0
1
0
1
1
0
0
VDD/256 × 2 (all channels)
to
to
to
to
to
to
to
to
to
to
to
to
to
1
1
1
1
1
1
1
0
1
1
0
0
VDD/256 × 254 (all channels)
1
1
1
1
1
1
1
1
1
1
0
0
VDD/256 × 255 (all channels)
×
×
×
×
×
×
×
×
1
1
0
1
Hi-Z (I/O expander state)*
×
×
×
×
×
×
×
×
1
1
1
0
Reset (state when power is ON)
×
×
×
×
×
×
×
×
1
1
1
1
Don’t Care
×: Don’t care *: Hi-Z output on all channels of AO5 through AO12
• D/A Converter (Channel select = “0001” to “1100”)
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4
0
0
0
0
0
0
0
0
0
0
0
0
GND
0
0
0
0
0
0
0
1
0
0
0
0
VDD/256 × 1
0
0
0
0
0
0
1
0
0
0
0
0
VDD/256 × 2
0
0
0
0
0
0
1
1
0
0
0
0
VDD/256 × 3
to
to
to
to
to
to
to
to
to
to
to
to
to
1
1
1
1
1
1
0
1
0
0
0
0
VDD/256 × 253
1
1
1
1
1
1
1
0
0
0
0
0
VDD/256 × 254
1
1
1
1
1
1
1
1
0
0
0
0
VDD/256 × 255
×
×
×
×
×
×
×
×
0
0
0
1
Hi-Z (I/O expander state)*
×
×
×
×
×
×
×
×
0
0
1
0
Don’t Care
to
to
to
to
to
to
to
to
to
to
to
to
Don’t Care
×
×
×
×
×
×
×
×
1
1
1
1
Don’t Care
×: Don’t care *: Only AO5 through AO12 output is valid
6
Analog output voltage level
MB88146A
• I/O Expander [Channel select = “1101”]: Serial → Parallel Conversion
Performs parallel conversion of data bits D4 to DF for output on pins D0 to D11.
Note that only those pins designated for output in the ESR (expander status register) are output.
Shift register
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
↓
↓
D11 D10
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Parallel I/O pins (output state)
• I/O Expander [Channel select = “1110”]: Parallel → Serial Conversion
Writes data from D0 to D11 pins to bits D4 to DF in the shift register.
Data is output to the SO pin on the shift clock (CLK) signal (The first 4 bits output data D0 to D3, so the
converted output should be read as data bits 5 through 16.).
Note that the data value is “0” for pins designated for output in the ESR (expander status register) as well as
analog output pins.
Shift register
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
↑
↑
D11 D10
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 Parallel I/O pins (output state)
• Expander Status Register [Channel select = “1111”]
Shift register
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4
↓
↓
D11 D10
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ESR
This register sets the status of each pin.
Setting
Pin status
“0”
• Input standby status (Hi-Z output)
• D11 to D4 pins used for analog output should be set to “0.”
“1”
• Output state
7
MB88146A
Note: After power VCCD is turned on, the state of pins and registers is as follows.
Pin
State
AO1 to AO4
“L” output
D11/AO5 to D4/AO12
Hi-Z state (input state)
D3 to D0
Hi-Z state (input state)
Register
State
Shift register
Bits DF to D8 are “0,” and D7 to D0 are not defined (retain prior state).
D/A register
All reset to “0.”
Parallel output register
Not defined (retain prior state).
Expander status register (ESR) All reset to “0.”
• ESR settings have priority in determining pin states. Switching between input standby state and analog output
state is enabled even when the ESR value is “1.” When the ESR value returns to “0”, the pin returns to its
previously defined state.
• In input standby state with AO set for Hi-Z output, the AO output setting can be used for transition to AO output
state.
8
MB88146A
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Conditions
VCCA
Power supply voltage
VCCD
Based on GND
(Ta = +25°C)
VDD
Input voltage 1
Vin1
Output voltage 1
Vout1
Input voltage 2
Vin2
Output voltage 2
Vout2
SI, CLK, CS,
SO, D0 to D3
D4 to D11
Unit
Min.
Max.
–0.3
+7.0
V
–0.3
VCCA*
V
–0.3
VCCA*
V
–0.3
VCCD + 0.3
V
–0.3
VCCD + 0.3
V
–0.3
VCCA + 0.3
V
–0.3
VCCA + 0.3
V
Power consumption
PD
—
—
250
mW
Operating temperature
Ta
—
–20
+85
°C
Storage temperature
Tstg
—
–55
+150
°C
* : VCCA
VCCD, VCCA
VDD
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Conditions
VCCA
—
VCCD
Power supply voltage
VDD
VCCA
VCCA
Value
Unit
Min.
Typ.
Max.
4.5
5.0
5.5
V
VCCD
2.7
—
VCCA
V
VDD
2.0
—
VCCA
V
GND
—
—
0
—
V
IAL
Source current
—
—
1.0
mA
IAH
Sink current
—
—
1.0
mA
Oscillation limit output
capacity
COL
—
—
—
1.0
µF
Operation temperature
Ta
—
–20
—
+85
°C
Analog output current
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
9
MB88146A
■ ELECTRICAL CHARACTERISTIC
1. DC Characteristics
(1) Digital section
(VCCD
Parameter
Symbol Pin name
Power supply voltage
VCCD
Power supply current
ICCD
Standby current
ICCS
Input leak current
IILK1
Value
Conditions
CLK, SI,
CS,
D0 to D3
Unit
Min.
Typ.
Max.
2.7
5.0
5.5
V
—
0.2
0.5
mA
CLK, SI, CS Stop
Vin = VCCD or
GND
–10
—
+10
µA
Vin = 0 to VCCD
–10
—
+10
µA
0.5 × VCCD
—
—
V
2.0
—
—
V
—
—
0.2 × VCCD
V
+10
µA
—
VCCD
VCCA, Ta = –20°C to +85°C)
CLK =1 MHz,
(Unloaded)
VCCD
4.0 V
“H” level input voltage
VIH1
“L” level input voltage
VIL1
High-impedance leak
current
IOLK
SO
Vin = 0 to VCCD
–10
—
“H” level output voltage
VOH1
VCCD − 0.4
—
—
V
VOL1
SO,
D0 to D3
IOH = –0.4 mA
“L” level output voltage
—
—
0.4
V
VCCD < 4.0 V
—
IOL = 2.5 mA
(2) D/A converter section
(VCCA = 5 V ± 10%, Ta = –20°C to +85°C)
Symbol
Power supply voltage
VDD
Power supply current
IDD
Resolution
Res
Monotonic increase
Rem
Nonlinearity error
LE
Differential linearity error
Nonlinearity error:
Differential linearity
error:
10
DLE
Pin name
VDD
AO1 to AO12
Value
Conditions
Min.
Typ.
Max.
Unit
VDD
VCCA
2.0
5.0
5.5
V
VDD
VCCA
—
1.2
2.5
mA
—
8
—
bits
—
8
—
bits
–1.5
—
+1.5
LSB
–1.0
—
+1.0
LSB
Unload
VDD = VCCA – 0.1 V
Digital value: #06
to #FF
Deviation (error) in input/output
curves with respect to an ideal
straight line connecting output
voltage at “06” and output voltage
at “FF.”
Deviation (error) in amplification with
respect to theoretical increase in
amplification per 1-bit increase in
digital value.
Ideal straight line
VAOH
Analog output
Parameter
Non linearity error
VAOL
#06
#FF
Digital setting
Note: The value of VAOH and VDD, and the value of VAOL
and GND are not necessarily equivalent.
MB88146A
(3) Operational Amplifier/Analog output section
(VDD = VCCA = 5.0 V, Ta = –20°C to +85°C)
Parameter
Power supply voltage
Symbol Pin name
VCCA
Value
Conditions
Typ.
Max.
4.5
5.0
5.5
V
—
1.0
3.7
mA
–10
—
+10
µA
—
0.5 × VCCA
—
—
V
—
—
—
0.2 × VCCA
V
VCCA − 0.4
—
—
V
—
VCCA
Unit
Min.
#80 setting
(Unloaded)
Power supply current
ICCA
Input leak current
IILK2
“H” level digital input
voltage
VIH2
“L” level digital input
voltage
VIL2
“H” level digital output
voltage
VOH2
IOH = –0.4 mA
“L” level digital output
voltage
VOL2
IOL = 2.5 mA
—
—
0.4
V
Analog output minimum
voltage 1
VAOL1
IAL = 0 A
#00 setting
GND
—
0.1
V
Analog output minimum
voltage 2
VAOL2
IAL = 0.5 mA
#00 setting
–0.2
GND
0.2
V
Analog output minimum
voltage 3
VAOL3
IAH = 0.5 mA
#00 setting
GND
—
0.2
V
Analog output minimum
voltage 4
VAOL4
IAL = 1.0 mA
#00 setting
–0.3
GND
0.3
V
Analog output minimum
voltage 5
VAOL5
IAH = 1.0 mA
#00 setting
GND
—
0.3
V
Analog output
maximum voltage 1
VAOH1
IAL = 0 A
#FF setting
VCCA − 0.1
—
VCCA
V
Analog output
maximum voltage 2
VAOH2
IAL = 0.5 mA
#FF setting
VCCA − 0.2
—
VCCA
V
Analog output
maximum voltage 3
VAOH3
IAH = 0.5 mA
#FF setting
VCCA − 0.2
VCCA
VCCA + 0.2
V
Analog output
maximum voltage 4
VAOH4
IAL = 1.0 mA
#FF setting
VCCA − 0.3
—
VCCA
V
Analog output
maximum voltage 5
VAOH5
IAH = 1.0 mA
#FF setting
VCCA − 0.3
VCCA
VCCA + 0.3
V
Vin = 0 to VCCA
D4 to D11
AO1 to AO12
AO1 to AO12
Note: IAH: Analog output sink current IAL: Analog output source current
11
MB88146A
2. AC Characteristics
• For operation at VCCD = 5.0 V
(VDD = VCCA = 5.0 V, Ta = –20°C to +85°C)
Parameter
Symbol
Conditions
Clock “L” level pulse width
tCKL
Clock “H” level pulse width
Value
Unit
Min.
Typ.
Max.
—
200
—
—
ns
tCKH
—
200
—
—
ns
tCr
—
—
—
200
ns
Clock rise time
tCf
—
—
—
200
ns
Serial input setup time
tSSU
—
30
—
—
ns
Serial input hold time
tSHD
—
60
—
—
ns
Serial output delay time
tSOD
See “Load condition 1”
0
80
170
ns
CS input setup time
tCSU
—
100
—
—
ns
CS hold time
tCCH
—
200
—
—
ns
CS “H” level hold time
tCSH
—
100
—
—
ns
Data output enable time
tSO
—
—
—
200
ns
Data output float time
SOZ
t
—
—
—
200
ns
Parallel input setup time
tPSU
—
30
—
—
ns
Parallel input hold time
tPHD
—
60
—
—
ns
Parallel output delay time
tPOD
See “Load condition 1”
—
100
170
ns
Analog output delay time
tAOD
See “Load condition 2”
—
30
100
µs
tR
—
—
—
50
ms
∆VR
—
–10
—
10
V/µs
Clock fall time
Power supply rise time
Power-on reset non-startup power
supply variation
• For operation at VCCD = 3.0 V *1
(VCCD = 3.0 V, Ta = –20°C to +85°C)
Parameter
Serial output delay time
Parallel output delay time
Value
Symbol
Conditions
tSOD
See “Load condition 1”*2
tPOD
3
See “Load condition 2”*
Typ.
Max.
0
120
300
ns
—
120
300
ns
*1: Items not listed are identical to characteristics for VCCD = 5.0 V.
*2: Cascade connection enabled at 1.5 MHz.
*3: Applied to D0 to D3 operating at VCCD.
Load Conditions
• Load condition 1
• Load condition 2
Measurement point
CL = 20 pF to 100 pF
12
Measurement point
RAL = 10 kΩ
Unit
Min.
CAL = 50 pF
MB88146A
• Input/Output Timing (CS method)
tCr
tCKH
tCf
CLK
tCKL
SI
tSSU
tCSH
tSHD
tCCH
tCSU
CS
tSO
tSOD
tSOD
tSOZ
SO
tPSU
tPHD
D0 to D11 (For input)
tPOD
D0 to D11 (For output)
tAOD
90 %
AO1 to AO12
10 %
The decision level for CLK, SI, CS, SO, and D0 to D3 is 80% and 20% of VCCD. The decision level for D4 to D11 is 80%
and 20% of VCCA, and for AO1 to AO12 is 90% and 10% of VCCA.
• Power Supply Timing
• Power-On Timing
tR
2.0 V
VCCD
0.2 V
• Power-On Reset Non-Startup Supply Variation
Upper limit, 5.5V
VCCD
∆V
∆V
∆T
∆T
∆VR =
∆V
∆T
2.7V, lower limit
13
MB88146A
3. Analog Output Noise Characteristic
(VDD = VCCD = VCCA = 5.0 V, Ta = +25°C)
Parameter
Symbol
Value
Measurement
Unit
condition
Min. Typ. Max.
Conditions
Digital supply noise
reduction ratio
PSRD
fNOISE = 1 kHz
1
—
—
20
dB
Analog supply noise
reduction ratio
PSRA
fNOISE = 1 kHz
1
—
—
20
dB
D/A supply noise
reduction ratio
PSRDA
fNOISE = 1 kHz
1
—
—
0
dB
VN1
• During serial transfer
• During analog operation
• During Hi-Z commands.
See “Operating Noise VN1.”
2
–30
—
30
mV
VN2
• Serial → parallel conversion
See “I/O Expander Operating
Noise 1 VN2.”
During digital-only pin operation
• During parallel → serial conversion
• ESR setting
During digital input/digital output
switching
2
–30
—
30
mV
VN3
• During serial → parallel conversion
See “I/O Expander Operating
Noise 2 VN3.”
During digital/analog capable pin
operation
• ESR setting
During digital output/digital output
switching
2
–0.1
—
0.1
V
Operating noise
I/O expander operating
noise 1
I/O expander operating
noise 2
• Measurement condition 1
• Measurement condition 2
VCCD = 5.0 V,VCCA = 5.0 V,VDD = 5.0 V
VCCD,VCCA,VDD
Measurement point
AO
Pattern
input
DUT
CAL = 30 pF
Input wave form
Sine wave
14
Offset
Amplitude
Temperature
Frequency
5.0 V
0.1 V
25°C
1 kHz
Measurement point
CLK = 2.5 MHz
SI
CS
AO
DUT
CAL = 30 pF
MB88146A
• Analog Output Noise Description
• Output Noise VN1
Noise to analog output during serial data transfer, analog operation, Hi-Z commands.
CLK
SI
Analog operation commands, Hi-Z commands
CS
AO×
Analog output
D11/AO5
to
D0/AO12
Digital input* ⇔ analog output
AO1
to
AO12
VN1
VN1
* Hi-Z state = digital input state.
• I/O Expander Operation Noise 1 VN2
Noise to analog output during parallel → serial conversion commands, serial → parallel conversion command for
digital-only pins, or ESR setting commands for switching between digital input and digital output.
CLK
SI
Parallel → serial conversion, serial → parallel conversion, ESR setting commands
CS
D3
to
D0
Parallel output
D11
to
D0
Digital input ⇔ digital output
AO1
to
AO12
VN2
VN2
(Continued)
15
MB88146A
(Continued)
• I/O Expander Operation Noise 2 VN3
Noise to analog output during serial → parallel switching commands for digital-only pins, or ESR setting commands
for switching between digital output and analog output.
CLK
SI
Serial → parallel switching commands, ESR setting commands
CS
D11
to
D4
Parallel output
D11/AO5
D0/AO12
AO1
to
AO12
16
Digital output ⇔ analog output
VN3
VN3
MB88146A
■ DATA INPUT/OUTPUT TIMING
MB88146A Data Input/Output Timing (Serial Bus Format)
• D/A converter operation, and I/O expander (serial → parallel conversion) operation, and ESR writing operation.
SI
CLK
D0
1
D1
2
D2
DE
3
DF
15
16
CS
AO×
D××
SO
Data input is enabled at the falling edge of the CS signal. 16-bit data is input, and the shift register command is
executed at the rising edge of CS.
In D/A converter operation, the analog output selected at the rising edge of CS is the conversion result. In serial
→ parallel conversion, the digital output selected at the rising edge of CS is the conversion result. In ESR write
operation, ESR data is set and pin status determined at the rising edge of CS.
• I/O expander (parallel → serial conversion) operation
SI
CLK
D0
1
DF
16
1
2
16
CS
D××
Retrieved parallel data
SO
D0
DF
Parallel-to-serial → Conversion result output
Data input is enabled at the falling edge of the CS signal. 16-bit data (parallel → serial conversion commands)
is input and commands accepted at the rising edge of CS. At the falling edge of CS, data from the parallel input
is loaded into bits D4 to DF of the shift register, and output from the SO pin timed to the falling edge of the CLK
signal.
17
MB88146A
■ USAGE PRECAUTIONS
1. Preventing Latch-Up
A condition known as “latch-up” may occur when the input or output pins of a CMOS IC device are exposed to
voltages higher then VCCD or VCCA or lower than GND voltage, or when voltages are applied to the device in
excess of rated values for VCCD, VccA, or VDD to GND voltages. Latchup produces a rapid increase in power
supply current, and may result in thermal destruction of elements. Users should take sufficient precautions to
ensure that absolute maximum ratings are not exceeded at any time during use.
2. Power Supply Pins
The power supply should be connected to the VCCD, VCCA, VDD, and GND terminals of the MB88146A with as
low an impedance as possible.
In addition, it is recommended that ceramic capacitors or approximately 0.1 µF be connected as bypass
capacitors between the VCCD, VCCA, and VDD terminals and the GND terminals.
■ ORDERING INFORMATION
Part number
MB88146AP
MB88146APFV
18
Package
24-pin Plastic DIP
(DIP-24P-M02)
24-pin Plastic SSOP
(FPT-24P-M03)
Remarks
MB88146A
■ PACKAGE DIMENSIONS
24-pin Plastic DIP
(DIP-24P-M02)
+.008
+0.20
30.20 –0.30 1.189 –.012
INDEX-1
13.55±0.25
(.533±.010)
INDEX-2
0.51(.020)MIN
4.96(.195)
MAX
3.00(.118)
MIN
0.25±0.05
(.010±.002)
0.98
.039
+0.50
–0
+.020
–0
1.50
0.45±0.08
(.018±.003)
.059
2.54(.100)
TYP
1.27(.050)
MAX
C
+0.50
–0
+.020
–0
15°MAX
15.24(.600)
TYP
1994 FUJITSU LIMITED D24015S-2C-3
Dimensions in mm (inches)
24-pin Plastic SSOP
(FPT-24P-M03)
* : These dimensions do not include resin protrusion.
+0.20
* 7.75±0.10(.305±.004)
1.25 –0.10
+.008
.049 –.004
Mounting height
0.10(.004)
* 5.60±0.10
INDEX
0.65±0.12(.0256±.0047)
7.15(.281)REF
C
1994 FUJITSU LIMITED F24018S-2C-2
(.220±.004)
+0.10
0.22 –0.05
+.004
.009 –.002
7.60±0.20
(.299±.008)
"A"
6.60(.260)
NOM
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
19
MB88146A
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9811
 FUJITSU LIMITED Printed in Japan
20
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.