FUJITSU SEMICONDUCTOR DATA SHEET DS07-13603-4E 16-bit Proprietary Microcontroller CMOS F2MC-16L MB90610A Series MB90611A/MB90613A ■ DESCRIPTION MB90610A series includes 16-bit microcontrollers optimally usable for high-speed real-time data processing in consumer appliances and for system control of printer, CD-ROM, celluar phone, copier, etc. The series uses the *F2MC-16L CPU which is based on the F2MC-16 but with enhanced high-level language and task switching instructions and additional addressing modes. The internal peripheral resources consist of a 3-channel serial port incorporating a UART function (and supporting I/O expansion serial mode), 8-channel 10-bit A/D converter, 2-channel PPG, 2-channel 16-bit reload timer, 8-channel chip select output, and 8-channel external interrupts. Also, multiplexed or non-multiplexed operation can be selected for the address/data bus. *: “F2MC is an abbreviation for “Fujitsu Flexible Microcontroller”. ■ FEATURES • F2MC-16L CPU • Minimum instruction execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication), maximum multiplier = 4 • Instruction set optimized for controller applications Upward object code compatibility with F2MC-16 (H) Wide range of data types (bit/byte/word/long word) Improved instruction cycles provide increased speed Additional addressing modes: 23 modes High code efficiency Access methods (bank access/linear pointer) Enhanced multiplication and division instructions (signed instructions added) High precision operations are enhanced by use of a 32-bit accumulator Extended intelligent I/O service (access area extended to 64 Kbytes) Maximum memory space: 16 Mbytes (Continued) ■ PACKAGE 100-pin Plastic LQFP 100-pin Plastic QFP (FPT-100P-M05) (FPT-100P-M06) MB90610A Series (Continued) • Enhanced high level language (C)/multitasking support instructions Use of a system stack pointer Enhanced pointer indirect instructions Barrel shift instructions Stack check function • Improved execution speed: Four byte instruction queue • Powerful interrupt function • Automatic data transfer function (does not use instructions) Internal peripherals • RAM: 1 Kbyte (MB90611A) 3 Kbytes (MB90613A) • General purpose ports 8, 16-bit data bus, multiplexed mode : 57 ports max. 16-bit non-multiplexed mode : 41 ports max. 8-bit non-multiplexed mode : 49 ports max. • UART (SCI): 3 channels For either asynchronous or clocked serial transfer (I/O expansion serial) • A/D converter: 8 channels (10-bit) 8-bit conversion mode also available • PPG (programmable pulse generator): 2 channels • 16-bit reload timer: 2 channels • Chip select output: 8 channels • External interrupts: 8 channels • 18-bit timebase timer Watchdog timer function • PLL clock multiplier function • CPU intermittent operation function • Various standby modes • LQFP-100/QFP-100 package • CMOS technology 2 MB90610A Series ■ PRODUCT LINEUP Part No. Parameter MB90611A MB90613A Classification Mask ROM ROM size — RAM size 1 Kbyte 3 Kbytes CPU functions Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time Ports I/O ports (CMOS/TTL) : 33 (31 CMOS/2 TTL) (N-channel open drain): 8 (16-bit non-multiplex mode) Total : 41 Packages : : : : : : 340 8/16 bits 1 to 7 bytes 1/4/8/16/32 bits 62.5 ns/4 MHz (PLL multiplier = 4) 1000 ns/16 MHz (minimum) FPT-100P-M05 FPT-100P-M06 UART (SCI) Three internal UARTs Full-duplex, double-buffered Selectable clock synchronous or asynchronous operation Built-in dedicated baud rate generator A/D Converter 10-bit × 8 channels A/D conversion time : 6.13 µs (98 machine cycles/16 MHz machine clock, includes sample and hold time) Triggers : Software, external, or multi-function timer output (RT0) activation can be selected. Activation modes : Single, scan (continuous conversion of multiple channels), continuous (continuous conversion of one channel), and stop (scan mode with synchronized conversion start) PPG 2 × 8-bit PPG outputs (1 channel PPG output in 16-bit mode) 16-Bit Reload Timer 16-bit reload timer operation (selectable toggle output, one-shot output) (Selectable count clock: 0.125 µs, 0.5 µs, or 2.0 µs for a 16 MHz machine cycle) Selectable event count function, 2 internal channels Chip select 8 outputs External interrupts 8 inputs External interrupt mode (Interrupts can be generated from four different types of request signal) PLL Function Other Selectable multiplier: 1/2/3/4 (Set a multiplier that does not exceed the assured operation frequency range.) — 3 MB90610A Series ■ PIN ASSIGNMENT 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P21/A01 P20/A00 P17/D15/AD15 P16/D14/AD14 P15/D13/AD13 P14/D12/AD12 P13/D11/AD11 P12/D10/AD10 P11/D09/AD09 P10/D08/AD08 D07/AD07 D06/AD06 D05/AD05 D04/AD04 D03/AD03 D02/AD02 D01/AD01 D00/AD00 VCC X1 X0 VSS ALE RD P55/WRL (Top view) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P71/INT1 P72/INT2 P73/INT3 P74/INT4/PPG0 P75/INT5/PPG1 P76/INT6/ATG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/INT7/TIN0 P81/TIN1 MD0 MD1 MD2 HST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P22/A02 P23/A03 P24/A04 P25/A05 P26/A06 P27/A07 P30/A08 P31/A09 VSS P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P44/A20 VCC P45/A21 P46/A22 P47/A23 P70/INT0 (FPT-100P-M05) 4 RST P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK PA7/CS7 PA6/CS6 PA5/CS5 PA4/CS4 PA3/CS3 PA2/CS2 PA1/CS1 CS0 P95/SCK2 P94/SOT2 P93/SIN2 P92/SCK1 P91/SOT1 P90/SIN1 P86/SCK0 P85/SOT0 P84/SIN0 P83/TOT1 P82/TOT0 MB90610A Series 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/D15/AD15 P16/D14/AD14 P15/D13/AD13 P14/D12/AD12 P13/D11/AD11 P12/D10/AD10 P11/D09/AD09 P10/D08/AD08 D07/AD07 D06/AD06 D05/AD05 D04/AD04 D03/AD03 D02/AD02 D01/AD01 D00/AD00 VCC X1 X0 VSS (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ALE RD P55/WRL RST P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK PA7/CS7 PA6/CS6 PA5/CS5 PA4/CS4 PA3/CS3 PA2/CS2 PA1/CS1 CS0 P95/SCK2 P94/SOT2 P93/SIN2 P92/SCK1 P91/SOT1 P90/SIN1 P86/SCK0 P85/SOT0 P84/SIN0 P83/TOT1 P82/TOT0 HST MD2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P74/INT4/PPG0 P75/INT5/PPG1 P76/INT6/ATG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/INT7/TIN0 P81/TIN1 MD0 MD1 P20/A00 P21/A01 P22/A02 P23/A03 P24/A04 P25/A05 P26/A06 P27/A07 P30/A08 P31/A09 VSS P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P44/A20 VCC P45/A21 P46/A22 P47/A23 P70/INT0 P71/INT1 P72/INT2 P73/INT3 (FPT-100P-M06) 5 MB90610A Series ■ PIN DESCRIPTION Pin no. LQFP*1 QFP*2 80 81 82 83 83 to 90 Pin name X0 X1 85 to 92 D00 to D07 Circuit type A Crystal oscillator pins (Oscillator) K (TTL) AD00 to AD07 91 to 98 93 to 100 P10 to P17 99 100 1 to 6 1 to 8 General purpose I/O ports This applies in non-multiplexed mode with an 8-bit external data bus. P08 to D15 In non-multiplexed mode, the I/O pins for the upper 8 bits of the external data bus This applies when using a 16-bit external data bus. AD08 to AD15 In multiplexed mode, the I/O pins for the upper 8 bits of the external address/data bus. P20 to P27 B (CMOS) B (CMOS) 16 to 20 22 to 24 18 to 22 P40 to P47 24 to 26 B (CMOS) 27 to 30 P70 to P73 INT0 to INT3 General purpose I/O ports This applies in multiplexed mode. In non-multiplexed mode, the output pins for the lower 8 bits of the external address bus. 9 P30 to P37 10 12 to 17 A08 to A15 A16 to A23 6 K (TTL) A00 to A07 *1: FPT-100P-M05 *2: FPT-100P-M06 In non-multiplex mode, the I/O pins for the lower 8 bits of the external data bus. In multiplexed mode, the I/O pins for the lower 8 bits of the external address/data bus. 7 8 10 to 15 25 to 28 Function General purpose I/O ports This applies in multiplexed mode. In non-multiplexed mode, the output pins for the upper 8 bits of the external address bus. General purpose I/O ports This applies when the upper address control register specifies port operation. The output pins for A16 to 23 of the external address bus This applies when the upper address control register specifies address operation. H General purpose I/O ports (CMOS/H) This applies in all cases. External interrupt request input pins As the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless done intentionally. (Continued) MB90610A Series Pin no. LQFP*1 QFP*2 29 30 31 32 31 33 Pin name P74, P75 Circuit type Function H General purpose I/O ports (CMOS/H) This applies when the waveform outputs for PPG timers 0 to 1 are disabled. INT4, INT5 External interrupt request input pins As the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless done intentionally. PPG0, PPG1 Output pins for PPG timers 0 to 1 This applies when the waveform outputs for PPG timers 0 to 1 are enabled. P76 H General purpose I/O port (CMOS/H) This applies in all cases. INT6 H External interrupt request input pin (CMOS/H) As the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally. ATG Trigger input pin for the A/D converter As the input operates continuously when the A/D converter inputs are operating, output to the pin from other functions must be stopped unless done intentionally. 32 34 AVCC Power supply Power supply for the analog circuits Do not switch this power supply on/off unless a voltage greater than AVCC is applied to VCC. 33 35 AVRH Power supply Analog circuit reference voltage input Do not switch the voltage to this pin on/off unless a voltage greater than AVRH is applied to AVCC. 34 36 AVRL Power supply Analog circuit reference voltage input 35 37 AVSS Power supply Ground level for the analog circuits 36 to 39 41 to 44 38 to 41 P60 to P67 43 to 46 AN0 to AN7 45 47 *1: FPT-100P-M05 *2: FPT-100P-M06 P80 C (AD) Open-drain output ports This applies when port operation is specified in the analog input enable register. Analog input pins for the A/D converter This applies when analog input mode operation is specified in the analog input enable register. H General purpose I/O port (CMOS/H) This applies in all cases. INT7 External interrupt request input pin As the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally. TIN0 Event input pin for reload timer 0 As the input operates continuously when the reload timer is set to input operation, output to the pin from other functions must be stopped unless done intentionally. (Continued) 7 MB90610A Series Pin no. LQFP*1 QFP*2 46 48 Pin name P81 TIN1 Function D General purpose I/O port (CMOS/H) This applies in all cases. Event input pin for reload timer 1 As the input operates continuously when the reload timer is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 47, 48 49, 50 MD0, MD1 E Input pins for specifying an oprating mode (CMOS/H) Connect directly to VCC or VSS. 49 51 MD2 M Input pins for specifying an oprating mode (CMOS/H) Connect directly to VCC or VSS. 50 52 HST F Hardware standby input pin (CMOS/H) 51, 52 53, 54 P82, P83 D General purpose I/O ports (CMOS/H) This applies when output is disabled for reload timers 0 to 1. TOT0, TOT1 53 55 P84 SIN0 54 56 P85 SOT0 55 57 P86 SCK0 56 58 P90 SIN1 *1: FPT-100P-M05 *2: FPT-100P-M06 8 Circuit type Output pins for reload timers 0 to 1 This applies when output is enabled for reload timers 0 to 1. D General purpose I/O port (CMOS/H) This applies in all cases. Serial data input pin for UART0 As the input operates continuously when UART0 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. D General purpose I/O port (CMOS/H) This applies when serial data output is disabled for UART0. Serial data output pin for UART0 This applies when serial data output is enabled for UART0. D General purpose I/O port (CMOS/H) This applies when the UART0 clock output is disabled. Clock I/O pin for UART0 This applies when the UART0 clock output is enabled. As the input operates continuously when UART0 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. D General purpose I/O port (CMOS/H) This applies in all cases. Serial data input pin for UART1 As the input operates continuously when UART1 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. (Continued) MB90610A Series Pin no. LQFP*1 QFP*2 57 59 Pin name P91 Circuit type D General purpose I/O port (CMOS/H) This applies when serial data output is disabled for UART1. SOT1 58 60 P92 Serial data output pin for UART1 This applies when serial data output is enabled for UART1. D General purpose I/O port (CMOS/H) This applies when the UART1 clock output is disabled. SCK1 59 61 P93 Clock I/O pin for UART1 This applies when the UART1 clock output is enabled. As the input operates continuously when UART1 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. D General purpose I/O port (CMOS/H) This applies in all cases. SIN2 60 62 P94 Serial data input pin for UART2 As the input operates continuously when UART2 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. D General purpose I/O port (CMOS/H) This applies when serial data output is disabled for UART2. SOT2 61 63 P95 Serial data output pin for UART2 This applies when serial data output is enabled for UART2. D General purpose I/O port (CMOS/H) This applies when the UART2 clock output is disabled. SCK2 62 63 to 69 64 CS0 65 to 71 PA1 to PA7 Clock I/O pin for UART2 This applies when the UART2 clock output is enabled. As the input operates continuously when UART2 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. J (CMOS) Chip select pin for program ROM I (CMOS) General purpose I/O ports This applies for pins with chip select output disabled by the chip select control register. CS1 to CS7 70 72 P50 CLK *1: FPT-100P-M05 *2: FPT-100P-M06 Function Output pins for the chip select function This applies for pins with chip select output enabled by the chip select control register. I (CMOS) General purpose I/O port This applies when CLK output is enabled. CLK output pin (Continued) 9 MB90610A Series (Continued) Pin no. LQFP*1 QFP*2 71 73 Pin name P51 Circuit type L (TTL) RDY 72 74 P52 75 P53 I (CMOS) 76 P54 L (TTL) 77 RST 76 78 P55 I (CMOS) General purpose I/O port This applies in 8-bit external bus mode or when output is disabled for the WR pin. Write strobe output pin for the upper 8 bits of the data bus This applies in 16-bit external bus mode and when output is enabled for the WR pin. G External reset request input pin (CMOS/H) I (CMOS) General purpose I/O port This applies when output is disabled for the WR pin. Write strobe output pin for the lower 8 bits of the data bus This applies when output is enabled for the WR pin. WRL 77 79 RD J (CMOS) Read strobe output pin for the data bus 78 80 ALE J (CMOS) ALE (address latch enabling) output pin 21, 82 23, 84 VCC Power supply Power supply for the digital circuits 9, 40, 79 11, 42, 81 VSS Power supply Ground level for the digital circuits *1: FPT-100P-M05 *2: FPT-100P-M06 10 General purpose I/O port This applies when the hold function is disabled. Hold request input pin This applies when the hold function is enabled. WRH 75 General purpose I/O port This applies when the hold function is disabled. Hold acknowledge output pin This applies when the hold function is enabled. HRQ 74 General purpose I/O port This applies when the external ready function is disabled. Ready input pin This applies when the external ready function is enabled. HAK 73 Function MB90610A Series ■ I/O CIRCUIT TYPE Type A Circuit Remarks X1 Clock input • Max. 3 to 32 MHz • Oscillator feedback resistance: approximately 1 MΩ X0 Standby control B Digital output R • CMOS level I/O With standby control Digital output Digital input Standby control C R Digital output • N-channel open drain output • CMOS level hysteresis input With AD control A/D input Digital input A/D Disable D Digital output R • CMOS level output • CMOS level hysteresis input With standby control Digital output Digital input Standby control Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in the standby state. (Continued) 11 MB90610A Series Type Circuit Remarks E • CMOS level input No standby control R Digital input F • CMOS level hysteresis input No standby control R Digital input G • CMOS level hysteresis input No standby control • With pull-up R Digital input H Digital output R • CMOS level output • CMOS level hysteresis input No standby control Digital output Digital input I Standby control • CMOS level I/O • Pull-up resistor approximately 50 kΩ • Pin goes to high impedance during stop mode. Digital output R Digital output Digital input Standby control Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in the standby state. (Continued) 12 MB90610A Series (Continued) Type Circuit Remarks J Standby control • CMOS level output • Pull-up resistor approximately 50 kΩ • Pin goes to high impedance during stop mode. Digital output Digital output K Digital output • CMOS level output • TTL level input With standby control Digital output R Digital input Standby control L Standby control Digital output • • • • CMOS level output TTL level input Pull-up resistor approximately 50 kΩ Pin goes to high impedance during stop mode. Digital output R Digital input Standby control M • CMOS level input No standby control R Digital input Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in the standby state. 13 MB90610A Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if the voltage applied between VCC and VSS exceeds the rating. If latchup occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation. For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage. 2. Treatment of Unused Pins Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins. 3. External Reset Input To reliably reset the controller by inputting an “L” level to the RST pin, ensure that the “L” level is applied for at least five machine cycles. Take particular note when using an external clock input. 4. VCC and VSS Pins Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins. 5. Cautions When Using an External Clock Drive the X0 pin only when using an external clock. • Using an External Clock MB90610A Series X0 OPEN X1 6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs Always cut the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before disconnecting the digital power supply (VCC). When turning the power on or off, ensure that AVRH does not exceed AVCC. Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC. 14 MB90610A Series ■ BLOCK DIAGRAM X0, 1 RST HST MD0 to MD2 7 CPU F2MC-16L family core Clock control circuit Interrupt controller RAM 8/16-bit PPG (output switching) × 1channel Communication prescaler PPG0 PPG1 3 AVcc AVRH, AVRL AVss ATG AN0 to AN7 A00 to A23 D00 to D15 ALE RD WRL, WRH HRQ HAK RDY CLK 3 3 UART F2MC-16 bus SIN0 to SIN2 SOT0 to SOT2 SCK0 to SCK2 2 A/D converter (8/10-bit) 8 8 24 IRT0 to IRT7 External interrupts 16 2 2 Reload timer External bus Interface 2 TIT0, TIT1 TOT0, TOT1 8 Chip select outputs CS0 to CS7 I/O ports 8 8 8 8 6 8 7 7 6 7 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P55 P60 to P67 P70 to P76 P80 to P86 P90 to P95 PA1 to PA7 15 MB90610A Series ■ F2MC-16L CPU PROGRAMMING MODEL • Dedicated Registers AH AL Accumulator USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bits 16 bits 32 bits • General-purpose Registers 32 banks (max.) R7 R6 RW7 R5 R4 RW6 R3 R2 RW5 R1 R0 RW4 RL3 RL2 RW3 RL1 RW2 RW1 RL0 RW0 000180H + RP × 10H → 16 bits • Processor States (PS) ILM RP I S T N CCR 16 Z V C MB90610A Series ■ MEMORY MAP External ROM/External bus FFFFFFH 002000H Address 3# 000380H RAM Registers 000180H 000100H 0000C0H Peripherals 000000H : Internal Type : External : No access Address #3 MB90611A 000500H MB90613A 000D00H 17 MB90610A Series ■ I/O MAP Address Register Name Access — *3 000000H Free 000001H Port 1 data register PDR1 000002H Port 2 data register 000003H Resource name Initial value — — R/W* *8 Port 1 XXXXXXXX PDR2 R/W* Port 2*7 XXXXXXXX Port 3 data register PDR3 R/W* Port 3*7 XXXXXXXX 000004H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 000005H Port 5 data register PDR5 R/W Port 5 – – XXXXXX 000006H Port 6 data register PDR6 R/W Port 6 11111111 000007H Port 7 data register PDR7 R/W Port 7 – XXXXXXX 000008H Port 8 data register PDR8 R/W Port 8 – XXXXXXX 000009H Port 9 data register PDR9 R/W Port 9 – – XXXXXX 00000AH Port A data register PDRA R/W Port A XXXXXXX – 00000BH to 10H Vacancy 000011H Port 1 direction register DDR1 R/W* Port 1*8 00000000 000012H Port 2 direction register DDR2 R/W* *7 Port 2 00000000 000013H Port 3 direction register DDR3 R/W* Port 3*7 00000000 000014H Port 4 direction register DDR4 R/W Port 4 00000000 000015H Port 5 direction register DDR5 R/W Port 5 ––000000 000016H Analog input enable register ADER R/W Port 6 11111111 000017H Port 7 direction register DDR7 R/W Port 7 –0000000 000018H Port 8 direction register DDR8 R/W Port 8 –0000000 000019H Port 9 direction register DDR9 R/W Port 9 ––000000 00001AH Port A direction register DDRA R/W Port A 0000000– 00001BH to 1FH Vacancy 000020H Serial mode register 0 SMR0 R/W! 000021H Serial control register 0 SCR0 R/W! — — *3 *3 — — — — 00000000 00000100 UART0 (SCI) 000022H Serial input data register 0/ Serial output data register 0 SIDR0/ SODR0 R/W 000023H Serial status register 0 SSR0 R/W! 00001–00 000024H Serial mode register 1 SMR1 R/W! 00000000 000025H Serial control register 1 SCR1 R/W! 00000100 000026H Serial input data register 1/ Serial output data register 1 SIDR1/ SODR1 R/W 000027H Serial status register 1 SSR1 R/W! UART1 (SCI) XXXXXXXX XXXXXXXX 00001–00 (Continued) 18 MB90610A Series Address Register Name Access 000028H Interrupt/DTP enable register ENIR R/W 000029H Interrupt/DTP request register EIRR R/W Interrupt level setting register ELVR R/W AD control status register ADCS R/W! 00002AH 00002BH 00002CH 00002DH 00002EH Resource name Initial value 00000000 DTP/external interrupt 00000000 00000000 00000000 00000000 A/D converter 00000000 XXXXXXXX AD data register ADCR R/W! *4 000030H PPG0 operation mode control register PPGC0 R/W PPG0 000000–1 000031H PPG1 operation mode control register PPGC1 R/W PPG1 000000–1 00002FH 000032H, Vacancy 33H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH — 0 0 0 0 0 0XX *3 — PPG0 reload register PRL0 R/W PPG0 PPG1 reload register PRL1 R/W PPG1 Control status register TMCSR0 R/W! TMR0/ TMRLR0 R/W Control status register TMCSR1 R/W! 16-bit timer register/ 16-bit reload register XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 16-bit reload timer 0 16-bit timer register/ 16-bit reload register R/W — *3 000040H to 43H Vacancy 000044H Serial mode register 2 SMR2 R/W! 000045H Serial control register 2 SCR2 R/W! ––––0000 XXXXXXXX XXXXXXXX 00000000 16-bit reload timer 1 TMR1/ TMRLR1 — ––––0000 XXXXXXXX XXXXXXXX — — 00000000 00000100 UART2 (SCI) 000046H Serial input data register 2/ Serial output data register 2 SIDR2/ SODR2 R/W 000047H Serial status register 2 SSR2 R/W! 00001–00 000048H CS control register 0 CSCR0 R/W ––––0000 000049H CS control register 1 CSCR1 R/W 00004AH CS control register 2 CSCR2 R/W 00004BH CS control register 3 CSCR3 R/W Chip select function XXXXXXXX ––––0000 ––––0000 ––––0000 (Continued) 19 MB90610A Series Address Register Name Access*2 Resource name Initial value 00004CH CS control register 4 CSCR4 R/W 00004DH CS control register 5 CSCR5 R/W 00004EH CS control register 6 CSCR6 R/W 00004FH CS control register 7 CSCR7 R/W 000050H Vacancy 000051H UART0 (SCI) machine clock division CDCR0 control register W 000052H Vacancy *3 000053H UART1 (SCI) machine clock division CDCR1 control register W 000054H Vacancy *3 000055H UART2 (SCI) machine clock division CDCR2 control register W 000056H to 8FH Vacancy — *3 — — 000090H to 9EH Reserved system area — *1 — — 00009FH Delayed interrupt generate/ release register DIRR R/W Delayed interrupt generation module –––––––0 0000A0H Low power consumption mode control register LPMCR R/W! Low power consumption 00011000 0000A1H Clock selection register CKSCR R/W! Low power consumption 11111100 0000A2H to A4H Vacancy 0000A5H — — — *3 ––––0000 Chip select function ––––0000 ––––0000 ––––0000 — UART0 (SCI) — UART1 (SCI) — UART2 (SCI) ––––1111 — ––––1111 — ––––1111 — *3 Auto-ready function selection register ARSR W External pins 0011––00 0000A6H External address output control register HACR W External pins 00000000 0000A7H Bus control signal selection register ECSR W External pins –000*000 0000A8H Watchdog timer control register WDTC R/W! Watchdog timer XXXXX 1 1 1 0000A9H Timebase timer control register TBTC R/W! Timebase timer 1––00100 0000AAH to AFH Vacancy 0000B0H Interrupt control register 00 ICR00 R/W! 00000111 0000B1H Interrupt control register 01 ICR01 R/W! 00000111 0000B2H Interrupt control register 02 ICR02 R/W! 0000B3H Interrupt control register 03 ICR03 R/W! 0000B4H Interrupt control register 04 ICR04 R/W! 00000111 0000B5H Interrupt control register 05 ICR05 R/W! 00000111 — *3 — — — Interrupt controller — — 00000111 00000111 (Continued) 20 MB90610A Series (Continued) Address Register Name Access Resource name Initial value 0000B6H Interrupt control register 06 ICR06 R/W! 00000111 0000B7H Interrupt control register 07 ICR07 R/W! 00000111 0000B8H Interrupt control register 08 ICR08 R/W! 00000111 0000B9H Interrupt control register 09 ICR09 R/W! 00000111 0000BAH Interrupt control register 10 ICR10 R/W! 0000BBH Interrupt control register 11 ICR11 R/W! 0000BCH Interrupt control register 12 ICR12 R/W! 00000111 0000BDH Interrupt control register 13 ICR13 R/W! 00000111 0000BEH Interrupt control register 14 ICR14 R/W! 00000111 0000BFH Interrupt control register 15 ICR15 R/W! 00000111 0000C0H to FFH External area *2 — — Interrupt controller 00000111 00000111 — — Initial values 0 : The initial value for this bit is “0”. 1 : The initial value for this bit is “1”. * : The initial value for this bit is “1” or “0”. (Determined by the level of the MD0 to MD2 pins.) X : The initial value for this bit is undefined. – : This bit is not used. The initial value is undefined. *1: Access prohibited. *2: This is the only external access area in the area below address 0000FFH. Access this address as an external I/O area. *3: Areas marked as “free” in the I/O map are reserved areas. These areas are accessed by internal access. No access signals are output on the external bus. *4: Only bit 15 can be written. The other bits are written to by the test function. Reading bits 10 to 15 returns zeros. *5: The R/W! symbol in the Read/Write column indicates that some bits are read-only or write-only. See the resource’s register list for details. *6: Using a read-modify-write instruction (such as the bit set instruction) to access one of the registers indicated by R/W!, R/W*, or W in the Read/Write column sets the specified bit to the desired value. However, this can cause misoperation if the other register bits include write-only bits. Therefore, do not use read-modify-write instructions to access these registers. *7: This register is only available when the address/data bus is in multiplex mode. Access to the register is prohibited in non-multiplex mode. *8: This register is only available when the external data bus is in 8-bit mode. Access to the register is prohibited in 16-bit mode. Note: The initial values listed for write-only bits are the initial values set by a reset. They are not the values returned by a read. Also, LPMCR/CKSCR/WDTC are sometimes initialized and sometimes not initialized, depending on the reset type. The listed initial values are for when these registers are initialized. 21 MB90610A Series ■ INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO INTERRUPT SOURCES Interrupt source I2OS support Interrupt vector Number Interrupt control register Address ICR Address Reset × #08 08H FFFFDCH — — INT 9 instruction × #09 09H FFFFD8H — — Exception × #10 0AH FFFFD4H — — External interrupt #0 #11 0BH FFFFD0H ICR00 0000B0H External interrupt #1 #13 0DH FFFFC8H ICR01 0000B1H External interrupt #2 #15 0FH FFFFC0H ICR02 0000B2H External interrupt #3 #17 11H FFFFB8H ICR03 0000B3H External interrupt #4 #19 13H FFFFB0H ICR04 0000B4H External interrupt #5 #21 15H FFFFA8H ICR05 0000B5H External interrupt #6 #23 17H FFFFA0H ICR06 0000B6H UART0 • transmit complete #24 18H FFFF9CH External interrupt #7 #25 19H FFFF98H ICR07 0000B7H UART1 • transmit complete #26 1AH FFFF94H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH PPG #0 × #27 1BH FFFF90H PPG #1 × #28 1CH FFFF8CH 16-bit reload timer #0 #29 1DH FFFF88H 16-bit reload timer #1 #30 1EH FFFF84H A/DC measurement complete #31 1FH FFFF80H UART2 • transmit complete #33 21H FFFF78H #34 22H FFFF74H UART2 • receive complete #35 23H FFFF70H ICR12 0000BCH UART1 • receive complete #37 25H FFFF68H ICR13 0000BDH UART0 • receive complete #39 27H FFFF60H ICR14 0000BEH #42 2AH FFFF54H ICR15 0000BFH Timebase timer interval interrupt Delayed interrupt generation module × × : indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (no stop request). : indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (with stop request). × : indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal. Note: Do not specify I2OS activation in interrupt control registers that do not support I2OS. 22 MB90610A Series ■ PERIPHERAL RESOURCES 1. Parallel Port The MB90610A series has 58 I/O pins, 18 output pins, and 8 open drain output pins. Ports 1 to 5 and ports 7 to A are I/O ports. The ports are inputs when the corresponding direction register bit is “0” and outputs when the corresponding bit is “1”. Port 1 is only available when the external data bus is in 8-bit mode. Access is prohibited in 16-bit mode. Ports 2 and 3 are only available when the address/data bus is in multiplex mode. Access is prohibited in nonmultiplex mode. Port 6 is an open drain port. Port 6 pins can only be used as ports when the analog input enable register is “0”. (1) Register Configuration Port data register bit 15 14 13 12 11 10 9 8 Address : PDR1 000001H : PDR3 000003H : PDR5 000005H PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0 : PDR7 000007H : PDR9 000009H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write (X) (X) (X) (X) (X) (X) (X) (X) Initial value PDR× Port data register 7 6 5 4 3 2 1 0 bit Address : PDR2 000002H : PDR4 000004H : PDR6 000006H PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0 : PDR8 000008H : PDRA 00000AH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write (X) (X) (X) (X) (X) (X) (X) (X) Initial value PDR× Notes: No register bits are provided for bit 6 to 7 of port 5. No register bit is provided for bit 7 of port 7. No register bit is provided for bit 7 of port 8. No register bits are provided for bits 6 to 7 of port 9. No register bit is provided for bit 0 of port A. Port direction register bit Address : DDR1 000011H : DDR3 000013H : DDR5 000015H : DDR7 000017H : DDR9 000019H Read/write Initial value Port direction register bit Address : DDR2 000012H : DDR4 000014H : DDR8 000018H : DDRA 00001AH Read/write Initial value 15 14 13 12 11 10 9 8 DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0 DDR× (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0 DDR× (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 23 MB90610A Series Note: No register bits are provided for bit 6 to 7 of port 5. No register bit is provided for bit 7 of port 7. No register bit is provided for bit 7 of port 8. No register bits are provided for bits 6 to 7 of port 9. No register bit is provided for bit 0 of port A. Port 6 does not have a DDR. Analog input enable register ADER 000016H bit 15 14 13 12 11 10 9 8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 ADER (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) Read/write Initial value (2) Register Details • Port Data Registers Port data register bit 15 14 13 12 11 10 9 8 Address : PDR1 000001H : PDR3 000003H : PDR5 000005H PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0 : PDR7 000007H : PDR9 000009H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write (X) (X) (X) (X) (X) (X) (X) (X) Initial value Port data register Address : PDR2 000002H : PDR4 000004H : PDR6 000006H : PDR8 000008H : PDRA 00000AH Read/write Initial value bit 7 6 5 4 3 2 1 PDR× 0 PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0 PDR× (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Note: No register bits are provided for bit 6 to 7 of port 5. No register bit is provided for bit 7 of port 7. No register bit is provided for bit 7 of port 8. No register bits are provided for bits 6 to 7 of port 9. No register bit is provided for bit 0 of port A. Port 1 is only available when the external data bus is in 8-bit mode. Access is prohibited in 16-bit mode. Ports 2, 3 are only available in multiplex mode. Access is prohibited in non-multiplex mode. 24 MB90610A Series • Port Direction Registers Port direction register bit Address : DDR1 000011H : DDR3 000013H : DDR5 000015H : DDR7 000017H : DDR9 000019H Read/write Initial value Port direction register bit Address : DDR2 000012H : DDR4 000014H : DDR8 000018H : DDRA 00001AH Read/write Initial value 15 14 13 12 11 10 9 8 DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0 DDR× (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0 DDR× (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) When pins are used as ports, the register bits control the corresponding pins as follows. 0: Input mode 1: Output mode Bits are set to “0” by a reset. Note: No register bits are provided for bit 6 to 7 of port 5. No register bit is provided for bit 7 of port 7. No register bit is provided for bit 7 of port 8. No register bit is provided for bit 0 of port A. No register bits are provided for bits 6 to 7 of port 9. Port 6 does not have a DDR. Port 1 is only available when the external data bus is in 8-bit mode. Access is prohibited in 16-bit mode. Ports 2 and 3 are only available in multiplex mode. Access is prohibited in non-multiplex mode. • Analog Input Enable Register bit Analog input enable register ADER 000016H Read/write Initial value 15 14 13 12 11 10 9 8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 ADER (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) Controls each pin of port 6 as follows. 0: Port input mode 1: Analog input mode Bits are set to “1” by a reset. Note: Inputting an intermediate level signal in port input mode causes an input leak current to flow. Therefore, set to analog input mode when applying an analog input. 25 MB90610A Series (3) Block Diagrams • I/O Port Internal data bus Data register read Data register Pin Data register write Direction register Direction register write Direction register read • Open Drain Port (Also used as Analog Inputs) Internal data bus RMW (Read-modify-write instruction) Pin Data register read Data register Data register write ADER ADER register write ADER register read 26 MB90610A Series (4) Port Pin Allocation Ports 1, 2, 3, 4, and 5 on the MB90610A series share pins with the external bus. The pin functions are determined by the bus mode and register settings. Function Pin Non-multiplex mode Multiplex mode External address control External address control Enable (address) Disable (port) Enable (address) Disable (port) External bus width External bus width External bus width External bus width 8-bit 16-bit D07 to D00 AD07 to AD00 P17 to P10/ D15 to D08/ AD15 to AD08 8-bit 16-bit 8-bit D07 to D00 Port D15 to D08 16-bit 8-bit AD07 to AD00 D15 to D08 Port P27 to P20/ A07 to A00 A07 to A00 A07 to A00 P37 to P30/ A15 to A08 A15 to A08 A15 to A08 P47 to P40/ A23 to A16 A23 to A16 Port A15 to A08 AD15 to AD08 A15 to A08 AD15 to AD08 Port A23 to A16 Port P57/ALE ALE ALE RD RD RD P55/WRL WRL WRL P54/WRH 16-bit Port WRH Port WRH Port WRH Port P53/HRQ HRQ HRQ P52/HAK HAK HAK P51/RDY RDY RDY P50/CLK CLK CLK WRH Note: The upper address, WRL, WRH, HAK, HRQ, RDY, and CLK can be set for use as ports by function selection. 27 MB90610A Series 2. UART 0/1/2 (SCI) UART 0/1/2 are serial I/O ports that can be used for CLK asynchronous (start-stop synchronization) or CLK synchronous (I/O expansion serial) data transfer. The ports have the following features. • Full duplex, double buffered • Supports CLK asynchronous (start-stop synchronization) and CLK synchronous (I/O expansion serial) data transfer • Multi-processor mode support • Built-in dedicated baud rate generator CLK asynchronous: 62500/31250/19230/9615/4808/2404/1202 bps CLK synchronous: 2 M/1 M/500 K/250 K bps • Supports flexible baud rate setting using an external clock • Error detect function (parity, framing, and overrun) • NRZ type transmission signal • Intelligent I/O service support (1) Register Configuration Serial mode register Address : channel 0 000020H : channel 1 000024H : channel 2 000044H bit MD1 Read/write Initial value Serial control register Address : channel 0 000021H : channel 1 000025H : channel 2 000045H Read/write Initial value 28 4 3 2 1 0 CS1 CS0 – SCKE SOE (R/W) (R/W) (0) (0) (W) (0) (W) (0) (W) (0) (–) (–) (R/W) (R/W) (0) (0) 15 14 P 13 SBL 12 CL 11 A/D 10 REC 9 RXE SMR 8 TXE SCR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (1) (0) (0) bit 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 SIDR (read) SODR (write) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit Read/write Initial value Machine clock division control register Address : channel 0 000051H : channel 1 000053H : channel 2 000055H 5 CS2 PEN Read/write Initial value Serial status register Address : channel 0 000023H : channel 1 000027H : channel 2 000047H 6 MD0 bit Read/write Initial value Input data register/ Output data register Address : channel 0 000022H : channel 1 000026H : channel 2 000046H 7 15 14 PE ORE (R) (0) (R) (0) bit 15 13 12 11 FRE RDRF TDRE (R) (0) 14 (R) (0) 13 (R) (1) 12 – – – – (–) (–) (–) (–) (–) (–) (–) (–) 10 – RIE (–) (–) 11 9 8 TIE SSR (R/W) (R/W) (0) (0) 10 9 8 DIV3 DIV1 DIV1 DIV0 (W) (1) (W) (1) (W) (1) (W) (1) CDCR MB90610A Series (2) Block Diagram Control signals Receive interrupt (to CPU) Dedicated baud rate generator SCK 16-bit timer 0 (Internal connection) Transmit interrupt (to CPU) Transmit clock Clock select circuit Receive clock External clock SIN Receive control circuit Transmit control circuit Start bit detect circuit Transmit start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter SOT Receive status evaluation circuit Receive error indication signal for EI2OS (to CPU) Receive shifter Transmit shifter Receive complete Transmit start SODR SIDR F2MC-16 bus SMR register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR register PEN P SBL CL A/D REC RXE TXE SSR register PE ORE FRE RDRF TDRE RIE TIE Control signals 29 MB90610A Series 3. 10-bit 8-input A/D Converter (With 8-bit Resolution Mode) The 10-bit 8-input A/D converter converts analog input voltages to digital values. The A/D converter has the following features. • Conversion time: Minimum of 6.13 µs per channel (98 machine cycles/16 MHz machine clock. This includes the sample and hold time) • Sample and hold time: Minimum of 3.75 µs per channel (60 machine cycles/16 MHz machine clock) • Uses RC-type successive approximation conversion with a sample and hold circuit. • 10-bit or 8-bit resolution • Eight program-selectable analog input channels Single conversion mode : Selectively convert a one channel. Scan conversion mode : Continuously convert multiple channels. Maximum of 8 program-selectable channels. Continuous conversion mode : Repeatedly convert specified channels. Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) • An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable for continuous operation. • Activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) Register Configuration bit 15 14 A/D control status register (upper) BUSY INT Address : 00002DH bit A/D control status register (lower) Address : 00002CH bit Read/write Initial value Read/write Initial value 30 11 10 7 MD1 6 9 INTE PAUS STS1 STS0 STRT 5 4 3 2 8 Reserved (W) (0) (–) (0) 1 0 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCS1 ADCS0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Read/write Initial value A/D data register (lower) Address : 00002FH 12 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) Read/write Initial value A/D data register (upper) Address : 00002EH 13 bit 15 14 13 12 11 10 9 8 S10 – – – – – D9 D8 (R/W) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (X) (R) (X) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) ADCR1 ADCR0 MB90610A Series (2) Block Diagram AVCC AVRH AVRL AVSS D/A converter MPX Successive approximation register Input circuit AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Comparator Decoder Data bus Sample and hold circuit Data register ADCR A/D control register 1 A/D control register 2 ADCS ATG Trigger activation Timer (Reload timer 1 output) φ Timer activation Operating clock Prescaler 31 MB90610A Series 4. 8/16-bit PPG This block contains the 8-bit reload timer module. The block performs PPG output in which the pulse output is controlled by the operation of the timer. The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. The PPG has the following functions. • 8-bit PPG output in 2-channel independent operation mode: Two independent PPG output channels are available. • 16-bit PPG output operation mode : One 16-bit PPG output channel is available. • 8+8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to channel 1. • PPG output operation: Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction with an external circuit. (1) Register Configuration bit PPG0 operation mode control register Address : channel 0 000030H 7 6 PEN0 — 5 4 3 2 1 0 POE0 PIE0 PUF0 PCM1 PCM0 Reserved (R/W) (—) (R/W) (R/W) (R/W) (R/W) (R/W) (—) (0) (0) (0) (0) (0) (0) (0) (1) Read/write Initial value bit PPG1 operation mode control register Address : channel 1 000031H 15 14 13 12 11 10 PEN1 PCS1 POE1 PIE1 PUF1 MD1 9 8 MD0 Reserved bit 15 14 13 12 11 10 9 8 Reload register H Address : channel 0 000035H : channel 1 000037H PRLH0, 1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Read/write Initial value bit 7 6 5 4 3 2 1 0 Reload register L Address : channel 0 000034H : channel 1 000036H 32 PPGC1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (—) (0) (0) (0) (0) (0) (0) (0) (1) Read/write Initial value Read/write Initial value PPGC0 PRLL0, 1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) MB90610A Series (2) Block Diagram • 8/16-bit PPG (channel 0) Output enable PPG0 Peripheral clock divided by 16 Peripheral clock divided by 4 Peripheral clock PPG0 output latch Invert Clear PEN0 Count clock selection Timebase counter output Main clock divided by 512 S R Q PCNT (down-counter) IRQ Reload ch.1 borrow L/H select L/H selector PRLL0 PRLBH0 PIE 0 PRLH0 PUF0 L-side data bus H-side data bus PPGC0 (Operation mode control) 33 MB90610A Series • 8/16-bit PPG (channel 1) Output enable PPG1 Peripheral clock PPG1 output latch Invert Count clock selection Clear PEN1 channel 0 borrow Timebase counter output Main clock divided by 512 S R Q PCNT (down-counter) IRQ Reload L/H select L/H selector PRLL1 PRLBH1 PIE1 PRLH1 PUF1 L-side data bus H-side data bus PPGC1 (Operation mode control) 34 MB90610A Series 5. 16-bit Reload Timer (with Event Count Function) The 16-bit reload timers consists of a 16-bit down-counter, a 16-bit reload register, one input (TIN) and one output (TOT) pin, and a control register. The input clock can be selected from one external clock and three types of internal clock. The output pin (TOT) outputs a toggle waveform in reload mode and a rectangular waveform during counting in one-shot mode. The input pin (TIN) functions as the event input in event count mode and as the trigger input or gate input in internal clock mode. This product has two internal 16-bit reload timer channels. (1) Register Configuration Timer control status register (upper) Address : channel 0 000039H : channel 1 00003DH Read/write Initial value bit Timer control status register (lower) Address : channel 0 000038H : channel 1 00003CH bit Read/write Initial value 14 13 — — — (—) (—) (—) (—) (—) (—) 7 6 12 — 11 10 9 8 CSL1 CSL2 MOD2 MOD1 (—) (R/W) (R/W) (R/W) (R/W) (—) (0) (0) (0) (0) 5 4 3 MOD0 OUTE OUTL RELD INTE 2 UF 1 0 CNTE TRG TMCSR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 16-bit timer register (upper)/ 16-bit reload register (upper) Address : channel 0 00003BH : channel 1 00003FH Read/write Initial value bit 16-bit timer register (lower)/ 16-bit reload register (lower) Address : channel 0 00003AH : channel 1 00003EH bit Read/write Initial value 15 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) TMR/ TMRLR 35 MB90610A Series (2) Block Diagram 16 16-bit reload register 8 Reload RELD 16-bit down-counter OUTE UF 16 OUTL F2MC-16 bus 2 OUT CTL GATE INTE UF Clock selector CNTE CSL0 TRG IN CTL Port (TIN) EXCK φ φ φ — — — 21 23 25 Output enable 3 Prescaler Clear Port (TOUT) MOD2 MOD1 Peripheral clock MOD0 3 Clear I2OSCLR Re-trigger 2 36 IRQ CSL1 Serial baud rate A/DC MB90610A Series 6. Chip Select Function This module generates chip select signals to simplify connection of memory or I/O devices. The module has 8 chip select output pins. The hardware outputs the chip select signals from the pins when it detects access of an address in the areas specified in the pin registers. (1) Register Configuration Address : : : : 000049H 00004BH 00004DH 00004FH bit Address : : : : 000048H 00004AH 00004CH 00004EH bit 15 14 13 12 — — — — 7 6 5 4 — — — — 11 10 9 8 ACTL OPEL CSA1 CSA0 3 2 1 Chip select control register (odd numbers: CSCR1/3/5/7) 0 ACTL OPEL CSA1 CSA0 Chip select control register (even numbers: CSCR0/2/4/6) (2) Block Diagram Address (from CPU) A23 A16 A15 A08 A07 Address decoder A00 Address decoder Decode signal Program area Decode CS0 (For the program ROM area) Chip select control register 0 Selection setting Selector Chip select control register 1 Selection setting Selector CS1 Chip select control register 6 Selection setting Selector CS6 Chip select control register 7 Selection setting Selector CS7 37 MB90610A Series 7. DTP/External Interrupts The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16L CPU to activate the extended intelligent I/O service or interrupt processing. Two request levels (“H” and “L”) are provided for extended intelligent I/O service. For external interrupt requests, generation of interrupts on a rising or falling edge as well as on “H”, “L” levels can be selected, giving a total of four types. (1) Register Configuration bit Interrupt/DTP enable register Address : 000028H 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Read/write Initial value bit 15 Interrupt/DTP register Address : 000029H ER7 14 13 12 11 10 9 8 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EIRR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Read/write Initial value bit 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Request level setting register (upper) Address : 00002BH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Read/write Initial value bit Request level setting register (lower) Address : 00002AH Read/write Initial value ENIR 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 ELVR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (2) Block Diagram F2MC-16 bus 8 Interrupt input 8 8 8 38 Interrupt/DTP enable register Gate Request F/F Interrupt/DTP register Request level setting register Edge detect circuit 8 Request input MB90610A Series 8. Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to the F2MC-16L CPU can be generated and cleared by software using this module. (1) Register Configuration Delayed interrupt generate/ bit clear decoder Address : 00009FH Read/write Initial value 15 14 13 12 11 10 9 8 — — — — — — — R0 (—) (—) (—) (—) (—) (—) (—) (—) (—) (—) (—) (—) DIRR (—) (R/W) (—) (0) (2) Block Diagram F2MC-16 bus Delayed interrupt generate/clear decoder Interrupt latch 39 MB90610A Series 9. Watchdog Timer and Timebase Timer Functions The watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller. The watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source. In addition to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. The timebase timer uses the main clock, regardless of the value of the MCS bit in the CKSCR register. (1) Register Configuration bit Watchdog timer control register Address : 0000A8H 7 6 5 4 3 2 1 PONR STBR WRST ERST SRST WTE WT1 Read/write Initial value Timebase timer control register Address : 0000A9H Read/write Initial value 0 WT0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (W) (1) (W) (1) (W) (1) bit 15 14 13 12 11 10 9 8 Reserved — — (—) (1) (—) (—) TBIE TBOF TBR TBC1 TBC0 (—) (R/W) (R/W) (—) (0) (0) (W) (1) WDTC TBTC (R/W) (R/W) (0) (0) (2) Block Diagram Main clock (OSC oscillator) TBTC TBC1 Selector TBC0 Clock input 212 214 Timebase timer 216 219 212 214 216 219 TBTRES TBR TBIE AND Q S R F2MC-16 bus TBOF Timebase interrupt WDTC WT1 Selector WT0 2-bit counter OF CLR Watchdog reset activation circuit CLR WDGRST To internal reset activation circuit WTE PONR From power-on detection STBR From hardware standby control circuit WRST 40 ERST RST pin SRST From the RST bit of the STBYC register MB90610A Series 10. Low Power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization Delay Time, and Clock Multiplier Function) The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode, main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are classified as low power consumption modes. In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock). The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the operating clock. In PLL sleep mode and main sleep mode, the CPU's operating clock only is stopped and other elements continue to operate. In timer mode, only the timebase timer operates. Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum power consumption. The CPU intermittent operation function provides an intermittent clock to the CPU when register, internal memory, internal resource, or external bus access is performed. This function reduces power consumption by lowering the CPU execution speed while still providing a high-speed clock to internal resources. The PLL clock multiplier ratio can be set to 1, 2, 3, 4 by the CS1, 0 bits. The WS1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop mode or hardware standby mode. (1) Register Configuration bit Low power consumption mode control register Address : 0000A0H Read/write Initial value bit Clock select register Address : 0000A1H Read/write Initial value 7 6 5 4 3 2 1 0 STP SLP SPL RST Reserved CG1 CG0 Reserved (W) (0) (W) (0) (R/W) (0) (W) (1) 15 14 13 12 Reserved (—) (1) MCM WS1 WS0 (R) (1) LPMCR (—) (R/W) (R/W) (—) (1) (0) (0) (0) 11 10 9 8 Reserved MCS CS1 CS0 CKSCR (R/W) (R/W) (—) (R/W) (R/W) (R/W) (1) (1) (1) (1) (0) (0) 41 MB90610A Series (2) Block Diagram CKSCR MCM MCS PLL multiplier circuit 1 2 3 4 Main clock (OSC oscillator) CPU clock 1/2 CPU clock generator CKSCR CS1 CS0 CPU clock selector 0/9/17/33 Intermittent cycle selection F2MC-16 bus LPMCR CG1 CG0 Cycle selection circuit for the CPU intermittent operation function LPMCR SLP Standby control circuit STP RST Release HST activate Peripheral clock generator Peripheral clock HST pin CKSCR WS1 WS0 Interrupt request or RST Oscillation stabilization delay time selector 24 213 215 218 Clock input Timebase clock Timebase timer 2 12 2 14 2 16 19 2 LPMCR SPL LPMCR RST Pin high impedance control circuit Pin Hi-Z Internal reset generation circuit Internal RST RST pin To watchdog timer WDGRST 42 MB90610A Series • State Transition Diagram for Clock Selection Power-on Main MCS = 1 MCM = 1 CS1/0 = XX (1) Main → PLLX MCS = 0 MCM = 1 (6) CS1/0 = XX (2) (3) (7) PLL1 → Main MCS = 1 MCM = 0 CS1/0 = 00 PLL multiplier = 1 MCS = 0 MCM = 0 (4) (6) CS1/0 = 00 PLL2 → Main MCS = 1 MCM = 0 (7) CS1/0 = 01 PLL multiplier = 2 MCS = 0 (6) MCM = 0 CS1/0 = 01 (7) PLL3 → Main (7) MCS = 1 MCM = 0 CS1/0 = 10 PLL4 → Main MCS = 1 MCM = 0 CS1/0 = 11 (1) (2) (3) (4) (5) (6) (7) PLL multiplier = 3 (5) MCS = 0 (6) (6) MCM = 0 CS1/0 = 10 PLL multiplier = 4 MCS = 0 MCM = 0 CS1/0 = 11 MCS bit cleared PLL clock oscillation stabilization delay complete and CS1/0 = “00” PLL clock oscillation stabilization delay complete and CS1/0 = “01” PLL clock oscillation stabilization delay complete and CS1/0 = “10” PLL clock oscillation stabilization delay complete and CS1/0 = “11” MCS bit set (including a hardware standby or watchdog reset) PLL clock and main clock synchronized timing 43 MB90610A Series 11. Interrupt Controller The interrupt control registers are located in the interrupt controller. An interrupt control register is provided for each I/O with an interrupt function. The registers have the following three functions. • Set the interrupt level of the corresponding peripheral. • Select whether to treat interrupts from the corresponding peripheral as standard interrupts or activate the extended intelligent I/O service. • Select the extended intelligent I/O service channel. (1) Register Configuration Interrupt control register Address : ICR01 0000B1H : ICR03 0000B3H : ICR05 0000B5H : ICR07 0000B7H : ICR09 0000B9H : ICR11 0000BBH : ICR13 0000BDH : ICR15 0000BFH bit Read/write Initial value 14 ICS3 ICS2 (W) (0) Read/write Initial value Interrupt control register Address : ICR00 0000B0H : ICR02 0000B2H : ICR04 0000B4H : ICR06 0000B6H : ICR08 0000B8H : ICR10 0000BAH : ICR12 0000BCH : ICR14 0000BEH 15 bit (W) (0) 7 6 (W) (0) 12 ICS1 ICS0 or or S1 S0 11 ISE 10 IL2 9 IL1 8 ICRxx IL0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (1) (1) (1) ICS3 ICS2 (W) (0) 13 5 4 ICS1 ICS0 or or S0 S1 3 ISE 2 IL2 1 IL1 0 IL0 ICRxx (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (1) (1) (1) Note: Do not access these registers using read-modify-write instructions as this can cause misoperation. 44 MB90610A Series (2) Block Diagram 4 4 I SE I L2 I L1 32 Determine priority of interrupt or I2OS IL0 Interrupt/ I2OS request (peripheral resource) 3 (CPU) Interrupt level I2OS selection 4 4 4 I CS1 I C S 0 I2OS vector selection 4 I2OS vector (CPU) F2MC-16 bus I CS3 I CS2 2 2 S1 S0 Detect I2OS completion condition 2 I2OS completion condition 45 MB90610A Series 12. External Bus Terminal Control Circuit This circuit controls the external bus terminals intended to extend outwardly the CPU’s address/data bus. (1) Register Configuration bit Register for selection of AUTO ready function Address : 0000A5H 15 14 13 12 IOR1 IOR0 HMR1 HMR0 Read/write Initial value bit Register for control of external address output Address : 0000A6H Read/write Initial value bit Register for selection of bus control signal Address : 0000A7H 10 — — 9 8 LMR1 LMR0 (W) (0) (W) (0) (W) (1) (W) (1) (—) (—) (—) (—) (W) (0) (W) (0) 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) 15 14 13 12 11 10 9 8 RYE CKE (W) (0) (W) (0) — Read/write Initial value 11 LMBS WRE HMBS IOBS HDE (—) (—) (W) (0) (W) (0) (W) (1/0) (W) (0) (W) (0) ARSR HACR ECSR (2) Block Diagram P5 P4 P5 P3 P2 P1 P1 data P1 direction RB Data control Access control Access control 46 Access control P1 MB90610A Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Rating (VSS = AVSS = 0.0 V) Parameter Symbol Rating Unit Min. Max. VSS – 0.3 VSS + 7.0 V AV * VSS – 0.3 VSS + 7.0 V AVRH*1 AVRL*1 VSS – 0.3 VSS + 7.0 V VI VSS – 0.3 VCC + 0.3 V VO VSS – 0.3 VCC + 0.3 V IOL — 15 mA IOLAV — 4 mA ΣIOL — 100 mA “L” level total average output current* ΣIOLAV — 50 mA “H” level maximum output current*3 IOH — –15 mA “H” level average output current*4 IOHAV — –4 mA “H” level total maximum output current ΣIOH — –100 mA “H” level total average output current*5 ΣIOHAV — –50 mA Power consumption Pd — +400 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C VCC CC 1 Power supply voltage Input voltage*2 Output voltage*2 “L” level maximum output current* 3 “L” level average output current*4 “L” level total maximum output current 5 Remarks *1: AVCC, AVRH, and AVRL must not exceed VCC. Similarly, it may not exceed AVRL, nor AVRH. *2: VI and VO must not exceed VCC + 0.3 V. *3: The maximum output current must not be exceeded at any individual pin. *4: The average output current is the rating for the current from an individual pin averaged over a duration of 100 ms. *5: The average total output current is the rating for the current from all pins averaged over a duration of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 47 MB90610A Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Power supply voltage VCC Operating temperature TA Rating Unit Remarks Min. Max. 2.7 5.5 V For normal operation 2.0 5.5 V To maintain statuses in stop mode –40 +85 °C WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 48 MB90610A Series 3. DC Characteristics (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter “H” level input voltage “L” level input voltage Symbol — — V VCC – 0.3 — — V — — 0.4 V — — 0.4 V — 30 — 100 kΩ VCC = +5.0 V±10% 16 MHz internal operation VCC = +3.0 V±10% 8 MHz internal operation VCC = +5.0 V±10% TA = 25°C — 50 70 mA — 25 30 mA — 10 20 mA — 5 10 mA — 0.1 10 µA — 10 — pF –10 — 10 µA VCC = +5.0 V±10% VCC = +3.0 V±10% — VIL VILS VILM “L” level output voltage VOL Rpu — VCC = +5.0 V±10% VCC = +3.0 V±10% VCC = +5.0 V±10% Other than P60 IOH = –4.0 mA to P67 VCC = +3.0 V±10% IOH = –1.6 mA VCC = +5.0 V±10% IOL = –4.0 mA All output pins VCC = +3.0 V±10% IOL = –2.0 mA RST, P50 to P55, RD, ALE, PA1 to PA7, CS0 ICC ICCS ICC VCC ICCS ICCH Input leakage current Leakage current for open drain outputs Pull-down resistance VCC – 0.5 VIHT VOH Input pin capacitance Max. VCC + 0.3 VCC + 0.3 VCC + 0.3 — — 0.3 VCC 0.2 VCC VSS + 0.3 0.8 0.2 VCC — “H” level output voltage Supply current Min. 0.7 VCC 0.8 VCC VCC – 0.3 2.2 0.7 VCC VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 Value Typ. — — — — — — — — — — Conditions VIH VIHS VIHM VILT Pull-up resistance Pin name Unit Remarks V V V V V V V V V V CIN Other than AVCC, AVSS, VCC,VSS IIL Other than P60 VCC = 5.5 V to P67 VSS < VI < VCC Ileak Other than P60 to P67 — — 0.1 10 µA Rpd MD2 — 40 — 200 kΩ — *1 *2 *2 *1 *2 *2 *1: Hysteresis input pins: RST, HST, P60 to P67, P70 to P76, P80 to P86, P90 to P95, PA1 to PA7 *2: TTL input pins: AD00/D00 to AD07/D07, AD08/D08/P10 to AD15/D15/P17, HRQ/P53, RDY/P51 49 MB90610A Series 4. AC Characteristics (1) Clock Timing • When VCC = +5.0 V±10% (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Clock frequency fC X0, X1 Clock cycle time tC Frequency variation ratio* (when locked) ∆f Input clock pulse width PWH PWL Input clock rise time and fall time tcr tcf Internal operating clock frequency fCP Internal operating clock cycle time tCP Parameter Conditions Value Unit Min. Max. — 3 32 MHz X0, X1 — 31.25 333 ns — — — 3 % X0 — 10 — ns X0 — — 5 ns — — 1.5 16 MHz — — 62.5 666 ns Remarks The duty ratio should be in the range 30 to 70% * : The frequency variation ratio is the maximum variation from the specified central frequency when the multiplier PLL is locked. The value is expressed as a proportion. ∆f = α f0 +α × 100 (%) Central frequency f0 -α • When VCC = +2.7 V (min.) (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Clock frequency fC X0, X1 Clock cycle time tC Input clock pulse width Parameter 50 Conditions Value Unit Min. Max. — 3 16 MHz X0, X1 — 62.5 333 ns PWH PWL X0 — 20 — ns Input clock rise time and fall time tcr tcf X0 — — 5 ns Internal operating clock frequency fCP — — 1.5 8 MHz Internal operating clock cycle time tCP — — 125 666 ns Remarks The duty ratio should be in the range 30 to 70% MB90610A Series • Clock Timing tC 0.8 VCC 0.2 VCC PWH PWL tcf tcr • PLL Operation Assurance Range Relationship between the internal operating clock frequency and supply voltage Power supply VCC (V) Normal operation range 5.5 4.5 3.3 PLL operation assurance range 2.7 1.5 8 3 fCP (MHz) 16 Internal clock Relationship between the oscillation frequency and internal operating clock frequency 16 Multiply Multiply by 4 by 3 No multiplier Internal Clock fCP (MHz) Multiply by 2 Multiply by 1 12 9 8 4 3 4 8 16 24 32 Oscillation clock fC (MHz) Note: Low voltage operation down to 2.7V is also assured for the evaluation tools. 51 MB90610A Series The AC characteristics are for the following measurement reference voltages. • Input Signal Waveform • Output Signal Waveform Hysteresis input pins Output pins 0.8 VCC 2.4 V 0.2 VCC 0.8 V Other than hysteresis/MD input pins 0.7 VCC 0.3 VCC (2) Clock Output Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Cycle time tCYC CLK ↑ → CLK ↓ tCHCL Pin name CLK Conditions VCC = +5 V±10% Value Max. tCP — ns tCP/2 – 20 tCP/2 + 20 ns tCYC tCHCL 2.4 V CLK 52 2.4 V 0.8 V Unit Min. Remarks MB90610A Series (3) Recommended Resonator Manufacturers • Sample Application of Piezoelectric Resonator (FAR Family) X0 X1 R *1 FAR *2 *2 C1 C2 FAR part number Frequency Dumping (built-in capacitor type) (MHz) resistor *1: Fujitsu Acoustic Resonator Initial deviation of FAR frequency (TA = +25°C) Temperature Loading characteristics of FAR frequency capacitors*2 (TA = –20°C to +60°C) FAR-C4CC-02000-L20 2.00 1 kΩ ±0.5% ±0.5% FAR-C4CA-04000-M01 4.00 — ±0.5% ±0.5% FAR-C4CB-08000-M02 8.00 — ±0.5% ±0.5% FAR-C4CB-10000-M02 10.00 — ±0.5% ±0.5% FAR-C4CB-16000-M02 16.00 — ±0.5% ±0.5% Built-in Inquiry: FUJITSU LIMITED 53 MB90610A Series • Sample Application of Ceramic Resonator X0 X1 R *4 *1 C1 Resonator manufacturer*1 Kyocera Corporation Resonator KBR-2.0MS PBRC2.00A KBR-4.0MSA KBR-4.0MKS PBRC4.00A PBRC4.00B KBR-6.0MSA KBR-6.0MKS PBRC6.00A PBRC6.00B KBR-8.0M PBRC8.00A PBRC8.00B KBR-10.0M PBRC10.00B KBR-12.0M PBRC12.00B *2 C2 Frequency (MHz) 2.00 4.00 6.00 8.00 10.00 12.00 *3 C1 (pF)*2 C2 (pF)*3 R*4 150 150 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 33 Built-in 33 Built-in 33 Built-in 150 150 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 33 Built-in 33 Built-in 33 Built-in Not required Not required 680 Ω 680 Ω 680 Ω 680 Ω Not required Not required Not required Not required 560 Ω Not required Not required 330 Ω 680 Ω 330 Ω 680 Ω (Continued) 54 MB90610A Series (Continued) Resonator manufacturer*1 Murata Mfg. Co., Ltd. Resonator CSA2.00MG040 CST2.00MG040 CSA4.00MG040 CST4.00MGW040 CSA6.00MG CST6.00MGW CSA8.00MTZ CST8.00MTW CSA10.00MTZ CST10.00MTW CSA12.00MTZ CST12.00MTW CSA16.00MXZ040 CST16.00MXW0C3 CSA20.00MXZ040 CSA24.00MXZ040 CSA32.00MXZ040 Frequency (MHz) 2.00 4.00 6.00 8.00 10.00 12.00 16.00 20.00 24.00 32.00 C1 (pF)*2 C2 (pF)*3 R*4 100 Built-in 100 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in 15 Built-in 10 5 5 100 Built-in 100 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in 15 Built-in 10 5 5 Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Inquiry: Kyocera Corporation • AVX Corporation North American Sales Headquarters: TEL 1-803-448-9411 • AVX Limited European Sales Headquarters: TEL 44-1252-770000 • AVX/Kyocera H.K. Ltd. Asian Sales Headquarters: TEL 852-363-3303 Murata Mfg. Co., Ltd. • Murata Electronics North America, Inc.: TEL 1-404-436-1300 • Murata Europe Management GmbH: TEL 49-911-66870 • Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233 55 MB90610A Series (4) Reset and Hardware Standby Inputs (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name tRSTL RST Hardware standby input time tHSTL HST Parameter Reset input time Conditions — Value Unit Min. Max. 16 tCP — ns 16 tCP — ns tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC • Conditions for Measurement of AC Reference Pin CL: Load capacity during testing CL 56 For CLK and ALE, CL = 30 pF. For address and data buses (AD15 to AD00), RD and WR, CL = 80 pF. Remarks MB90610A Series (5) Power-on Reset (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Power supply rise time tR VCC Power supply cut-off time tOFF VCC Parameter Conditions — Value Unit Remarks Min. Max. — 30 ms * 1 — ms For repetition of the operation * : VCC should be lower than 0.2 V before power supply rise. Notes: • The above values are the values required for a power-on reset • When HST = “L”, this standard must be followed to turn on power supply for power-on reset whether or not necessary. • The device has built-in registers which are initialized only by power-on reset. For possible initialization of these registers, turn on power supply according to this standard. tR 2.7 V VCC 0.2 V 0.2 V tOFF Abrupt changes in the power supply voltage may cause a power-on reset. When changing the power supply voltage during operation, the change should be as smooth as possible, as shown in the following figure. Main power supply voltage Sub power supply voltage The gradient should be no more than 50mV/ms. VSS 57 MB90610A Series (6) Bus Timing (Read) (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter ALE pulse width Symbol Pin name tLHLL ALE Valid address → ALE ↓ time tAVLL Address ALE ↓ → address valid time tLLAX Address Valid address → RD ↓ time tAVRL RD, Address Valid address → valid data input tAVDV Address/ data RD pulse width tRLRH RD Conditions Value Min. 58 tRLDV Data Unit VCC = +5.0 V±10% tCP/2 – 20 — ns VCC = +3.0 V±10% tCP/2 – 35 — ns VCC = +5.0 V±10% tCP/2 – 20 — ns VCC = +3.0 V±10% tCP/2 – 40 — ns tCP/2 – 15 — ns tCP – 15 — ns VCC = +5.0 V±10% — 5 tCP/2 – 60 ns VCC = +3.0 V±10% — 5 tCP/2 – 80 ns — 3 tCP/2 – 20 — ns 3 tCP/2 – 60 ns 3 tCP/2 – 80 ns 0 — ns tCP/2 – 15 — ns tCP/2 – 10 — ns — VCC = +5.0 V±10% RD ↓ → valid data input Max. — VCC = +3.0 V±10% RD ↑ → data hold time tRHDX RD ↑ → ALE ↑ time tRHLH RD, ALE RD ↑ → address valid time tRHAX Address, RD Valid address → CLK ↑ time tAVCH Address, CLK tCP/2 – 20 — ns RD ↓ → CLK ↑ time RD, CLK tCP/2 – 20 — ns tRLCH — Remarks MB90610A Series tAVCH tRLCH 2.4 V CLK tLLAX tAVLL 2.4 V ALE 2.4 V tRHLH 2.4 V 0.8 V tLHLL 2.4 V tAVRL tRLRH 2.4 V RD 0.8 V Multiplex mode tRHAX 2.4 V 0.8 V A23 to A16 2.4 V 0.8 V tRLDV tAVDV 2.4 V Address 0.8 V tRHDX 2.4 V 2.2 V 0.8 V 0.8 V Read data 0.8 V Non-multiplex mode A23 to A00 tRHAX 2.4 V 0.8 V 2.4 V 0.8 V tAVDVtAVDV D15 to D00 2.2 V tRLDV tRHDX 2.2 V 0.8 V Read data 2.2 V 0.8 V 59 MB90610A Series (7) Bus Timing (Write) (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Valid address → WR ↓ time tAVWL Address WR pulse width tWLWH WRL, WRH Valid data output → WR ↑ time tDVWH Parameter Data WR ↑ → data hold time tWHDX WR ↑ → address valid time tWHAX Address WR ↑ → ALE ↑ time tWHLH ALE, WRL, WRH WR ↓ → CLK ↓ time tWLCL WRL, WRH, CLK Value Conditions Unit Min. Max. tCP – 15 — ns 3 tCP/2 – 20 — ns 3 tCP/2 – 20 — ns VCC = +5.0 V±10% 20 — ns VCC = +3.0 V±10% 30 — ns tCP/2 – 10 — ns tCP/2 – 15 — ns tCP/2 – 20 — ns — — Remarks tWLCH 2.4 V CLK tWHLH 2.4 V ALE tWLWH tAVWL 2.4 V WR (WRL, WRH) 0.8 V Multiplex mode tWHAX A23 to A16 2.4 V 2.4 V 0.8 V 0.8 V tDVWH AD15 to AD00 2.4 V Address 0.8 V 2.4 V 0.8 V 0.8 V tWHAX 2.4 V 2.4 V 0.8 V 0.8 V tDVWH D15 to D00 60 2.4 V Write data Non-multiplex mode A23 to A00 tWHDX 2.4 V 0.8 V Write data tWHDX tWHDX 2.4 V 0.8 V MB90610A Series (8) Ready Input Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name RDY setup time tRYHS RDY RDY hold time tRYHH RDY Parameter Conditions Value Unit Min. Max. VCC = +5.0 V±10% 45 — ns VCC = +3.0 V±10% 70 — ns — 0 — ns Remarks Note: Use the auto-ready function if the setup time at fall of the RDY is too short. 2.4 V CLK 2.4 V ALE RD/WR tRYHS tRYHS RDY (Wait cycle) 0.2 VCC 0.2 VCC tRYHS RDY (No wait cycle) 0.8 VCC 0.8 VCC tRYHH 61 MB90610A Series (9) Hold Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Conditions Value Min. Max. Unit Pin floating → HAK ↓ time tXHAL HAK — 30 tCP ns HAK ↑ → pin valid time tHAHV HAK — tCP 2 tCP ns Note: After reading HRQ, more than one cycle is required before changing HAK. HRQ 2.4 V HAK 0.8 V tXHAL Pin 62 tHAHV High impedance Remarks MB90610A Series (10) I/O Expansion Serial Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Conditions Value Min. Max. Unit Serial clock cycle time tSCYC SCK0 to 2 — 8 tCP — ns SCK ↓ → SOT delay time tSLOV SCK0 to 2 SOT0 to 2 VCC = +5.0 V±10% –80 80 ns VCC = +3.0 V±10% –120 120 ns Valid SIN → SCK ↑ tIVSH SCK0 to 2 SIN0 to 2 VCC = +5.0 V±10% 100 — ns VCC = +3.0 V±10% 200 — ns SCK ↑ → valid SIN hold tSHIX time SCK0 to 2 SIN0 to 2 VCC = +5.0 V±10% 60 — ns VCC = +3.0 V±10% 120 — ns Serial clock “H” pulse width tSHSL SCK0 to 2 — 4 tCP — ns Serial clock “L” pulse width tSLSH SCK0 to 2 — 4 tCP — ns — 150 ns SCK ↓ → SOT delay time tSLOV SCK0 to 2 SOT0 to 2 VCC = +5.0 V±10% VCC = +3.0 V±10% — 200 ns Valid SIN → SCK ↑ tIVSH SCK0 to 2 SIN0 to 2 VCC = +5.0 V±10% 60 — ns VCC = +3.0 V±10% 120 — ns SCK ↑ → valid SIN hold tSHIX time SCK0 to 2 SIN0 to 2 VCC = +5.0 V±10% 60 — ns VCC = +3.0 V±10% 120 — ns Remarks CL = 80 pF + 1 TTL for the internal shift clock mode output pin. CL = 80 pF + 1 TTL for the external shift clock mode output pin. Notes: • These are the AC characteristics for CLK synchronous mode. • CL is the load capacitance connected to the pin at testing. • tCP is the machine cycle period (unit: ns). 63 MB90610A Series • Internal Shift Clock Mode tSCYC 2.4 V SCK 0.8 V tSLOV 0.8 V 2.4 V 0.8 V SOT tIVSH tSHIX 0.8 VCC 0.2 VCC SIN 0.8 VCC 0.2 VCC • External Shift Clock Mode tSLSH tSHSL SCK 0.2 VCC tSLOV SOT 0.2 VCC 2.4 V 0.8 V tIVSH SIN 64 0.8 VCC 0.8 VCC 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC MB90610A Series (11) Timer Input Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Input pulse width Pin name Conditions tTIWH/L TIN0 to 1 — Value Min. Max. 4 tCP — Unit Remarks ns • Timer Input Timing 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTIWH tTIWL (12) Timer Output Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter CLK ↑ → TOUT change timing tTO Pin name TOT0 to 1 Conditions Value Unit Min. Max. VCC = +5.0 V±10% 30 — ns VCC = +3.0 V±10% 80 — ns Remarks • Timer Output Timing CLK TOUT 2.4 V 2.4 VCC 0.8 VCC tTO 65 MB90610A Series (13) Trigger Input Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter tTRGH tTRGL Input pulse width Pin name ATG INT0 to INT1 0.8 VCC Value Conditions — Min. Max. 5 tCP — Unit Remarks ns 0.8 VCC 0.2 VCC tTRGH 0.2 VCC tTRGL (14) Chip Select Output Timing (VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Chip select enabled → Valid data input time 66 Symbol tSVDV Pin name Conditions Value Unit Min. Max. VCC = +5.0 V±10% — 5 tCP/2 – 60 ns VCC = +3.0 V±10% — 5 tCP/2 – 80 ns CS0 to CS7 D15 to D00 RD ↑ → Chip select enabled time tRHSV CS0 to CS7 RD — tCP/2 – 10 — ns WR ↑ → Chip select enabled time tWHSV CS0 to CS7 WRH, WRL — tCP/2 – 10 — ns Enabled chip select → CLK ↑ time tSVCH CS0 to CS7 CLK — — tCP/2 – 20 ns Remarks MB90610A Series tSVCH 2.4 V CLK 2.4 V RD tRHSV A23 to A00 CS0 to CS7 2.4 V 0.8 V tSVDV D15 to D00 2.4 V Read data 0.8 V tWHSV 2.4 V WR (WRL, WRH) D15 to D00 Write data 67 MB90610A Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = +2.7 V to +5.5 V, AVSS = VSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C) Parameter Symbol Pin name Value Min. Typ. Max. Unit Resolution — — — 10 10 bit Total error — — — — ±3.0 LSB Linearity error — — — — ±2.0 LSB Differential linearity error — — — — ±1.5 LSB Zero transition voltage VOT AN0 to AN7 AVRL – 1.5 AVRL + 0.5 AVRL + 2.5 LSB Full scale transition voltage VFST AN0 to AN7 AVRH – 4.5 AVRH – 1.5 AVRH + 0.5 LSB 6.125*1 — — µs 12.25*2 — — µs Conversion time — — Analog port input current IAIN AN0 to AN7 — 0.1 10 µA Analog input voltage VAIN AN0 to AN7 AVRL — AVRH V — AVRH AVRL + 2.7 — AVCC V — AVRL 0 — AVRH – 2.7 V IA AVCC — 3 — mA IAH AVCC — — 5*3 µA IR AVRH — 200 — µA IRH AVRH — — *3 5 µA AN0 to AN7 — — 4 LSB Reference voltage Power supply current Reference voltage supply current Variation between channels — *1: For VCC = +5.0 V±10% and a 16 MHz machine clock *2: For VCC = +3.0 V±10% and a 8 MHz machine clock *3: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = +5.0 V). Notes: • The relative error increases as |AVRH – AVRL| decreases. • The output impedance of the external circuit for the analog input should be in the following range. Output impedance of external circuit < approx. 7 kΩ • If the output impedance of the external circuit is too high, the sampling time for the analog voltage may be too short. (Sampling time = 3.75 µs @4 MHz (This corresponds to 16 MHz internal operation if the multiplier is 4.)) • For an external capacitor to be provided outside the chip, its capacity should desirably be thousands times larger than that of the capacity in the chip taking in consideration the influence of the capacity distribution of the external and internal capacitors. 68 MB90610A Series • Model of The Analog Input Circuit Sample and hold circuit C0 Analog input Comparator RON1 RON2 RON3 RON4 C1 RON1 = 1.5 kΩ (approx.) (VCC = 5.0 V) RON2 = 0.5 kΩ (approx.) (VCC = 5.0 V) RON3 = 0.5 kΩ (approx.) (VCC = 5.0 V) RON4 = 0.5 kΩ (approx.) (VCC = 5.0 V) C0 = 60 pF (approx.) C1 = 4 pF (approx.) Note: The above values are for reference only. 6. A/D Converter Glossary • Resolution The change in analog voltage that can be recognized by the A/D converter. If the resolution is 10 bits, the analog voltage can be resolved into 210 = 1024 steps. • Total error The deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and noise. • Linearity error The deviation between the actual conversion characteristic of the device and the line linking the zero transition point (00 0000 0000 ↔ 00 0000 0001) and the full scale transition point (11 1111 1110 ↔ 11 1111 1111). • Differential linearity error The variation from the ideal input voltage required to change the output code by 1 LSB. Digital output 11 1111 1111 11 1111 1110 • • • (1 LSB × N + VOT) • • • • • • • Linearity error • 00 0000 0010 00 0000 0001 00 0000 0000 Analog input VOT 1 LSB = VNT V(N + 1)T VFST VFST – VOT 1022 Linearity error = VNT – (1 LSB × N + VOT) 1 LSB Differential linearity error = V(N + 1)T – VNT 1 LSB (LSB) – 1 (LSB) 69 MB90610A Series ■ EXAMPLES CHARACTERISTICS (1) “H” Level Output Voltage VOH – IOH VOH (V) 1.0 0.9 TA = +25°C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –2 –4 –6 (2) “L” Level Output Voltage VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V –8 IOH (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage VIN (V) 5.0 VIN – VCC (CMOS Input) TA = +25°C 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2 3 4 5 6 VCC (V) VOL (V) 1.0 0.9 TA = +25°C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2 4 VOL – IOL VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V 6 8 IOL (mA) (4) “H” Level Input Voltage/“L” Level Input Voltage VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2 VIN – VCC (Hysteresis Input) TA = +25°C VIHS VILS 3 4 5 6 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 70 MB90610A Series (5) Power Supply Current (fcp = internal frequency) ICC (mA) 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 ICC – VCC TA = +25°C fcp = 16 MHz fcp = 12.5 MHz fcp = 8 MHz fcp = 4 MHz 3.0 IA (mA) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 4.0 5.0 6.0 VCC (V) IA – AVCC ICCS (mA) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.0 IR (mA) 0.30 TA = +25°C fCP = 16 MHz ICCS – VCC TA = +25°C fcp = 16 MHz fcp = 12.5 MHz fcp = 8 MHz fcp = 4 MHz 4.0 5.0 6.0 VCC (V) IR – AVR TA = +25°C fCP = 16 MHz 0.20 0.10 0 3.0 4.0 5.0 6.0 AVCC (V) 3.0 4.0 5.0 6.0 AVR (V) (6) Pull-up Resistance R – VCC R (k ) 1000 TA = +25°C 100 10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC (V) 71 MB90610A Series ■ INSTRUCTIONS (340 INSTRUCTIONS) Table 1 Explanation of Items in Tables of Instructions Item Mnemonic Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. # Indicates the number of bytes. ~ Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. RG B Operation Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the “~” column. Indicates the operation of instruction. LH Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers “0”. X : Extends with a sign before transferring. – : Transfers nothing. AH Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. – : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. I S T N Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. – : No change. S : Set by execution of instruction. R : Reset by execution of instruction. Z V C RMW 72 Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. – : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. MB90610A Series Table 2 Explanation of Symbols in Tables of Instructions Symbol A Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL:AH AH AL Upper 16 bits of A Lower 16 bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset vct4 vct8 Vector number (0 to 15) Vector number (0 to 255) ( )b Bit address (Continued) 73 MB90610A Series (Continued) Symbol Meaning rel Branch specification relative to PC ear eam Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) rlst Register list Table 3 Code 00 01 02 03 04 05 06 07 Notation R0 R1 R2 R3 R4 R5 R6 R7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 Effective Address Fields Address format RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Number of bytes in address extension * Register direct “ea” corresponds to byte, word, and long-word types, starting from the left 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 Register indirect 0C 0D 0E 0F @RW0 + @RW1 + @RW2 + @RW3 + Register indirect with post-increment 10 11 12 13 14 15 16 17 @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 Register indirect with 8-bit displacement 18 19 1A 1B @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 Register indirect with 16-bit displacement 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address — 0 0 1 2 0 0 2 2 Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes) column in the tables of instructions. 74 MB90610A Series Table 4 Number of Execution Cycles for Each Type of Addressing (a) Code Operand Number of execution cycles for each type of addressing Number of register accesses for each type of addressing Listed in tables of instructions Listed in tables of instructions 00 to 07 Ri RWi RLi 08 to 0B @RWj 2 1 0C to 0F @RWj + 4 2 10 to 17 @RWi + disp8 2 1 18 to 1B @RWj + disp16 2 1 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 4 4 2 1 2 2 0 0 Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles (b) byte Operand (c) word (d) long Number Number Number Number Number Number of of of of cycles access of cycles access of cycles access Internal register +0 1 +0 1 +0 2 Internal memory even address Internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 Even address on external data bus (16 bits) Odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 External data bus (8 bits) +1 1 +4 2 +8 4 Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value) in the tables of instructions. • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory — +2 External data bus (16 bits) — +3 External data bus (8 bits) +3 — Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. • Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for “worst case” calculations. 75 MB90610A Series Mnemonic Table 7 Transfer Instructions (Byte) [41 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 2 3 1 2 2+ 2 2 2 3 1 3 4 2 2 3+ (a) 3 2 3 10 1 0 0 1 1 0 0 0 0 2 0 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 Z Z Z Z Z Z Z Z Z Z * * * * * * * – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * R * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 2 3 2 2 2+ 2 2 2 2 3 3 4 2 2 3+ (a) 3 2 3 5 10 0 0 1 1 0 0 0 0 1 2 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8) X X X X X X X X X X * * * * * * * – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi) +disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 byte ((A)) ← (AH) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * – – * – * * * * * * * * * * * * * – – * – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – XCH XCH XCH XCH A, ear A, eam Ri, ear Ri, eam 2 2+ 2 2+ 4 5+ (a) 7 9+ (a) 2 0 4 2 0 2× (b) 0 2× (b) byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) Z Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 76 MB90610A Series Table 8 Mnemonic Transfer Instructions (Word/Long Word) [38 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 2 3 1 1 2 2+ 2 2 3 2 3 3 4 1 2 2 3+ (a) 3 3 2 5 10 0 0 0 1 1 0 0 0 0 1 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 word (A) ← ((RWi) +disp8) word (A) ← ((RLi) +disp8) – – – – – – – – – – – * * * * * * * – * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW dir, A addr16, A SP, A RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) word ((RWi) +disp8) ← (A) word ((RLi) +disp8) ← (A) word (RWi) ← (ear) word (RWi) ← (eam) word (ear) ← (RWi) word (eam) ← (RWi) word (RWi) ← imm16 word (io) ← imm16 word (ear) ← imm16 word (eam) ← imm16 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * – * – * * * * * * * * * * * * * * – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVW AL, AH /MOVW @A, T 2 3 0 (c) word ((A)) ← (AH) – – – – – * * – – – XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam 2 2+ 2 2+ 4 5+ (a) 7 9+ (a) 2 0 4 2 0 2× (c) 0 2× (c) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVL MOVL MOVL A, ear A, eam A, #imm32 2 2+ 5 4 5+ (a) 3 2 0 0 0 (d) 0 long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 – – – – – – – – – – – – – – – * * * * * * – – – – – – – – – MOVL MOVL ear, A eam, A 2 2+ 4 5+ (a) 2 0 0 (d) long (ear) ← (A) long (eam) ← (A) – – – – – – – – – – * * * * – – – – – – Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 77 MB90610A Series Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2× b) 0 0 (b) 0 0 (b) 0 (b) 0 2×(b) 0 0 (b) 0 byte (A) ← (A) +imm8 byte (A) ← (A) +(dir) byte (A) ← (A) +(ear) byte (A) ← (A) +(eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear) + (C) byte (A) ← (A) + (eam) + (C) byte (A) ← (AH) + (AL) + (C) (decimal) byte (A) ← (A) –imm8 byte (A) ← (A) – (dir) byte (A) ← (A) – (ear) byte (A) ← (A) – (eam) byte (ear) ← (ear) – (A) byte (eam) ← (eam) – (A) byte (A) ← (AH) – (AL) – (C) byte (A) ← (A) – (ear) – (C) byte (A) ← (A) – (eam) – (C) byte (A) ← (AH) – (AL) – (C) (decimal) Z Z Z Z – Z Z Z Z Z Z Z Z Z – – Z Z Z Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – * – – – – – – – – – * – – – – ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW A A, ear A, eam A, #imm16 ear, A eam, A A, ear A, eam A A, ear A, eam A, #imm16 ear, A eam, A A, ear A, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2×(c) 0 (c) 0 0 (c) 0 0 2×(c) 0 (c) word (A) ← (AH) + (AL) word (A) ← (A) +(ear) word (A) ← (A) +(eam) word (A) ← (A) +imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) – (AL) word (A) ← (A) – (ear) word (A) ← (A) – (eam) word (A) ← (A) –imm16 word (ear) ← (ear) – (A) word (eam) ← (eam) – (A) word (A) ← (A) – (ear) – (C) word (A) ← (A) – (eam) – (C) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – * – – – – – – – * – – ADDL ADDL ADDL SUBL SUBL SUBL A, ear 2 A, eam 2+ A, #imm32 5 A, ear 2 A, eam 2+ A, #imm32 5 6 7+(a) 4 6 7+(a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) +imm32 long (A) ← (A) – (ear) long (A) ← (A) – (eam) long (A) ← (A) –imm32 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * – – – – – – Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 78 MB90610A Series Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW INC INC ear eam 2 2+ 2 5+ (a) 2 0 0 byte (ear) ← (ear) +1 2× (b) byte (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DEC DEC ear eam 2 2+ 3 5+ (a) 2 0 0 byte (ear) ← (ear) –1 2× (b) byte (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * INCW INCW ear eam 2 2+ 3 5+ (a) 2 0 0 word (ear) ← (ear) +1 2× (c) word (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DECW DECW ear eam 2 2+ 3 5+ (a) 2 0 0 word (ear) ← (ear) –1 2× (c) word (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * INCL INCL ear eam 2 2+ 7 9+ (a) 4 0 0 long (ear) ← (ear) +1 2× (d) long (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DECL DECL ear eam 2 2+ 7 9+ (a) 4 0 0 long (ear) ← (ear) –1 2× (d) long (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 11 Mnemonic Compare Instructions (Byte/Word/Long Word) [11 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW CMP CMP CMP CMP A A, ear A, eam A, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (AH) – (AL) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← imm8 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPW CMPW CMPW CMPW A A, ear A, eam A, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (AH) – (AL) word (A) ← (ear) word (A) ← (eam) word (A) ← imm16 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPL CMPL CMPL A, ear A, eam A, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (A) ← (ear) word (A) ← (eam) word (A) ← imm32 – – – – – – – – – – – – – – – * * * * * * * * * * * * – – – Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 79 MB90610A Series Table 12 Mnemonic Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # ~ RG B Operation word (AH) /byte (AL) Quotient → byte (AL) Remainder → byte (AH) word (A)/byte (ear) Quotient → byte (A) Remainder → byte (ear) word (A)/byte (eam) Quotient → byte (A) Remainder → byte (eam) long (A)/word (ear) Quotient → word (A) Remainder → word (ear) long (A)/word (eam) Quotient → word (A) Remainder → word (eam) DIVU A 1 *1 0 0 DIVU A, ear 2 *2 1 0 DIVU A, eam 2+ *3 0 *6 DIVUW A, ear 2 *4 1 0 DIVUW A, eam 2+ *5 0 *7 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10 0 1 0 MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 0 1 0 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: LH AH I S T N Z V C RMW – – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – * * – 0 byte (AH) *byte (AL) → word (A) 0 byte (A) *byte (ear) → word (A) (b) byte (A) *byte (eam) → word (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 word (AH) *word (AL) → long (A) 0 word (A) *word (ear) → long (A) (c) word (A) *word (eam) → long (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 × (b) normally. (c) when the result is zero or when an overflow occurs, and 2 × (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 80 MB90610A Series Table 13 Logical 1 Instructions (Byte/Word) [39 Instructions] Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW AND AND AND AND AND A, #imm8 A, ear A, eam ear, A eam, A 2 2 2+ 2 2+ 2 3 4+ (a) 3 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) and imm8 byte (A) ← (A) and (ear) byte (A) ← (A) and (eam) byte (ear) ← (ear) and (A) byte (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * OR OR OR OR OR A, #imm8 A, ear A, eam ear, A eam, A 2 2 2+ 2 2+ 2 3 4+ (a) 3 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) or imm8 byte (A) ← (A) or (ear) byte (A) ← (A) or (eam) byte (ear) ← (ear) or (A) byte (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * XOR XOR XOR XOR XOR A, #imm8 A, ear A, eam ear, A eam, A 2 2 2+ 2 2+ 2 3 4+ (a) 3 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) xor imm8 byte (A) ← (A) xor (ear) byte (A) ← (A) xor (eam) byte (ear) ← (ear) xor (A) byte (eam) ← (eam) xor (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * NOT NOT NOT A ear eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 byte (A) ← not (A) 0 byte (ear) ← not (ear) 2× (b) byte (eam) ← not (eam) – – – – – – – – – – – – – – – * * * * * * R R R – – – – – * ANDW ANDW ANDW ANDW ANDW ANDW A A, #imm16 A, ear A, eam ear, A eam, A 1 3 2 2+ 2 2+ 2 2 3 4+ (a) 3 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) and (A) word (A) ← (A) and imm16 word (A) ← (A) and (ear) word (A) ← (A) and (eam) word (ear) ← (ear) and (A) word (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * ORW ORW ORW ORW ORW ORW A A, #imm16 A, ear A, eam ear, A eam, A 1 3 2 2+ 2 2+ 2 2 3 4+ (a) 3 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) or (A) word (A) ← (A) or imm16 word (A) ← (A) or (ear) word (A) ← (A) or (eam) word (ear) ← (ear) or (A) word (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * XORW XORW XORW XORW XORW XORW A A, #imm16 A, ear A, eam ear, A eam, A 1 3 2 2+ 2 2+ 2 2 3 4+ (a) 3 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) xor (A) word (A) ← (A) xor imm16 word (A) ← (A) xor (ear) word (A) ← (A) xor (eam) word (ear) ← (ear) xor (A) word (eam) ← (eam) xor (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * NOTW NOTW NOTW A ear eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 word (A) ← not (A) 0 word (ear) ← not (ear) 2× (c) word (eam) ← not (eam) – – – – – – – – – – – – – – – * * * * * * R R R – – – – – * Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 81 MB90610A Series Table 14 Mnemonic Logical 2 Instructions (Long Word) [6 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW ANDL ANDL A, ear A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) and (ear) long (A) ← (A) and (eam) – – – – – – – – – – * * * * R R – – – – ORL ORL A, ear A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) or (ear) long (A) ← (A) or (eam) – – – – – – – – – – * * * * R R – – – – XORL XORL A, ea A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) xor (ear) long (A) ← (A) xor (eam) – – – – – – – – – – * * * * R R – – – – Table 15 Mnemonic Sign Inversion Instructions (Byte/Word) [6 Instructions] # ~ RG B 0 NEG A 1 2 0 NEG NEG ear eam 2 2+ 3 5+ (a) 2 0 NEGW A 1 2 0 NEGW ear NEGW eam 2 2+ 3 5+ (a) 2 0 Table 16 Mnemonic NRML A, R0 Operation byte (A) ← 0 – (A) 0 byte (ear) ← 0 – (ear) 2× (b) byte (eam) ← 0 – (eam) 0 word (A) ← 0 – (A) 0 word (ear) ← 0 – (ear) 2× (c) word (eam) ← 0 – (eam) LH AH I S T N Z V C RMW X – – – – * * * * – – – – – – – – – – – * * * * * * * * – * – – – – – * * * * – – – – – – – – – – – * * * * * * * * – * Normalize Instruction (Long Word) [1 Instruction] # ~ RG B 2 *1 1 0 Operation LH AH long (A) ← Shift until first digit is “1” – byte (R0) ← Current shift count – I S T N Z V C RMW – – – * – – – – *1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 82 MB90610A Series Table 17 Mnemonic Shift Instructions (Byte/Word/Long Word) [18 Instructions] # ~ RG B RORC A ROLC A 2 2 2 2 0 0 0 0 RORC RORC ROLC ROLC ear eam ear eam 2 3 2+ 5+(a) 2 3 2+ 5+(a) 2 0 2 0 0 2×(b) 0 2×(b) ASR LSR LSL A, R0 A, R0 A, R0 2 2 2 *1 *1 *1 1 1 1 ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 2 2 2 ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2 ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 Operation LH AH I S T N Z V C RMW byte (A) ← Right rotation with carry byte (A) ← Left rotation with carry – – – – – – – – – – * * * * – – * * – – byte (ear) ← Right rotation with carry byte (eam) ← Right rotation with carry byte (ear) ← Left rotation with carry byte (eam) ← Left rotation with carry – – – – – – – – – – – – – – – – * * * * * * * * – – – – * * * * – * – * 0 0 0 byte (A) ← Arithmetic right barrel shift (A, R0) byte (A) ← Logical right barrel shift (A, R0) byte (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – 0 0 0 0 0 0 word (A) ← Arithmetic right shift (A, 1 bit) word (A) ← Logical right shift (A, 1 bit) word (A) ← Logical left shift (A, 1 bit) – – – – – – – – * – – * – – – * R * * * * – – – * * * – – – *1 *1 *1 1 1 1 0 0 0 word (A) ← Arithmetic right barrel shift (A, R0) word (A) ← Logical right barrel shift (A, R0) word (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – *2 *2 *2 1 1 1 0 0 0 long (A) ← Arithmetic right shift (A, R0) long (A) ← Logical right barrel shift (A, R0) long (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – – – – – *1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 83 MB90610A Series Table 18 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel rel rel rel rel # ~ RG B Operation 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 0 1 0 2 0 0 0 0 0 (c) 0 (d) 0 – – – – – – – 1 0 0 0 2 (c) 2×(c) (c) 2×(c) 2×(c) 0 *2 0 2×(c) word (PC) ← (A) word (PC) ← addr16 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← (ear), (PCB) ← (ear +2) word (PC) ← (eam), (PCB) ← (eam +2) word (PC) ← ad24 0 to 15, (PCB) ← ad24 16 to 23 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← addr16 Vector call instruction word (PC) ← (ear) 0 to 15 (PCB) ← (ear) 16 to 23 word (PC) ← (eam) 0 to 15 (PCB) ← (eam) 16 to 23 word (PC) ← addr0 to 15, (PCB) ← addr16 to 23 JMP JMP JMP JMP JMPP JMPP JMPP @A addr16 @ear @eam @ear *3 @eam *3 addr24 1 3 2 2+ 2 2+ 4 CALL CALL CALL CALLV CALLP @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6 2 2+ 3 1 2 CALLP @eam *6 2+ CALLP addr24 *7 4 *1: *2: *3: *4: *5: *6: *7: Branch 1 Instructions [31 Instructions] 2 3 3 4+(a) 5 6+(a) 4 6 7+(a) 6 7 10 11+(a) 10 LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 4 when branching, 3 when not branching. (b) + 3 × (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack. Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 84 MB90610A Series Table 19 Mnemonic Branch 2 Instructions [19 Instructions] # ~ RG B CBNE A, #imm8, rel CWBNE A, #imm16, rel 3 4 *1 *1 0 0 0 0 CBNE ear, #imm8, rel CBNE eam, #imm8, rel*9 CWBNE ear, #imm16, rel CWBNE eam, #imm16, rel*9 4 4+ 5 5+ *2 *3 *4 *3 1 0 1 0 0 (b) 0 (c) DBNZ 3 *5 2 3+ *6 2 DWBNZ ear, rel 3 *5 2 DWBNZ eam, rel 3+ *6 INT INT INTP INT9 RETI #vct8 addr16 addr24 2 3 4 1 1 LINK #local8 Operation LH AH I S T N Z V C RMW Branch when byte (A) ≠ imm8 Branch when word (A) ≠ imm16 – – – – – – – – – – * * * * * * * * – – Branch when byte (ear) ≠ imm8 Branch when byte (eam) ≠ imm8 Branch when word (ear) ≠ imm16 Branch when word (eam) ≠ imm16 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – Branch when byte (ear) = (ear) – 1, and (ear) ≠ 0 2×(b) Branch when byte (eam) = (eam) – 1, and (eam) ≠ 0 – – – – – * * * – – – – – – – * * * – * – – – – – * * * – – 2 Branch when word (ear) = (ear) – 1, and (ear) ≠ 0 2×(c) Branch when word (eam) = (eam) – 1, and (eam) ≠ 0 – – – – – * * * – * 20 16 17 20 15 0 0 0 0 0 8×(c) 6×(c) 6×(c) 8×(c) 6×(c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt – – – – – – – – – – R R R R * S S S S * – – – – * – – – – * – – – – * – – – – * – – – – * – – – – – 2 6 0 (c) – – – – – – – – – – UNLINK 1 5 0 (c) At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. – – – – – – – – – – RET *7 RETP *8 1 1 4 6 0 0 (c) (d) Return from subroutine Return from subroutine – – – – – – – – – – – – – – – – – – – – DBNZ *1: *2: *3: *4: *5: *6: *7: *8: *9: ear, rel eam, rel 0 0 5 when branching, 4 when not branching 13 when branching, 12 when not branching 7 + (a) when branching, 6 + (a) when not branching 8 when branching, 7 when not branching 7 when branching, 6 when not branching 8 + (a) when branching, 7 + (a) when not branching Retrieve (word) from stack Retrieve (long word) from stack In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 85 MB90610A Series Table 20 Mnemonic Other Control Instructions (Byte/Word/Long Word) [36 Instructions] # ~ RG B Operation PUSHW A PUSHW AH PUSHW PS PUSHW rlst 1 1 1 2 4 4 4 *3 0 0 0 *5 (c) (c) (c) *4 word (SP) ← (SP) –2, ((SP)) ← (A) word (SP) ← (SP) –2, ((SP)) ← (AH) word (SP) ← (SP) –2, ((SP)) ← (PS) (SP) ← (SP) –2n, ((SP)) ← (rlst) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – POPW POPW POPW POPW A AH PS rlst 1 1 1 2 3 3 4 *2 0 0 0 *5 (c) (c) (c) *4 word (A) ← ((SP)), (SP) ← (SP) +2 word (AH) ← ((SP)), (SP) ← (SP) +2 word (PS) ← ((SP)), (SP) ← (SP) +2 (rlst) ← ((SP)), (SP) ← (SP) +2n – – – – * – – – – – – – – – * * * – – – – – * – – – * – – – * – – – * – – – – – JCTX @A 1 14 0 – – * * * * * * * – AND OR CCR, #imm8 CCR, #imm8 2 2 3 3 0 0 0 0 byte (CCR) ← (CCR) and imm8 byte (CCR) ← (CCR) or imm8 – – – – * * * * * * * * * * * * * * – – MOV RP, #imm8 MOV ILM, #imm8 2 2 2 2 0 0 0 0 byte (RP) ←imm8 byte (ILM) ←imm8 – – – – – – – – – – – – – – – – – – – – MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam 2 3 2+ 2+ (a) 2 1 2+ 1+ (a) 1 1 0 0 0 0 0 0 word (RWi) ←ear word (RWi) ←eam word(A) ←ear word (A) ←eam – – – – – – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – ADDSP #imm8 ADDSP #imm16 2 3 3 3 0 0 0 0 word (SP) ← (SP) +ext (imm8) word (SP) ← (SP) +imm16 – – – – – – – – – – – – – – – – – – – – MOV MOV 2 2 *1 1 0 0 0 0 byte (A) ← (brgl) byte (brg2) ← (A) Z – * – – – – – – – * * * * – – – – – – 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 6× (c) Context switch instruction LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 ¥ (pop count) + 2 ¥ (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) – 3 ¥ (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count ¥ (c), or push count ¥ (c) *1: Pop count or push count. Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 86 MB90610A Series Table 21 Bit Manipulation Instructions [21 Instructions] Mnemonic # ~ RG B MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp 3 4 3 5 5 4 0 0 0 (b) (b) (b) MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A 3 4 3 7 7 6 0 0 0 SETB SETB SETB dir:bp addr16:bp io:bp 3 4 3 7 7 7 CLRB dir:bp CLRB addr16:bp CLRB io:bp 3 4 3 BBC BBC BBC dir:bp, rel addr16:bp, rel io:bp, rel BBS BBS BBS Operation byte (A) ← (dir:bp) b byte (A) ← (addr16:bp) b byte (A) ← (io:bp) b LH AH I S T N Z V C RMW Z Z Z * * * – – – – – – – – – * * * * * * – – – – – – – – – 2× (b) bit (dir:bp) b ← (A) 2× (b) bit (addr16:bp) b ← (A) 2× (b) bit (io:bp) b ← (A) – – – – – – – – – – – – – – – * * * * * * – – – – – – * * * 0 0 0 2× (b) bit (dir:bp) b ← 1 2× (b) bit (addr16:bp) b ← 1 2× (b) bit (io:bp) b ← 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 7 7 7 0 0 0 2× (b) bit (dir:bp) b ← 0 2× (b) bit (addr16:bp) b ← 0 2× (b) bit (io:bp) b ← 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – dir:bp, rel addr16:bp, rel io:bp, rel 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – SBBS addr16:bp, rel 5 *3 0 2× (b) Branch when (addr16:bp) b = 1, bit = 1 – – – – – – * – – * WBTS io:bp 3 *4 0 *5 Wait until (io:bp) b = 1 – – – – – – – – – – WBTC io:bp 3 *4 0 *5 Wait until (io:bp) b = 0 – – – – – – – – – – *1: *2: *3: *4: *5: 8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 87 MB90610A Series Table 22 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW # ~ 1 1 1 1 1 1 3 2 1 2 1 1 RG B 0 0 0 0 0 0 0 0 0 0 0 0 Table 23 Mnemonic RG B Operation byte (A) 0 to 7 ↔ (A) 8 to 15 word (AH) ↔ (AL) byte sign extension word sign extension byte zero extension word zero extension LH AH – – X – Z – – * – X – Z I S T N Z V C RMW – – – – – – – – – – – – – – * * R R – – * * * * – – – – – – – – – – – – – – – – – – – – – – – – String Instructions [10 Instructions] # ~ Operation LH AH I S T N Z V C RMW MOVS/MOVSI MOVSD 2 2 *2 *2 *5 *5 *3 Byte transfer @AH+ ← @AL+, counter = RW0 *3 Byte transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – SCEQ/SCEQI SCEQD 2 2 *1 *1 *5 *5 *4 Byte retrieval (@AH+) – AL, counter = RW0 *4 Byte retrieval (@AH–) – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – FISL/FILSI 2 6m+6 *5 *3 Byte filling @AH+ ← AL, counter = RW0 – – – – – * * – – – MOVSW/MOVSWI MOVSWD 2 2 *2 *2 *8 *8 *6 Word transfer @AH+ ← @AL+, counter = RW0 – *6 Word transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – SCWEQ/SCWEQI SCWEQD 2 2 *1 *1 *8 *8 *7 Word retrieval (@AH+) – AL, counter = RW0 *7 Word retrieval (@AH–) – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – FILSW/FILSWI 2 6m+6 *8 *6 Word filling @AH+ ← AL, counter = RW0 – – – – – * * – – – m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case *3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) × n *5: 2 × (RW0) *6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) × n *8: 2 × (RW0) Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 88 MB90610A Series ■ ORDERING INFORMATION Part number Package MB90611APFV 100-pin Plastic LQFP (FPT-100P-M05) MB90611APF 100-pin Plastic QFP (FPT-100P-M06) Remarks 89 MB90610A Series ■ PACKAGE DIMENSIONS 100-pin Plastic LQFP (FPT-100P-M05) +0.20 16.00±0.20(.630±.008)SQ 75 1.50 −0.10 +.008 .059 −.004 51 14.00±0.10(.551±.004)SQ 76 (Mounting height) 50 12.00 (.472) REF 15.00 (.591) NOM Details of "A" part 0.15(.006) INDEX 100 0.15(.006) 26 0.15(.006)MAX LEAD No. "B" 25 1 0.40(.016)MAX "A" +0.08 0.50(.0197)TYP 0.18 −0.03 +.003 .007 −.001 +0.05 0.08(.003) 0.127 −0.02 +.002 .005 −.001 M Details of "B" part 0.10±0.10 (STAND OFF) (.004±.004) 0.50±0.20(.020±.008) 0.10(.004) C 0~10˚ Dimensions in mm (inches) 1995 FUJITSU LIMITED F100007S-2C-3 100-pin Plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) 80 3.35(.132)MAX 20.00±0.20(.787±.008) 0.05(.002)MIN (STAND OFF) 51 81 50 14.00±0.20 (.551±.008) 17.90±0.40 (.705±.016) 12.35(.486) REF 16.30±0.40 (.642±.016) INDEX 31 100 "A" LEAD No. 1 30 0.65(.0256)TYP 0.30±0.10 (.012±.004) 0.13(.005) 0.15±0.05(.006±.002) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 18.85(.742)REF 22.30±0.40(.878±.016) C 90 1994 FUJITSU LIMITED F100008-3C-2 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX 0 10° 0.80±0.20 (.031±.008) Dimensions in mm (inches) MB90610A Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fmap.com.sg/ F9907 FUJITSU LIMITED Printed in Japan 91