FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16305-2E
32-bit RISC Microcontroller
CMOS
FR Series MB91107/108
MB91107/108
■ DESCRIPTION
The MB91107 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family)
core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU
processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU,
the MB91107 normally operates in the external bus access mode and executes instructions on the internal
1 Kbyte cache memory and RAM (MB91107: 128 Kbytes, MB91108: 160 Kbytes) for enhanced performance.
The MB91107 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers.
*: FR Family stands for FUJITSU RISC controller.
■ FEATURES
FR CPU
•
•
•
•
•
•
32-bit RISC, load/store architecture, 5-stage pipeline
Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
General purpose registers: 32 bits × 16
16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
supporting high level languages
(Continued)
■ PACKAGE
120-pin Plastic LQFP
(FPT-120P-M21)
MB91107/108
(Continued)
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots: Reduced overhead time in branch executions
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
• Interrupt (push PC and PS): 6 cycles, 16 priority levels
Bus interface
•
•
•
•
•
•
Clock doubler: Internal 50 MHz, external bus 25 MHz operation
25-bit address bus (32 Mbytes memory space)
8/16-bit data bus
Basic external bus cycle: 2 clock cycles
Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 8
Interface supported for various memory technologies
DRAM interface (area 4 and 5)
• Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
• Unused data/address pins can be configured us input/output ports
• Little endian mode supported (Select 1 area from area 1 to 5)
DRAM interface
•
•
•
•
•
2 banks independent control (area 4 and 5)
Double CAS DRAM (normal DRAM I/F) / Single CAS DRAM / Hyper DRAM
Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
DRAM refresh
CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode
• Supports 8/9/10/12-bit column address width
• 2CAS/1WE, 2WE/1CAS selective
Cache memory
•
•
•
•
1-Kbyte instruction cache memory
2 way set associative
32 block/way, 4 entry(4 word)/block
Lock function: For specific program code to be resident in cache memory
DMAC (DMA controller)
•
•
•
•
•
8 channels
Transfer incident/external pins/internal resource interrupt requests
Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
Transfer data length: 8 bits/16 bits/32 bits selective
NMI/interrupt request enables temporary stop operation
UART
•
•
•
•
•
•
2
3 independent channels
Full-duplex double buffer
Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
Asynchronous (start-stop system), CLK-synchronized communication selective
Multi-processor mode
Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate
(Continued)
MB91107/108
(Continued)
• Use external clock can be used as a transfer clock
• Error detection: Parity, frame, overrun
10-bit A/D converter (successive approximation conversion type)
•
•
•
•
•
10-bit resolution, 4 channels
Successive approximation type: Conversion time of 5.6 µs at 25 MHz
Internal sample and hold circuit
Conversion mode: Single conversion/scanning conversion/repeated conversion selective
Start: Software/external trigger/internal timer selective
16-bit reload timer
• 16-bit timer: 3 channels
• Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective
Other interval timers
• 16-bit timer: 3 channels (U-TIMER)
• PWM timer: 4 channels
• Watchdog timer: 1 channel
Bit search module
First bit transition “1” or “0” from MSB can be detected in 1 cycle
Interrupt controller
• External interrupt input: Non-maskable interrupt (NMI), normal interrupt 8 (INT0 to INT7)
• Internal interrupt incident:UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt
module
• Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 levels)
Others
• Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset
• Low-power consumption mode: Sleep mode/stop mode
• Clock control
Gear function:Operating clocks for CPU and peripherals are independently selective
Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)
However, operating frequency for peripherals is less than 25 MHz.
• Packages: LQFP-120
• CMOS technology (0.35 µm): MB91V108 (0.25 µm) ••••• Development model
MB91107 (0.25 µm) ••••• Production model
MB91108 (0.25 µm) ••••• Production model
• Power supply voltage: 3.3 V ± 0.3 V (internal regulator)
3
MB91107/108
■ PIN ASSIGNMENT
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
RAS1/PB4
DW0/PB3
CS0H/PB2
CS0L/PB1
RAS0/PB0
VCC
X0
X1
VSS
PI1/EOP2/ATG
PI0/DACK2
PE7/DREQ2
PE6/EOP1
PE5/DACK1
PE4/DREQ1
PE3/EOP0
PE2/DACK0
PE1/DREQ0
PE0/SC2
PF7/SO2
PF6/SI2
PF5/SC1
PF4/SO1
PF3/SI1
PF2/SC0
PF1/SO0
VSS
PF0/SI0
PG7/INT7
PG6/INT6
(TOP VIEW)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
P26/D22
P27/D23
D24
D25
D26
D27
D28
D29
D30
D31
VSS
A00
A01
A02
A03
A04
A05
A06
A07
VCC
A08
A09
A10
A11
A12
A13
A14
A15
VSS
P60/A16
PB5/CS1L
PB6/CS1H
PB7/DW1
C
CS0
PA1/CS1
PA2/CS2
PA3/CS3
PA4/CS4
PA5/CS5
PA6/CLK
NMI
HST
RST
VSS
MD0
MD1
MD2
P80/RDY
P81/BGRNT
P82/BRQ
RD
WR0
P85/WR1
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
(FPT-120P-M21)
4
PG5/INT5
PG4/INT4
PG3/INT3
PG2/INT2
PG1/INT1
PG0/INT0
VCC
PH7/OCPA3
PH6/OCPA2
PH5/OCPA1
PH4/OCPA0
PH3/TRG3/CS7
PH2/TRG2/CS6
PH1/TRG1
PH0/TRG0
AN3
AN2
AN1
AN0
AVSS/AVRL
AVRH
AVCC
A24/P70
A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
MB91107/108
■ PIN DESCRIPTION
Pin no.
Pin name
Circuit
type
Function
85
86
87
88
89
90
91
92
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
C
Bit 16 to bit 23 of external data bus.
Can be configured as ports (P20 to P27) when external data bus width is
set to 8-bit.
93
94
95
96
97
98
99
100
D24
D25
D26
D27
D28
D29
D30
D31
C
Bit 24 to bit 31 of external data bus.
102
103
104
105
106
107
108
109
111
112
113
114
115
116
117
118
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
F
Bit 00 to bit 15 of external address bus.
120
1
2
3
4
5
6
7
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
F
Bit 16 to bit 23 of external address bus.
Can be configured as ports(P60 to P67) when not used as address bus.
8
A24/P70
F
Bit 24 of external address bus.
Can be configured as a port(P70) when not used as address bus.
79
RDY/P80
C
External ready input.
Inputs “0” when bus cycle is being executed and not completed.
Can be configured as a port when this pin is not used.
(Continued)
5
MB91107/108
Pin no.
Pin name
Circuit
type
80
BGRNT/P81
F
External bus release acknowledge output.
Outputs “L” level when external bus is released.
Can be configured as a port when this pin is not used.
81
BRQ/P82
P
External bus release request input.
Inputs “1” when release of external bus is required.
Can be configured as a port when this pin is not used.
82
RD
M
Read strobe output pin for external bus.
83
84
WR0
WR1/P85
M
F
Function
Write strobe output pin for external bus. Relation between control signals
and effective byte locations is as follows:
16-bit bus width
8-bit bus width
D31 to
D24
WR0
WR0
D23 to
D16
WR1
(I/O port enabled)
Note: WR1 is Hi-Z during resetting. Attach an external pull-up resister
when using at 16-bit bus width.
65
CS0
66
67
68
69
70
M
Chip select 0 output (“L” active).
CS1/PA1
CS2/PA2
CS3/PA3
CS4/PA4
CS5/PA5
F
Chip select 1 output (“L” active).
Chip select 2 output (“L” active).
Chip select 3 output (“L” active).
Chip select 4 output (“L” active).
Chip select 5 output (“L” active).
Can be configured as ports when PA1 to PA5 are not used.
71
CLK/PA6
F
System clock output.
Outputs clock signal of external bus operating frequency.
Can be configured as a port when PA6 is not used.
56
57
58
59
60
61
62
63
RAS0/PB0
CS0L/PB1
CS0H/PB2
DW0/PB3
RAS1/PB4
CS1L/PB5
CS1H/PB6
DW1/PB7
F
RAS output for DRAM bank 0.
CASL output for DRAM bank 0.
CASH output for DRAM bank 0.
Refer to the
WE output for DRAM bank 0 (“L” active).
DRAM interface
RAS output for DRAM bank 1.
for details.
CASL output for DRAM bank 1.
CASH output for DRAM bank 1.
WE output for DRAM bank 1 (“L” active)
Can be configured as a port when PB0 to PB7 are not used.
76
77
78
MD0
MD1
MD2
G
Mode pins 0 to 2.
MCU basic operation mode is set by these pins.
Directly connect these pins with VCC or VSS for use.
53
54
X1
X0
A
Clock (oscillator) output.
Clock (oscillator) input.
74
RST
B
External reset input.
73
HST
H
Hardware standby input (“L” active).
(Continued)
6
MB91107/108
Pin no.
Pin name
Circuit
type
72
NMI
H
42
43
SC2/PE0
DREQ0/PE1
F
F
Function
NMI (non-maskable interrupt pin) input (“L” active).
(SC2) Clock I/O pin for UART2.
Clock output is available when clock output of UART2 is enabled.
(PE0) General purpose I/O port.
This function is available when UART2 clock output is disabled.
(DREQ0) External transfer request input pins for DMA. This pin is used
for input when external trigger is selected to cause DMAC operation, and
it is necessary to disable output for other functions from this pin unless
such output is made intentionally.
(PE1) General purpose I/O port.
44
45
DACK0/PE2
EOP0/PE3
F
F
(DACK0) External transfer request acknowledge output pin for DMAC
(ch. 0). This function is available when transfer request output for DMAC
is enabled.
(PE2) General purpose I/O port.
This function is available when transfer request acknowledge output for
DMAC or DACK0 output is disabled.
(EOP0) Can be configured as DMAC EOP OUTPUT (ch.0) when DMAC
EOP output is enable.
(PE3) General purpose I/O port.
46
DREQ1/PE4
F
(DREQ1) External transfer request input pins for DMA. This pin is used
for input when external trigger is selected to cause DMAC operation, and
it is necessary to disable output for other functions from this pin unless
such output is made intentionally.
(PE4) General purpose I/O port.
47
48
DACK1/PE5
EOP1/PE6
F
F
(DACK1) External transfer request acknowledge output pin for DMAC
(ch. 1). This function is available when transfer request output for DMAC
is enabled.
(PE5) General purpose I/O port.
This function is available when transfer request acknowledge output for
DMAC or DACK1 output is disabled.
(EOP1) Can be configured as DMAC EOP OUTPUT (ch.1) when DMAC
EOP output is enable.
(PE6) General purpose I/O port.
49
DREQ2/PE7
F
(DREQ2) External transfer request input pins for DMA.
This pin is used for input when external trigger is selected to cause
DMAC operation, and it is necessary to disable output for other functions
from this pin unless such output is made intentionally.
(PE7) General purpose I/O port.
(Continued)
7
MB91107/108
Pin no.
33
Pin name
SI0/PF0
Circuit
type
F
Function
(SI0) UART0 data input pin.
This pin is used for input during UART0 is in input operation, and it is
necessary to disable output for other functions from this pin unless such
output is made intentionally.
(PF0) General purpose I/O port.
35
36
37
SO0/PF1
SC0/PF2
SI1/PF3
F
F
F
(SO0) UART0 data output pin.
This function is available when UART0 data output is enabled.
(PF1) General purpose I/O port.
This function is available when UART0 data output is disabled.
(SC0) UART0 clock I/O pin.
Clock output is available when UART0 clock output is enabled.
(PF2) General purpose I/O port.
This function is available when UART0 clock output is disabled.
(SI1) UART1 data input pin.
This pin is used for input during UART1 is in input operation, and it is
necessary to disable output for other functions from this pin unless such
output is made intentionally.
(PF3) General purpose I/O port.
38
39
40
SO1/PF4
SC1/PF5
SI2/PF6
F
F
F
(SO1) UART1 data output pin.
This function is available when UART1 data output is enabled.
(PF4) General purpose I/O port.
This function is available when UART1 data output is disabled.
(SC1) Clock I/O pin for UART1.
Clock output is available when clock output of UART1 is enabled.
(PF5) General purpose I/O port.
This function is available when UART1 clock output is disabled.
(SI2) UART2 data input pin.
This pin is used for input during UART2 is in input operation, and it is
necessary to disable output for other functions from this pin unless such
output is made intentionally.
(PF6) General purpose I/O port.
41
8
SO2/PF7
F
(SO2) UART2 data output pin.
This function is available when UART2 data output is enabled.
(PF7) General purpose I/O port.
This function is available when UART2 data output is disabled.
(Continued)
MB91107/108
Circuit
type
Pin no.
Pin name
25
26
27
28
29
30
31
32
INT0/PG0
INT1/PG1
INT2/PG2
INT3/PG3
INT4/PG4
INT5/PG5
INT6/PG6
INT7/PG7
I
16
17
TRG0/PH0
TRG1/PH1
F
18
19
20
21
22
23
50
TRG2/PH2/
CS6
TRG3/PH3/
CS7
OCPA0/PH4
OCPA1/PH5
OCPA2/PH6
OCPA3/PH7
DACK2/PI0
Function
(INT0 to INT7) External interrupt request input pin.
This pin is used for input during corresponding interrupt is enabled, and
it is necessary to disable output for other functions from this pin unless
such output is made intentionally.
(PG0 and PG7) General purpose I/O port.
(TRG0 and TRG1) PWM timer external trigger input pin.
This function is available when PH0 and PH1 data outputs are disabled.
(PH0 and PH1) General purpose I/O port.
(TRG2 and TRG3) PWM timer external trigger input pin.
This function is available when PH2 and PH3 data outputs are disabled.
F
(PH2 and PH3) Can be configured as a I/O port when TRG2, TRG3,
CS6 and CS7 are not used.
Chip select 6 output (“L” active).
Chip select 7 output (“L” active).
F
(OCPA0 to OCPA3) PWM timer output pin.
This function is available when PWM timer output is enabled.
(PH4 to PH7) General purpose I/O port.
F
(DACK2) External transfer request acknowledge output pin for DMAC
(ch. 2). This function is available when transfer request output for DMAC
is enabled.
(PI0) General purpose I/O port.
This function is available when transfer request acknowledge output for
DMAC or DACK2 output is disabled.
(EOP2) EOP output pin for DMAC (ch.1).
This function is available when EOP output for DMAC is enabled.
51
EOP2/PI1/
ATG
F
(PI1) General purpose I/O port.
This function is available when transfer complete acknowledge output
for DMAC output is disabled.
(ATG)External trigger input pin for A/D converter.
This pin is used for input when external trigger is selected to cause A/D
converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.
12 to 15
AN0 to AN3
N
(AN0 to AN3) Analog input pins of A/D converter.
This function is available when AIC register is set to specify analog input
mode.
9
AVCC
Power supply pin (VCC) for A/D converter.
10
AVRH
Reference voltage input (high) for A/D converter.
Make sure to turn on and off this pin with potential of AVRH or more applied to VCC.
(Continued)
9
MB91107/108
(Continued)
Pin no.
Pin name
Circuit
type
Function
11
AVSS/ AVRL
Power supply pin (VSS) for A/D converter and reference voltage input pin
(low).
24, 55,
110
VCC
Power supply pin (VCC) for digital circuit.
Always three pins must be connected to the power supply
64
C
Bypass capacitor pin for internal capacitor.
Refer to the HANDLING DEVICES.
34, 52, 75,
101, 119
VSS
Earth level (VSS) for digital circuit.
Note : In most of the above pins, I/O port and resource I/O are multiplexed e.g. xxx/Pxxx. In case of conflict between
output of I/O port and resource I/O, priority is always given to the output of resource I/O.
■ DRAM CONTROL REGISTER
Pin
name
10
Data bus 16-bit mode
2CAS/1WR mode 1CAS/2WR mode
Data bus 8-bit
mode
RAS0
Area 4 RAS
Area 4 RAS
Area 4 RAS
RAS1
Area 5 RAS
Area 5 RAS
Area 5 RAS
CS0L
Area 4 CASL
Area 4 CAS
Area 4 CAS
CS0H
Area 4 CASH
Area 4 WEL
Area 4 CAS
CS1L
Area 5 CASL
Area 5 CAS
Area 5 CAS
CS1H
Area 5 CASH
Area 5 WEL
Area 5 CAS
DW0
Area 4 WE
Area 4 WEL
Area 4 WE
DW1
Area 5 WE
Area 5 WEL
Area 5 WE
Remarks
Correspondence of “L” “H” to lower address 1 bit (A0) in data bus 16-bit mode.
“L”: “0”
“H”: “1”
CASL : CAS which A0 corresponds to “0”
area
CASH : CAS which A0 corresponds to “1”
area
WEL : WE which A0 corresponds to “0”
area
WEH : WE which A0 corresponds to “1”
MB91107/108
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation feedback resistance: 1 MΩ
approx.
X1
Clock input
X0
A
STANDBY
CONTROL
VCC
P-channel type Tr.
B
• CMOS level
Hysteresis input
Without standby control
• With pull-up resistance
N-channel type Tr.
Diffused
resistor
VSS
Digital input
Digital output
• CMOS level I/O
With standby control
Digital output
C
Digital input
STANDBY
CONTROL
• Analog input
N
Analog input
(Continued)
11
MB91107/108
Type
Circuit
Remarks
Digital output
• CMOS level output
• CMOS level
Hysteresis input
With standby control
Digital output
F
Digital input
STANDBY
CONTROL
• CMOS level input
Without standby control
G
Digital input
• CMOS level
Hysteresis input
Without standby control
H
Digital input
Digital output
I
• CMOS level output
• CMOS level
Hysteresis input
Without standby control
Digital output
Digital input
(Continued)
12
MB91107/108
(Continued)
Type
Circuit
Remarks
• CMOS level output
Digital output
M
Digital output
Digital output
• CMOS level output
• CMOS level input
With standby control
• With pull-down resistance
Digital output
P
Pull-down
resistor control
Digital input
STANDBY
CONTROL
13
MB91107/108
■ HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over
rating across VCC and VSS may cause latchup.
This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.
2. Treatment of Pins
•Treatment of unused pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
•Handling the output pins
Connecting an output pin to the power supply, to another output pin, or to a large-capacitance load may cause
a large current to flow. Since letting it flow for an extended period of time degrades the device, be careful in
using the device not to exceed the maximum rating.
•Power supply pins
When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of
the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to
prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to
observe the total output current standard, connect all VCC and VSS pins to the power supply or GND.
It is preferred to connect VCC and VSS of MB91107 to power supply with minimal impedance possible.
It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC and
VSS at a position as close as possible to MB91107.
•Mode setting pins (MD0 to MD2)
Connect mode setting pins (MD0 to MD2) directly to VCC or VSS.
Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and
make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.
•Crystal oscillator circuit
Noises around X0 and X1 pins may cause malfunctions of MB91101. In designing the PC board, layout X0, X1
and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.
It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for
stable operation.
3. Notes on Use
•External reset input
The RST pin requires "L" level input for at least five machine cycles before the the internal circuitry can be
completely reset.
•External clock
To use an external clock, in principle, supply the X0 and X1 pins with a clock signal opposite in phase to the X0.
To use the STOP mode (oscillation stop mode) along with the external clock, in which the X1 pin stops with "H"
output, you should insert an external resistor of about 1 kilohm to prevent a collision between outputs.
Given the next page is an example of using an external clock.
14
MB91107/108
•Using an external clock (for normal use)
X0
X1
MB91108
MB91107
Note: To use the STOP mode (oscillation stop mode), insert a resistor to the X1 pin.
4. Notes on Internal DC-DC Regulator
• Since this product contains a regulator, be sure to supply current at 3.3 V to the VCC pin and insert a bypass
capacitor of about 0.1 µF to the C pin for the regulator.
• The A/D converter requires a 3.3-V power supply separately.
•Connecting to power supply
3.3 V
VCC
C
AVCC
AVRH
AVSS
GND
VSS
•Notes on using the STOP mode
The regulator built in this product stops in the STOP mode. If the regulator stops due to a malfunction caused
by noise or a fault in the power supply during normal operation, the internal 2.5-V power supply may go below
the lower limit of the guaranteed operating voltage range. When using the STOP mode with the internal regulator,
therefore, be sure to supply an auxiliary external power to prevent the 3.3-V power supply from coming down.
Even in that case, the internal regulator can be restarted by input of a reset signal (To restart the regulator, keep
the reset pin at the L level for at least the oscillation settling time).
15
MB91107/108
•Using STOP mode with 3.3 V power supply
3.3 V
2.4 kΩ
VCC
C
0.1 µF
VSS
7.6 kΩ
5. Turning on the Power Supply
•RST pin
When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power
supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycles, then set to “H” level.
•Pin Condition at Turning on the Power Supply
The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on
the power supply and then starting oscillation and then the operation of the internal regulator becomes stable.
So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz.
Take care that the pin condition may be output condition at initial unstable condition.
(With the MB91107, however, initalization can be achieved in less than about 42 ms after turning on the internal
power supply by maintaining the RST pin at "L" level.)
•Source Oscillation Input at Turning on the Power Supply
At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting.
•Hardware Stand-by at Turning on the Power Supply
When turning on the power supply with the HST pin being set to “L” level, the hardware doesn’t stand by. However
the HST pin becomes available after the reset cancellation, the HST pin must once be back to “H” level.
•Power on Reset
Make sure to make power on reset at turning on the power supply or returning on the power supply when the
power supply voltage is below the warranty range for normal operation.
16
MB91107/108
■ BLOCK DIAGRAM
FR CPU
Bit Search Module
I-bus
Instruction Cache
1 KB
(16 bit)
Harvard
Princeton
D-bus (32 bit)
Bus Converter
DMAC (8 ch)
DREQ0 DREQ1 DREQ2
DACK0 DACK1 DACK2
EOP0 EOP1 EOP2
Bus Controller
32 bit
16 bit
Bus Converter
C-bus
X0 X1
RST
HST
Clock Control Unit
(Watch Dog Timer)
RAM 128 KB (MB91107)
RAM 160 KB (MB91108)
DRAM Controller
INT0 ∼ INT7
NMI
RAS0
CS0L
CS0H
DW0
RAS1
CS1L
CS1H
DW1
Interrupt Control Unit
(32 bit)
AN0 ∼ AN3
AVCC AVRH
AVSS AVRL
ATG
D31 ∼ D16
A24 ∼ A00
RD
WR0 ∼ WR1
RDY
CLK
CS0 ∼ CS7
BRQ BGRNT
Port 0 ∼ Port B
10 bit A/D
Converter (4 ch)
Reload Timer (3 ch)
Port
R-bus (16 bit)
UART (3 ch)
with
Baud Rate Timer
PWM Timer (4 ch)
SI0 SI1 SI2
SO0 SO1 SO2
SC0 SC1 SC2
OCPA0 ∼ OCPA3
TRG0 ∼ TRG3
Note: Pins are display for functions (Actually some pins are multiplexer).
When using REALOS, time control should be done by using external interrupt or inner timer.
17
MB91107/108
■ CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory
space.
External ROM/external
bus mode
Internal ROM/external
bus mode
0000 0000H
I/O
I/O
I/O
I/O
Access inhibited
Access inhibited
External area
External area
Direct addressing area*1
0000 0400H
See “■ I/O MAP”
0000 0800H
0001 0000H
000C 0000H
Internal RAM
000E 0000H
External area
000E 8000H
0010 0000H
External area
←Internal 128 KB-RAM
Internal RAM ←Internal 32KB-RAM *2 (MB91108 only)
Access inhibited
External area
FFFF FFFFH
*1: The following areas on the memory space are assigned to direct addressing area for
I/O. In these areas, an address can be specified in a direct operand of a code.
Direct areas consists of the following areas dependent on accessible data sizes.
→
byte data access
0-0FFH
→
half word data access
0-1FFH
→
word data access
0-3FFH
*2: Access inhibited of MB91107
Note : Only the above mode exist in this product.
18
MB91107/108
2. Registers
The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose
registers on memory.
•Dedicated registers
Program counter (PC)
Program status (PS)
: 32-bit length, indicates the location of the instruction to be executed.
: 32-bit length, register for storing register pointer or condition codes.
: Holds top address of vector table used in EIT (Exceptional/Interrupt/
Table base register (TBR)
Trap processing.
Return pointer (RP)
: Holds address to resume operation after returning from a subroutine.
System stack pointer (SSP) : Indicates system stack space.
User's stack pointer (USP) : Indicates user’s stack space.
Multiplication/division result
: 32-bit length, register for multiplication/division.
register (MDH/MDL)
32 bit
32 bit
Initial value
Program counter
PC
XXXX XXXX Indeterminate
Program status
PS
Table base register
TBR
0 0 0F FC 0 0
Return pointer
RP
XXXX XXXX Indeterminate
System stack pointer
SSP
0000 0000
User’s stack pointer
USP
XXXX XXXX Indeterminate
Multiplication/division result register
MDH
XXXX XXXX Indeterminate
MDL
XXXX XXXX Indeterminate
ILM
SCR CCR
•Program status (PS)
The PS register is for holding program status and consists of a condition code register (CCR), a system condition
code register (SCR) and a interrupt level mask register (ILM).
31
PS
20
19
18
17
ILM4 to ILM0
ILM
16
10
9
D1 D0
SCR
8
7
6
5
4
3
2
1
0
T
S
I
N
Z
V
C
CCR
19
MB91107/108
•Condition code register (CCR)
S-flag : Specifies a stack pointer used as R15.
I-flag
: Controls user interrupt request enable/disable.
N-flag : Indicates sign bit when division result is assumed to be in the 2’s complement format.
Z-flag : Indicates whether or not the result of division was “0”.
: Assumes the operand used in calculation in the 2’s complement format and indicates whether or
V-flag
not overflow has occurred.
C-flag : Indicates if a carry or borrow from the MSB has occurred.
•System condition code register (SCR)
T-flag : Specifies whether or not to enable step trace trap.
•Interrupt level mask register (ILM)
ILM4 to ILM0 : Register for holding interrupt level mask value. The value held by this register is used as a
level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,
the interrupt request is accepted.
20
ILM4
ILM3
ILM2
ILM1
ILM0
Interrupt level
High-low
0
0
0
0
0
0
High
0
1
1
1
1
15
1
1
1
1
1
31
Low
MB91107/108
■ GENERAL-PURPOSE REGISTERS
R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator
and a memory access pointer.
32 bit
R0
R1
:
:
R12
R13
R14
R15
AC
FP
SP
Initial value
XXXX XXXXH
:
:
:
:
:
:
XXXX XXXXH
00 0 0 0 0 0 0 H
Of the above 16 registers, following registers have special functions. To support the special functions, part of
the instruction set has been sophisticated to have enhanced functions.
R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointer (SP)
Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value).
21
MB91107/108
■ SETTING MODE
1. Pin
•Mode setting pins and modes
Mode setting pins
Mode name
Reset vector
access area
External data bus
width
MD2
MD1
MD0
0
0
0
External vector
mode 0
External
8 bits
External
16 bits
Bus mode
External ROM/external
bus mode
0
0
1
External vector
mode 1
0
1
0
—
—
—
Inhibited
0
1
1
Internal vector mode
Internal
(Mode register)
Inhibited
1
—
—
—
—
—
Inhibited
2. Registers
•Mode data
MODR
Address : 0000 07FFH
M1
M0
∗
∗
∗
∗
∗
∗
Initial value
Access
XXXX XXXXB
W
Bus mode setting bit
Always write “0” except for M1 and M0.
•Bus mode setting bits and functions
M1
M0
Functions
0
0
Single-chip mode
0
1
Internal ROM/external bus mode
1
0
External ROM/external bus mode
1
1
—
Note : MB91107 places 128-KB internal RAM in the internal ROM area.
To use the 128-KB internal RAM, be sure to set ’01’.
22
Note
Inhibited
Inhibited
MB91107/108
■ I/O MAP
The remainder of this section contains a list of the registers for peripheral resources in memory space.
Address
Register
name
000001H
PDR2
Port 2 data registe
R/W
XXXXXXXXB
000004H
PDR7
Port 7 data registe
R/W
− − − − − − −XB
000005H
PDR6
Port 6 data registe
R/W
XXXXXXXXB
000008H
PDRB
Port B data registe
R/W
XXXXXXXXB
000009H
PDRA
Port A data registe
R/W
−XXXXXX−B
00000BH
PDR8
Port 8 data registe
R/W
000012H
PDRE
Port E data registe
R/W
XXXXXXXXB
000013H
PDRF
Port F data registe
R/W
XXXXXXXXB
000014H
PDRG
Port G data registe
R/W
XXXXXXXXB
000015H
PDRH
Port H data registe
R/W
XXXXXXX0B
000016H
PDRI
Port I data registe
R/W
− − − − − −XXB
00001CH
SSR0
Serial status register 0
R/W
0 0 0 0 1 − 0 0B
00001DH
SIDR0/
SODR0
Serial input data register 0/
Serial output data register
R/W
00001EH
SCR0
Serial control register 0
R/W
0 0 0 0 0 1 0 0B
00001FH
SMR0
Serial mode register 0
R/W
0 0 − − 0 − 0 0B
000020H
SSR1
Serial status register 1
R/W
0 0 0 0 1 − 0 0B
000021H
SIDR1/
SODR1
Serial input data register 1/
Serial output data register
R/W
000022H
SCR1
Serial control register 1
R/W
0 0 0 0 0 1 0 0B
000023H
SMR1
Serial mode register 1
R/W
0 0 − − 0 − 0 0B
000024H
SSR2
Serial status register 2
R/W
0 0 0 0 1 − 0 0B
000025H
SIDR2/
SODR2
Serial input data register 2/
Serial output data register
R/W
000026H
SCR2
Serial control register 2
R/W
0 0 0 0 0 1 0 0B
000027H
SMR2
Serial mode register 2
R/W
0 0 − − 0 − 0 0B
TMRLR0
16-bit reload register 0
W
TMR0
16-bit timer register 0
R
000028H
000029H
00002AH
00002BH
00002EH
00002FH
TMCSR0
Register name
16-bit reload timer
control status register 0
Access
Resource name
Port Data Register
UART0
UART1
UART2
Initial value
− −X− −XXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reload Timer 0
R/W
XXXXXXXXB
XXXXXXXXB
− − − − 0 0 0 0B
0 0 0 0 0 0 0 0B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
23
MB91107/108
Address
000030H
000031H
000032H
000033H
000036H
000037H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
00003EH
00003FH
000042H
000043H
000050H
Register
name
Register name
Access
16-bit reload register 1
W
TMR1
16-bit timer register 1
R
16-bit reload timer
control status register 1
ADCR
A/D converter data register
ADCS
A/D converte control status register
TMRLR2
TMR2
TMCSR2
XXXXXXXXB
R
R/W
W
16-bit timer register 2
R
Area select register 6
W
AMR6
Area mask register 6
W
ASR7
Area select register 7
W
AMR7
Area mask register 7
W
000059H
CS67
Output enable
R/W
000078H
000079H
UTIM0/
UTIMR0
U-TIMER register ch.0
U-TIMER reload register ch.0
R/W
00007BH
UTIMC0
U-TIMER control register ch.0
R/W
000052H
000053H
000054H
000055H
000056H
000057H
XXXXXXXXB
XXXXXXXXB
− − − − 0 0 0 0B
0 0 0 0 0 0 0 0B
− − − − − − XXB
A/D Converter
(Successive
approximation type)
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
Reload Timer 2
XXXXXXXXB
XXXXXXXXB
− − − − 0 0 0 0B
R/W
ASR6
000051H
Reload Timer 1
R/W
16-bit reload register 2
16-bit reload timer control status
register 2
Initial value
XXXXXXXXB
TMRLR1
TMCSR1
Resource name
0 0 0 0 0 0 0 0B
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
External Bus Interface 1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
− − − − 0 0 1 1B
0 0 0 0 0 0 0 0B
U-TIMER 0
0 0 0 0 0 0 0 0B
0 − − 0 0 0 0 1B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
24
MB91107/108
Address
00007CH
Register
name
Register name
Access
Resource name
Initial value
0 0 0 0 0 0 0 0B
00007DH
UTIM1/
UTIMR1
U-TIMER register ch.1
U-TIMER reload register ch.1
R/W
00007FH
UTIMC1
U-TIMER control register ch.1
R/W
000080H
000081H
UTIM2/
UTIMR2
U-TIMER register ch.2
U-TIMER reload register ch.2
R/W
000083H
UTIMC2
U-TIMER control register ch.2
R/W
0 − − 0 0 0 0 1B
000094H
EIRR
External interrup request register
R/W
0 0 0 0 0 0 0 0B
000095H
ENIR
Interrupt enabble register
R/W
ELVR
External interrup request level
setup register
R/W
0000D2H
DDRE
Port E data direction register
W
0000D3H
DDRF
Port F data direction register
W
000098H
000099H
U-TIMER 1
0 0 0 0 0 0 0 0B
0 − − 0 0 0 0 1B
0 0 0 0 0 0 0 0B
U-TIMER 2
External Interrupt/NMI
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Port E-I Data Direction
Register
0000D4H
DDRG
Port G data direction register
W
0000D5H
DDRH
Port H data direction register
W
0 0 0 0 0 0 0 1B
0000D6H
DDRI
Port I data direction register
W
− − − − − − 0 0B
GCN1
General control register 1
R/W
GCN2
General control register 2
R/W
0000DCH
0000DDH
0000DFH
0000E0H
0 0 0 0 0 0 0 0B
0 0 1 1 0 0 1 0B
0 0 0 1 0 0 0 0B
0 0 0 0 0 0 0 0B
1 1 1 1 1 1 1 1B
PTMR0
PWM timer register 0
R
PCSR0
PWM cycle setting register 0
W
PDUT0
PWM duty setting register 0
W
0000E6H
PCNH0
Control status register H 0
R/W
0000E7H
PCNL0
Control status register L 0
R/W
PTMR1
PWM timer register 1
R
PCSR
PWM cycle setting register 1
W
PDUT
PWM duty setting register 1
W
0000EEH
PCNH
Control status register H 1
R/W
0 0 0 0 0 0 0 −B
0000EFH
PCNL
Control status register L 1
R/W
0 0 0 0 0 0 0 0B
0000E1H
0000E2H
0000E3H
0000E4H
0000E5H
0000E8H
0000E9H
0000EAH
0000EBH
0000ECH
0000EDH
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
PWM
0 0 0 0 0 0 0 −B
0 0 0 0 0 0 0 0B
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
25
MB91107/108
Address
0000F0H
Register
name
Register name
Access
Resource name
Initial value
1 1 1 1 1 1 1 1B
PTMR2
PWM timer register 2
R
PCSR2
PWM cycle setting register 2
W
PDUT2
PWM duty setting register 2
W
0000F6H
PCNH2
Control status register H 2
R/W
0000F7H
PCNL2
Control status register L 2
R/W
PTMR3
PWM timer register 3
R
PCSR3
PWM cycle setting register 3
W
PDUT3
PWM duty setting register 3
W
0000FEH
PCNH3
Control status register H 3
R/W
0 0 0 0 0 0 0 −B
0000FFH
PCNL3
Control status register L 3
R/W
0 0 0 0 0 0 0 0B
0000F1H
0000F2H
0000F3H
0000F4H
0000F5H
0000F8H
0000F9H
0000FAH
0000FBH
0000FCH
0000FDH
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 −B
PWM
000202H
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
000200H
000201H
0 0 0 0 0 0 0 0B
DPDP
DMAC parameter descriptor point
XXXXXXXXB
R/W
XXXXXXXXB
000203H
X 0 0 0 0 0 0 0B
000204H
0 0 0 0 0 0 0 0B
000205H
000206H
DACSR
DMAC control status register
R/W
DMAC
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
000207H
0 0 0 0 0 0 0 0B
000208H
XXXXXXXXB
000209H
00020AH
DATCR
DMAC pin control register
XX 0 0 0 0 0 0B
R/W
XX 0 0 0 0 0 0B
00020BH
XX 0 0 0 0 0 0B
0003E4H
− − − − − − − −B
0003E5H
0003E6H
ICHCR
Instruction cache
R/W
Instruction Cache
0003E7H
− − − − − − − −B
− − − − − − − −B
− − 0 0 0 0 0 0B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
26
MB91107/108
Address
Register
name
Register name
Access
Resource name
0003F0H
0003F1H
0003F2H
Initial value
XXXXXXXXB
BSD0
Bit search module
zero-detection data register
XXXXXXXXB
W
XXXXXXXXB
0003F3H
XXXXXXXXB
0003F4H
XXXXXXXXB
0003F5H
0003F6H
BSD1
Bit search module
single-detection data register
0003F7H
0003FAH
XXXXXXXXB
Bit Search Module
0003F8H
0003F9H
XXXXXXXXB
R/W
BSDC
Bit search module
transition-detection data register
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
W
XXXXXXXXB
0003FBH
XXXXXXXXB
0003FCH
XXXXXXXXB
0003FDH
0003FEH
BSRR
Bit search module result register
XXXXXXXXB
R
XXXXXXXXB
0003FFH
XXXXXXXXB
000400H
ICR00
Interrupt control register 0
− − − 1 1 1 1 1B
000401H
ICR01
Interrupt control register 1
− − − 1 1 1 1 1B
000402H
ICR02
Interrupt control register 2
− − − 1 1 1 1 1B
000403H
ICR03
Interrupt control register 3
− − − 1 1 1 1 1B
000404H
ICR04
Interrupt control register 4
− − − 1 1 1 1 1B
000405H
ICR05
Interrupt control register 5
− − − 1 1 1 1 1B
000406H
ICR06
Interrupt control register 6
− − − 1 1 1 1 1B
000407H
ICR07
Interrupt control register 7
− − − 1 1 1 1 1B
000408H
ICR08
Interrupt control register 8
000409H
ICR09
Interrupt control register 9
− − − 1 1 1 1 1B
00040AH
ICR10
Interrupt control register 10
− − − 1 1 1 1 1B
00040BH
ICR11
Interrupt control register 11
− − − 1 1 1 1 1B
00040CH
ICR12
Interrupt control register 12
− − − 1 1 1 1 1B
00040DH
ICR13
Interrupt control register 13
− − − 1 1 1 1 1B
00040EH
ICR14
Interrupt control register 14
− − − 1 1 1 1 1B
00040FH
ICR15
Interrupt control register 15
− − − 1 1 1 1 1B
000410H
ICR16
Interrupt control register 16
− − − 1 1 1 1 1B
R/W
Interrupt Controller
− − − 1 1 1 1 1B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
27
MB91107/108
Address
Register
name
000411H
ICR17
Interrupt control register17
− − − 1 1 1 1 1B
000412H
ICR18
Interrupt control register 18
− − − 1 1 1 1 1B
000413H
ICR19
Interrupt control register 19
− − − 1 1 1 1 1B
000414H
ICR20
Interrupt control register 20
− − − 1 1 1 1 1B
000415H
ICR21
Interrupt control register 21
− − − 1 1 1 1 1B
000416H
ICR22
Interrupt control register 22
− − − 1 1 1 1 1B
000417H
ICR23
Interrupt control register 23
− − − 1 1 1 1 1B
000418H
ICR24
Interrupt control register 24
− − − 1 1 1 1 1B
000419H
ICR25
Interrupt control register 25
− − − 1 1 1 1 1B
00041AH
ICR26
Interrupt control register 26
− − − 1 1 1 1 1B
00041BH
ICR27
Interrupt control register 27
− − − 1 1 1 1 1B
00041CH
ICR28
Interrupt control register 28
− − − 1 1 1 1 1B
00041DH
ICR29
Interrupt control register 29
− − − 1 1 1 1 1B
00041EH
ICR30
Interrupt control register 30
− − − 1 1 1 1 1B
00041FH
ICR31
Interrupt control register 31
− − − 1 1 1 1 1B
000420H
ICR32
Interrupt control register 32
000421H
ICR33
Interrupt control register 33
− − − 1 1 1 1 1B
000422H
ICR34
Interrupt control register 34
− − − 1 1 1 1 1B
000423H
ICR35
Interrupt control register 35
− − − 1 1 1 1 1B
000424H
ICR36
Interrupt control register 36
− − − 1 1 1 1 1B
000425H
ICR37
Interrupt control register 37
− − − 1 1 1 1 1B
000426H
ICR38
Interrupt control register 38
− − − 1 1 1 1 1B
000427H
ICR39
Interrupt control register 39
− − − 1 1 1 1 1B
000428H
ICR40
Interrupt control register 40
− − − 1 1 1 1 1B
000429H
ICR41
Interrupt control register 41
− − − 1 1 1 1 1B
00042AH
ICR42
Interrupt control register 42
− − − 1 1 1 1 1B
00042BH
ICR43
Interrupt control register 43
− − − 1 1 1 1 1B
00042CH
ICR44
Interrupt control register 44
− − − 1 1 1 1 1B
00042DH
ICR45
Interrupt control register 45
− − − 1 1 1 1 1B
00042EH
ICR46
Interrupt control register 46
− − − 1 1 1 1 1B
00042FH
ICR47
Interrupt control register 47
− − − 1 1 1 1 1B
000430H
DICR
Delayed interrupt
R/W
000431H
HRCL
Holding request withdrawal
request level set register
R/W
Register name
Access
R/W
Resource name
Interrupt Controller
Delayed Interrupt Controller
Register
Initial value
− − − 1 1 1 1 1B
− − − − − − − 0B
− − − 1 1 1 1 1B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
28
MB91107/108
Address
Register
name
000480H
RSRR/
WTCR
Reset cause register/watchdog
cycle control register
R/W
1 XXXX − 0 0B
000481H
STCR
Stand-by controller register
R/W
0 0 0 1 1 1 − −B
000482H
PDRR
DMA controller request prohibit
resister
R/W
000483H
CTBR
Timebase timer clear register
000484H
GCR
Gear controller register
000485H
WPR
000488H
Register name
Access
Resource name
Clock Controller
Initial value
− − − − 0 0 0 0B
W
XXXXXXXXB
R/W
1 1 0 0 1 1 − 1B
Watchdog reset generation
postpone register
W
XXXXXXXXB
PCTR
PLL controller register
W
000601H
DDR2
Port 2 data direction register
W
0 0 0 0 0 0 0 0B
000604H
DDR7
Port 7 data direction register
W
− − − − − − − 0B
000605H
DDR6
Port 6 data direction register
W
000608H
DDRB
Port B data direction register
W
000609H
DDRA
Port A data direction register
W
− 0 0 0 0 0 0 −B
00060BH
DDR8
Port 8 data direction register
W
− −0 0 0 0 0 0B
ASR1
Area selection register 1
W
AMR1
Area mask register 1
W
ASR2
Area selection register 2
W
AMR2
Area mask register 2
W
ASR3
Area selection register 3
W
AMR3
Area mask register 3
W
ASR4
Area selection register 4
W
AMR4
Area mask register 4
W
ASR5
Area selection register 5
W
00060CH
00060DH
00060EH
00060FH
000610H
000611H
000612H
000613H
000614H
000615H
000616H
000617H
000618H
000619H
00061AH
00061BH
00061CH
00061DH
PLL Controller
Port Direction Register
0 0 − − 0 − − −B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 1 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
External Bus Interface
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 11B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 1B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
29
MB91107/108
(Continued)
Address
00061EH
Register
name
Register name
Access
Resource name
0 0 0 0 0 0 0 0B
AMR5
Area mask register 5
W
000620H
AMD0
Area mode register 0
R/W
− − − 0 0 1 1 1B
000621H
AMD1
Area mode register 1
R/W
0 − − 0 0 0 0 0B
000622H
AMD32
Area mode register 32
R/W
0 0 0 0 0 0 0 0B
000623H
AMD4
Area mode register 4
R/W
0 − − 0 0 0 0 0B
000624H
AMD5
Area mode register 5
R/W
0 − − 0 0 0 0 0B
000625H
DSCR
DRAM signal control register
W
0 0 0 0 0 0 0 0B
RFCR
Refresh control register
EPCR0
External pin control register 0
W
EPCR1
External pin control register 1
W
DMCR4
DRAM control register 4
R/W
DMCR5
DRAM control register 5
R/W
00061FH
000626H
000627H
000628H
000629H
00062AH
00062BH
00062CH
00062DH
00062EH
00062FH
0007FEH
LER
0007FFH
MODR
R/W
Little endian register
W
Mode register
W
0 0 0 0 0 0 0 0B
External Bus Interface
Note : RMW-type instructions (RMW: Read modify write)
AND
Rj, @Ri
OR
Rj, @Ri
ANDH
Rj, @Ri
ORH Rj, @Ri
ANDB
Rj, @Ri
ORB Rj, @Ri
BANDL #u4, @Ri
BORL #u4, @Ri
BANDH #u4, @Ri
BORH #u4, @Ri
− − XXXXXXB
0 0 − − − 0 0 0B
− − − − 1 1 0 0B
− 1 1 1 1 1 1 1B
− − − − − − − 1B
1 1 1 1 1 1 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 −B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 −B
Little Endian Registor
Mode Register
Note: Do not execute an RMW-type instruction for any register containing a write-only bit.
30
Initial value
EOR
EORH
EORB
BEORL
BEORH
Rj, @Ri
Rj, @Ri
Rj, @Ri
#u4, @Ri
#u4, @Ri
− − − − − 0 0 0B
XXXXXXXXB
MB91107/108
■ INTERRUPT CAUSES, INTERRUPT VECTORS
AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes
Interrupt number
Decimal Hexadecimal
Interrupt level
Register
Offset
TBR default
address
Reset
0
00
3FCH
0FFFFCH
Reserved for system
1
01
3F8H
0FFFF8H
Reserved for system
2
02
3F4H
0FFFF4H
Reserved for system
3
03
3F0H
0FFFF0H
Reserved for system
4
04
3ECH
0FFFECH
Reserved for system
5
05
3E8H
0FFFE8H
Reserved for system
6
06
3E4H
0FFFE4H
Reserved for system
7
07
3E0H
0FFFE0H
Reserved for system
8
08
3DCH
0FFFDCH
Reserved for system
9
09
3D8H
0FFFD8H
Reserved for system
10
0A
3D4H
0FFFD4H
Reserved for system
11
0B
3D0H
0FFFD0H
Reserved for system
12
0C
3CCH
0FFFCCH
Reserved for system
13
0D
3C8H
0FFFC8H
Exception for undefined instruction
14
0E
3C4H
0FFFC4H
NMI request
15
0F
FH fixed
3C0H
0FFFC0H
External interrupt 0
16
10
ICR00
3BCH
0FFFBCH
External interrupt 1
17
11
ICR01
3B8H
0FFFB8H
External interrupt 2
18
12
ICR02
3B4H
0FFFB4H
External interrupt 3
19
13
ICR03
3B0H
0FFFB0H
UART0 receive complete
20
14
ICR04
3ACH
0FFFACH
UART1 receive complete
21
15
ICR05
3A8H
0FFFA8H
UART2 receive complete
22
16
ICR06
3A4H
0FFFA4H
UART0 transmit complete
23
17
ICR07
3A0H
0FFFA0H
UART1 transmit complete
24
18
ICR08
39CH
0FFF9CH
UART2 transmit complete
25
19
ICR09
398H
0FFF98H
DMAC0 (complete, error)
26
1A
ICR10
394H
0FFF94H
DMAC1 (complete, error)
27
1B
ICR11
390H
0FFF90H
DMAC2 (complete, error)
28
1C
ICR12
38CH
0FFF8CH
DMAC3 (complete, error)
29
1D
ICR13
388H
0FFF88H
DMAC4 (complete, error)
30
1E
ICR14
384H
0FFF84H
DMAC5 (complete, error)
31
1F
ICR15
380H
0FFF80H
DMAC6 (complete, error)
32
20
ICR16
37CH
0FFF7CH
DMAC7 (complete, error)
33
21
ICR17
378H
0FFF78H
(Continued)
31
MB91107/108
(Continued)
Interrupt causes
Interrupt number
Decimal Hexadecimal
Register
Offset
TBR default
address
A/D converter (successive
approximation conversion type)
34
22
ICR18
374H
0FFF74H
Reload timer 0
35
23
ICR19
370H
0FFF70H
Reload timer 1
36
24
ICR20
36CH
0FFF6CH
Reload timer 2
37
25
ICR21
368H
0FFF68H
PWM0
38
26
ICR22
364H
0FFF64H
PWM1
39
27
ICR23
360H
0FFF60H
PWM2
40
28
ICR24
35CH
0FFF5CH
PWM3
41
29
ICR25
358H
0FFF58H
U-TIMER0
42
2A
ICR26
354H
0FFF54H
U-TIMER1
43
2B
ICR27
350H
0FFF50H
U-TIMER2
44
2C
ICR28
34CH
0FFF4CH
Reserved for system
45
2D
ICR29
348H
0FFF48H
Reserved for system
46
2E
ICR30
344H
0FFF44H
Reserved for system
47
2F
ICR31
340H
0FFF40H
Reserved for system
48
30
ICR32
33CH
0FFF3CH
Reserved for system
49
31
ICR33
338H
0FFF38H
Reserved for system
50
32
ICR34
334H
0FFF34H
Reserved for system
51
33
ICR35
330H
0FFF30H
Reserved for system
52
34
ICR36
32CH
0FFF2CH
Reserved for system
53
35
ICR37
328H
0FFF28H
Reserved for system
54
36
ICR38
324H
0FFF24H
Reserved for system
55
37
ICR39
320H
0FFF20H
Reserved for system
56
38
ICR40
31CH
0FFF1CH
Reserved for system
57
39
ICR41
318H
0FFF18H
Reserved for system
58
3A
ICR42
314H
0FFF14H
Reserved for system
59
3B
ICR43
310H
0FFF10H
Reserved for system
60
3C
ICR44
30CH
0FFF0CH
Reserved for system
61
3D
ICR45
308H
0FFF08H
Reserved for system
62
3E
ICR46
304H
0FFF04H
Delayed interrupt cause bit
63
3F
ICR47
300H
0FFF00H
Reserved for system (used in REALOS*)
64
40
2FCH
0FFEFCH
Reserved for system (used in REALOS*)
65
41
2F8H
0FFEF8H
66 to 255
42 to FF
2F4H to
000H
0FFEF4H to
0FFC00H
Used in INT instructions
*: When using in REALOS/FR, interrupt 0x40, 0x41 for system code.
32
Interrupt level
MB91107/108
■ PERIPHERAL RESOURCES
1. I/O Ports
There are 2 types of I/O port register structure; PDR (port data register) and DDR (data direction register) .
• For input (DDR = “0”) setting;
PDR reading operation: reads level of corresponding external pin.
PDR writing operation: writes set value to PDR.
• For output (DDR = “1”) setting;
PDR reading operation: reads PDR value.
PDR writing operation: outputs PDR value to corresponding external pin.
(1) Register configuration
•Port Data Register (PDR)
Address
bit 7
bit 0
Initial value
Access
000001H
PDR2
XXXXXXXXB
R/W
000005H
PDR6
XXXXXXXXB
R/W
000004H
PDR7
- - - - - - - XB
R/W
00000BH
PDR8
- - X - - XXXB
R/W
000009H
PDRA
- XXXXXX -B
R/W
000008H
PDRB
XXXXXXXXB
R/W
000012H
PDRE
XXXXXXXXB
R/W
000013H
PDRF
XXXXXXXXB
R/W
000014H
PDRG
XXXXXXXXB
R/W
000015H
PDRH
XXXXXXX0B
R/W
000016H
PDRI
- - - - - - XXB
R/W
R/W : Readable and writable
: Unused
X
: Indeterminate
33
MB91107/108
•Data Direction Register (DDR)
Address
bit 7
bit 0
Access
000601H
DDR2
0 0 0 0 0 0 0 0B
W
000605H
DDR6
0 0 0 0 0 0 0 0B
W
000604H
DDR7
- - - - - - - 0B
W
00060BH
DDR8
- - 0 - - 0 0 0B
W
000609H
DDRA
- 0 0 0 0 0 0 -B
W
000608H
DDRB
0 0 0 0 0 0 0 0B
W
0000D2H
DDRE
0 0 0 0 0 0 0 0B
W
0000D3H
DDRF
0 0 0 0 0 0 0 0B
W
0000D4H
DDRG
0 0 0 0 0 0 0 0B
W
0000D5H
DDRH
0 0 0 0 0 0 0 1B
W
0000D6H
DDRI
- - - - - - 0 0B
W
W
-
34
Initial value
: Write only
: Unused
MB91107/108
(2) Block diagram
Data Bus
Resource input
0
1
PDR read
0
pin
PDR
Resource
output
1
Resource output enable
DDR
PDR : Port Data Register
DDR : Data Direction Register
35
MB91107/108
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.
DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system.
• 8 channels
• Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer
• Transfer all through the area
• Max. 65536 of transfer cycles
• Interrupt function right after the transfer
• Selectable for address transfer increase/decrease by the software
• External transfer request input pin, external transfer request accept output pin, external transfer complete
output pin three pins for each
(1) Register configuration
DMAC (DMAC internal registers)
Address
bit 31
bit 0
DMAC parameter descriptor point
DPDP
000200H
DPDP
DMAC control status register
000204H
DACSR
DACSR
DATCR
DATCR
DMAC pin control register
000208H
RAM (DMA descriptor)
bit 31
bit 0
DPDP + 0H
DMA
ch-0
descriptor
DPDP + 0CH
DMA
ch-1
descriptor
:
:
DPDP + 54H
DMA
ch-7
descriptor
36
MB91107/108
(2) Block diagram
3
DREQ0 ∼DREQ2
3
Edge/level
detection circuit
3
3
Sequencer
Inner resource
Transfer request
8
DACK0 ∼ DACK2
EOP0 ∼ EOP2
Interrupt request
5
Data buffer
Switcher
DACSR
Data bus
DPDP
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
37
MB91107/108
3. UART
The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features.
The MB91107 consists of 3 channels of UART.
• Full double double buffer
• Both a synchronous (start-stop system) communication and CLK synchronous communication are available.
• Supporting multi-processor mode
• Perfect programmable baud rate
Any baud rate can be set by internal timer (refer to section “4. U-TIMER”).
• Any baud rate can be set by external clock.
• Error checking function (parity, framing and overrun)
• Transfer signal: NRZ code
• Enable DMA transfer/start by interrupt.
(1) Register configuration
•Serial control register
Address
SCR0 : 00001EH
SCR1 : 000022H
SCR2 : 000026H
bit 15
bit 8 bit 7
SCR0 to SCR2
bit 0
(SMR)
Initial value
0 0 0 0 010 0B
Access
R/W
•Serial mode register
Address
SMR0 : 00001FH
SMR1 : 000023H
SMR2 : 000027H
bit 15
bit 8 bit 7
bit 0
SMR0 to SMR2
Initial value Access
0 0 - - 0 - 0 0B
R/W
bit 15
bit 8 bit 7
bit 0
SSR0 to SSR2
(SIDR/SODR)
Initial value Access
0 0 0 01 - 0 0B
R/W
bit 15
(SSR)
bit 8 bit 7
bit 0
(SIDR/SODR)
Initial value Access
XXXXXXXXB
R
(SSR)
bit 8 bit 7
bit 0
(SIDR/SODR)
Initial value Access
XXXXXXXXB
R
(SCR)
•Serial status register
Address
SSR0 : 00001CH
SSR1 : 000020H
SSR2 : 000024H
•Serial input data register
Address
SIDR0 : 00001DH
SIDR1 : 000021H
SIDR2 : 000025H
•Serial output data register
Address
SIDR0 : 00001DH
SIDR1 : 000021H
SIDR2 : 000025H
bit 15
R/W : Readable and writable
R
: Read only
W : Write only
38
X
: Unused
: Indeterminate
MB91107/108
(2) Block diagram
Control signal
Receive interrupt
( to CPU)
SC (clock)
Clock
select
circuit
From U-TIMER
Transmit interrupt
( to CPU)
Transmit clock
Receive clock
From external clock
SC
Receive control
circuit
SI
(Receive data)
Transmit control
circuit
Start bit detect
circuit
Transmit bit
counter
Receive bit
counter
Transmit start
circuit
Receive parity
counter
Transmit parity
counter
SO
(Transmit data)
Receive status
judge circuit
Receive shifter
Receive
complete
Receive error
generate signal for DMA
( to DMAC)
Transmit shifter
Transmit
start
SIDR
SODR
R - BUS
MD1
MD0
SCR
SMR
Register
Register
CS0
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
Register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
39
MB91107/108
4. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and
reload value of U-TIMER allows flexible setting of baud rate.
The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.
The MB91107 has 3 channel U-TIMER embedded on the chip. An interval of up to 216 × φ can be counted.
(1) Register configuration
• U-TIMER register ch 0 to ch 2
Address
bit 15
UTIM0 : 000078H
UTIM1 : 00007CH
UTIM2 : 000080H
bit 0
Initial value Access
0 0 0 0 0 0 0 0B
R
0 0 0 0 0 0 0 0B
bit 0
Initial value Access
0 0 0 0 0 0 0 0B
W
0 0 0 0 0 0 0 0B
bit 0
UTIMC0 to UTIMC2
Initial value Access
0 - - 0 0 0 0 1B R/W
UTIM0 to UTIM2
• U-TIMER reload register ch 0 to ch 2
Address
bit 15
UTIM0 : 000078H
UTIM0 to UTIM2
UTIM1 : 00007CH
UTIM2 : 000080H
• U-TIMER control register ch 0 to ch 2
Address
bit 15
UTIM0 : 00007BH
(Vacancy)
UTIM1 : 00007FH
UTIM2 : 000083H
R/W
R
W
-
40
: Readable and writable
: Read only
: Write only
: Unused
MB91107/108
(2) Block diagram
15
0
UTIMR (reload register)
load
15
0
UTIM (timer)
clock
underflow
φ
control
(Peripheral clock)
f.f.
to UART
41
MB91107/108
5. PWM Timer
The PWM timer can output high accurate PWM waves efficiently.
MB91101 has inner 4-channel PWM timers, and has the following features.
• Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit
compare resister with a buffer for duty setting, and a pin controller.
• The count clock of a 16-bit down counter can be selected from the following four inner clocks.
• Inner clock φ, φ/4, φ/16, φ/64
• The counter value can be initialized “FFFFH” by the resetting or the counter borrow.
• PWM output (each channel)
• Resister description
Cycle setting register: Reload data register with a buffer
Duty factor setting register: Compare register with a buffer
Transfer from the buffers uses the counter borrow method.
• Pin control outline
Set to ’1’ at a duty factor match. (Preferential)
Set to ’0’ at a counter borrow.
The output value fixed mode is available, which makes all ’L’ (or ’H’) output easy.
The polarity can also be specified.
• Interrupt requests can be generated by selected a combination of events:
This timer is activated.
A counter borrow is generated (cycle match).
A duty factor match is generated.
A counter borrow is generated (cycle match) or a duty factor match is generated.
DMA transfer can be invoked by the above interrupt request.
• Simultaneous activation of multiple channels of the PWM timer can be set by software or by using another
interval timer. Restarting the PWM timer during operation can also be set.
42
MB91107/108
(1) Register configuration
Address
bit 15
bit 0
0000DCH
GCN1
0000DFH
GCN2
Initial value
Access
0 0 1 1 0 0 1 0B
0 0 0 1 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
General control register 1
General control register 2
0000E0H
PTMR
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
R
ch0 timer register
0000E2H
PCSR
XXXXXXXXB
XXXXXXXXB
W
ch0 cycle setting register
0000E4H
PDUT
XXXXXXXXB
XXXXXXXXB
W
ch0 duty setting register
0 0 0 0 0 0 0 -B
0 0 0 0 0 0 0 0B
R/W
0000E6H
PCNH
PCNL
ch0 control status register
0000E8H
PTMR
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
R
ch1 timer register
0000EAH
PCSR
XXXXXXXXB
XXXXXXXXB
W
ch1 cycle setting register
0000ECH
PDUT
XXXXXXXXB
XXXXXXXXB
W
ch1 duty setting register
0 0 0 0 0 0 0 -B
0 0 0 0 0 0 0 0B
R/W
0000EEH
PCNH
PCNL
ch1 control status register
0000F0H
PTMR
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
R
ch2 timer register
0000F2H
PCSR
XXXXXXXXB
XXXXXXXXB
W
ch2 cycle setting register
0000F4H
PDUT
XXXXXXXXB
XXXXXXXXB
W
ch2 duty setting register
0 0 0 0 0 0 0 -B
0 0 0 0 0 0 0 0B
R/W
0000F6H
PCNH
PCNL
ch2 control status register
0000F8H
PTMR
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
R
0000FAH
PCSR
XXXXXXXXB
XXXXXXXXB
(W)
ch3 cycle setting register
0000FCH
PDUT
XXXXXXXXB
XXXXXXXXB
W
ch3 duty setting register
0 0 0 0 0 0 0 -B
0 0 0 0 0 0 0 0B
R/W
0000FEH
PCNH
PCNL
R/W : Readable and writable
R : Read only
W : Write only
X
ch3 timer register
ch3 control status register
: Unused
: Indeterminate
43
MB91107/108
(2) Block Diagram
•General construction
16-bit reload
timer ch0
General control
register 1
(cause
selection)
16-bit reload
timer ch1
4
General control register 2
4
External TRG0 to TRG3
TRG input
PWM timer ch0
PWM0
TRG input
PWM timer ch1
PWM1
TRG input
PWM timer ch2
PWM2
TRG input
PWM timer ch3
PWM3
•For one channel
PCSR
PDUT
Prescaler
1/1
1/4
1/16
1/64
ck
cmp
Load
16-bit down counter
Start
Borrow
PPG
mask
S
Q
PWM output
R
Peripheral clock
Enable
TRG input
Edge
detect
Soft trigger
44
Interrupt
selection
Reverse
bit
IRQ
MB91107/108
6. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal
count clock and control registers.
Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock).
The DMA transfer can be started by the interruption.
The MB91107 consists of 3 channels of the 16-bit reload timer.
(1) Register configuration
•Control status register
Address
TMCSR0 : 00002EH
TMCSR1 : 000036H
TMCSR2 : 000042H
bit 15
bit 0
Initial value
Access
- - - - 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
bit 0
Initial value
Access
XXXXXXXXB
R
XXXXXXXXB
bit 0
Initial value
Access
XXXXXXXXB
W
XXXXXXXXB
TMCSR0 to TMCSR2
•16-bit timer register
Address
TMR0 : 00002AH
TMR1 : 000032H
TMR2 : 00003EH
bit 15
TMR0 to TMR2
•16-bit reload register
Address
TMRLR0 : 000028H
TMRLR1 : 000030H
TMRLR2 : 00003CH
bit 15
TMRLR0 to TMRLR2
R/W : Readable and writable
R
: Read only
W : Write only
X
: Unused
: Indeterminate
45
MB91107/108
(2) Block diagram
16
16-bit reload register
8
R
|
B
U
S
Reload
RELD
16
16-bit down counter
OUTE
UF
OUTL
2
OUT
CTL.
GATE
INTE
2
Clock selector
UF
CSL1
CNTE
IRQ
CSL0
2
TRG
Retrigger
IN CTL.
EXCK
φ
φ
φ
21
23
25
Prescaler
clear
PWM (ch 0, ch 1)
A/D (ch 2)
3
MOD2
MOD1
Internal clock
3
46
MOD0
MB91107/108
7. Bit Search Module
The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and
returns locations of the transitions.
(1) Register configuration
Address
bit 31
bit 0
0003F0H
BSD0
0003F4H
BSD1
0003F8H
BSDC
0003FCH
BSRR
Initial value
Access
XXXXXXXXXXXXXXXXB
W
Zero-detection data register
XXXXXXXXXXXXXXXXB
XXXXXXXXXXXXXXXXB
R/W Single-detection data register
XXXXXXXXXXXXXXXXB
XXXXXXXXXXXXXXXXB
W
Detection data register
XXXXXXXXXXXXXXXXB
XXXXXXXXXXXXXXXXB
R
Search result register
XXXXXXXXXXXXXXXXB
R/W
R
W
X
: Readable and writable
: Read only
: Write only
: Indeterminate
(2) Block diagram
D-BUS
Input latch
Address
decoder
Detection
mode
Single-detection data register
Bit search circuit
Search result
47
MB91107/108
8. A/D Converter (Successive Approximation Conversion Type)
The A/D converter is the module which converts an analog input voltage to a digital value, and it has following
features.
• Minimum converting time: 5.6 µs/ch. (system clock: 25 MHz)
• Inner sample and hold circuit
• Resolution: 10 bits
• Analog input can be selected from 4 channels by program.
Single convert mode: 1 channel is selected and converted.
Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable.
Continuous convert mode: Converting the specified channel repeatedly.
Stop convert mode: After converting one channel then stop and wait till next activation synchronising at
the beginning of conversion can be peformed.
• DMA transfer operation is available by interruption.
• Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer
(rising edge).
(1) Register configuration
•A/D converter control register
Address
00003AH
bit 15
bit 0
Initial value Access
0 0 0 0 0 0 0 0B R/W
0 0 0 0 0 0 0 0B
bit 0
Initial value Access
- - - - - -XXB
R
XXXXXXXXB
ADCS
•A/D converter data register
Address
000038H
bit 15
ADCR
R/W : Readable and writable
R
: Read only
X
: Indeterminate
48
MB91107/108
(2) Block diagram
AVCC
AVRH
AVSS
Internal voltage
generator
AN0
AN1
AN2
AN3
Input circuit
MPX
Successive approximation register
R
|
B
U
S
Comparator
Decoder
Sample & hold circuit
Data register
ADCR
A/D control register
Trigger start
ADCS
ATG
TIM0
(Internal connection)
(Reload timer ch2)
Timer start
φ
Operating clock
Prescaler
(Peripheral clock)
49
MB91107/108
9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
•Hardware configuration
This module consists of the following components:
• ICR register
• Interrupt priority evaluation circuit
• Interrupt level/interrupt number (vector) generator
• HOLD request cancel request generator
•Main Features
The major functions of this module are listed below:
• NMI request/interrupt request detection
• Priority evaluation (interrupt level and number)
• Transfer of interrupt level as evaluation factor (to the CPU)
• Transfer of interrupt number as evaluation factor (to the CPU)
• Instruction of returning from the stop mode by NMI/interrupt generation
• Generating a request to cancel the HOLD request to the bus master
50
MB91107/108
(1) Register configuration
•Interrupt control register 0 to 47
Address
000400H
bit 7
ICR00
bit 0
Initial value Access
- - - 11111B
R/W
Address
000419H
000401H
ICR01
- - - 11111B
R/W
000402H
ICR02
- - - 11111B
000403H
ICR03
000404H
bit 7
ICR25
bit 0
Initial value Access
- - - 11111B R/W
00041AH
ICR26
- - - 11111B
R/W
R/W
00041BH
ICR27
- - - 11111B
R/W
- - - 11111B
R/W
00041CH
ICR28
- - - 11111B
R/W
ICR04
- - - 11111B
R/W
00041DH
ICR29
- - - 11111B
R/W
000405H
ICR05
- - - 11111B
R/W
00041EH
ICR30
- - - 11111B
R/W
000406H
ICR06
- - - 11111B
R/W
00041FH
ICR31
- - - 11111B
R/W
000407H
ICR07
- - - 11111B
R/W
000420H
ICR32
- - - 11111B
R/W
000408H
ICR08
- - - 11111B
R/W
000421H
ICR33
- - - 11111B
R/W
000409H
ICR09
- - - 11111B
R/W
000422H
ICR34
- - - 11111B
R/W
00040AH
ICR10
- - - 11111B
R/W
000423H
ICR35
- - - 11111B
R/W
00040BH
ICR11
- - - 11111B
R/W
000424H
ICR36
- - - 11111B
R/W
00040CH
ICR12
- - - 11111B
R/W
000425H
ICR37
- - - 11111B
R/W
00040DH
ICR13
- - - 11111B
R/W
000426H
ICR38
- - - 11111B
R/W
00040EH
ICR14
- - - 11111B
R/W
000427H
ICR39
- - - 11111B
R/W
00040FH
ICR15
- - - 11111B
R/W
000428H
ICR40
- - - 11111B
R/W
000410H
ICR16
- - - 11111B
R/W
000429H
ICR41
- - - 11111B
R/W
000411H
ICR17
- - - 11111B
R/W
00042AH
ICR42
- - - 11111B
R/W
000412H
ICR18
- - - 11111B
R/W
00042BH
ICR43
- - - 11111B
R/W
000413H
ICR19
- - - 11111B
R/W
00042CH
ICR44
- - - 11111B
R/W
000414H
ICR20
- - - 11111B
R/W
00042DH
ICR45
- - - 11111B
R/W
000415H
ICR21
- - - 11111B
R/W
00042EH
ICR46
- - - 11111B
R/W
000416H
ICR22
- - - 11111B
R/W
00042FH
ICR47
- - - 11111B
R/W
000417H
ICR23
- - - 11111B
R/W
000418H
ICR24
- - - 11111B
R/W
•Request level register for canceling hold request
Address
00000431H
bit 7
bit 0
HRCL
Initial value Access
- - - 11111B R/W
R/W : Readable and writable
: Unused
51
MB91107/108
(2) Block diagram
INT0∗2
IM
Priority judgment
OR
5
NMI
processing
NMI
LEVEL
4 ∼ 0∗4
4
LEVEL,
VECTOR
generation
LEVEL judgment
ICR00
RI00
VECTOR
judgment
6
HLDREQ
cancel
request
HLDCAN∗3
VCT5 ∼ 0∗5
ICR47
RI47
(DLYIRQ)
DLYI∗1
R-BUS
*1 : DLY I stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11. Delayed
Interrupt Module” for detail).
*2 : INT0 is a wake-up signal to clock control block in the sleep or stop status.
*3 : HLDCAN is a bus release request signal for bus masters other than CPU.
*4 : LEVEL 4 to LEVEL 0 are interrupt level outputs.
*5 : VCT5 to VCT0 are interrupt vector outputs.
52
MB91107/108
10. External Interrupt/NMI Control Block
The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to
INT7 pins.
Detecting levels can be selected from “H”, “L”, rising edge and falling edge (not for NMI pin).
(1) Register configuration
•Interrupt enable register
Address
000095H
bit 15
bit 8 bit 7
EIRR
bit 0
ENIR
Initial value
00000000B
Access
R/W
00000000B
R/W
00000000B
R/W
•External interrupt cause register
bit 15
bit 8 bit 7
EIRR
000094H
bit 0
ENIR
•Request level setting register
bit 15
bit 8 bit 7
EIRR
000099H
bit 0
ENIR
(2) Block diagram
R BUS
8
Interrupt
request
9
8
8
Interrupt enable register
Gate
Cause F/
Edge detection
circuit
9
INT0 ~ INT7
NMI
Interrupt cause register
Request level setting register
53
MB91107/108
11. Delayed Interrupt Module
Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed
interrupt module, an interrupt request to CPU can be generated/cancelled by the software.
Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram.
•Register configuration
•Delayed interrupt control register
Address
000430H
bit 7
bit 0
DICR
R/W : Readable and writable
: Unused
54
Initial value Access
- - - - - - - 0B R/W
MB91107/108
12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions.
• CPU clock generation (including gear function)
• Peripheral clock generation (including gear function)
• Reset generation and cause hold
• Standby function (including hardware standby)
• DMA request prohibit
• PLL (multiplier circuit) embedded
(1) Register configuration
•Reset cause register/watchdog cycle control register
Address
000480H
bit 15
RSRR
bit 10 bit 8
WTCR
bit 0
Initial value
Access
1XXXX - 0 0B R/W
bit 0
Initial value
0 0 0 111 - - B
R/W
Initial value
- - - - 0 0 0 0B
R/W
Initial value
XXXXXXXXB
W
Initial value
- - - - 0 0 0 0B
R/W
Initial value
XXXXXXXXB
W
Initial value
00 - - 0 - - - B
W
(STCR)
•Stand-by controled register
Address
000481H
bit 15
bit 10
(RSRR/WTCR)
bit 8
STCR
•DMA controlerrequest prohibit resister
Address
000482H
bit 15
bit 8
PDRR
bit 0
(CTBR)
•Timebase timer clear resister
Address
000483H
bit 15
bit 8
PDRR
bit 0
(CTBR)
•Gear control resister
Address
000484H
bit 15
bit 8
GCR
bit 0
(WPR)
•Watchdog reset generation postpone resister
Address
000485H
bit 15
bit 8
(GCR)
bit 0
WPR
•PLL control resister
Address
000488H
bit 15
bit 8
PCTR
R/W
W
X
bit 0
Vacancy
: Readable and writable
: Write only
: Unused
: Indeterminate
55
MB91107/108
(2) Block diagram
R
|
B
U
S
Gear control
block
GCR register
CPU gear
Peripheral
gear
PCTR register
Oscil-
PLL
lator
1/2
Internal interrupt
Selection
circuit
X0
X1
CPU clock
Internal bus clock
External bus clock
Internal
clock
generator
circuit
Peripheral DMA clock
Internal bus
peripheral clock
(Stop/sleep control section)
Internal reset
STCR register
Status
transition
control
circuit
CPU hold enable
HST pin
DMA request
STOP state
SLEEP state
CPU hold request
Reset
generation
F/F
(DNA prohibit
circuit)
PDRR register
(Reset cause circuit)
Power on cell
RST pin
RSRR register
(Watchdog control section)
WPR register
Watchdog F/F
CTBR register
Timebase timer
Count clock
56
Internal reset
MB91107/108
13. External Bus Interface
The external bus interface controls the interface between the device and the external memory and also the
external I/O, and has the following features.
• 25-bit (32 Mbytes) address output
• 6 independent banks owing to the chip select function.
Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.
Total 32 Mbytes × 6 area setting is available by the address pin and the chip select pin.
• 8/16-bit bus width setting are available for every chip select area.
Areas 6 and 7 allow the inclusive areas to be set.
• Programmable automatic memory wait (max. for 7 cycles) can be inserted.
• DRAM interface support
• Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)
Single CAS DRAM
Hyper DRAM
• 2 banks independent control (RAS, CAS, etc. control signals)
• DRAM select is available from 2CAS/1WE and 1CAS/2WE.
• Hi-speed page mode supported
• CBR/self refresh supported
• Programmable wave form
• Unused address/data pin can be used for I/O port.
• Little endian mode supported
• Clock doubler: Internal bus 50 MHz, external bus 25 MHz
(1) Register configuration
•Area selection resister 1 to 5
Address
00060CH
000610H
000614H
000618H
00061CH
bit 15
bit 0
Initial value
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 0B
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B
0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B
0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 1B
Access
W
W
W
W
W
bit 0
Initial value
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
W
W
W
W
W
ASR1
ASR2
ASR3
ASR4
ASR5
•Area mask resister 1 to 5
Address
00060EH
000612H
000616H
00061AH
00061EH
bit 15
AMR1
AMR2
AMR3
AMR4
AMR5
(Continued)
57
MB91107/108
(Continued)
•Area mode resister 0, 1, 32, 4, 5
Address
AMD0
: 000620H
AMD1
: 000621H
AMD32 : 000622H
: 000023H
AMD4
AMD5
: 000624H
bit 15
bit 8 bit 7
bit 0
AMD0
AMD1
Initial value
Access
- - - 0 0 1 1 1B 0 - - 0 0 0 0 0B
R/W
AMD32
AMD4
0 0 0 0 0 0 0 0B
AMD5
(DSCR)
0 - - 0 0 0 0 0B
R/W
Initial value
0 0 0 0 0 0 0 0B
W
0 - - 0 0 0 0 0B
R/W
•DRAM signal control resister
Address
000625H
bit 15
bit 8 bit 7
AMD5
bit 0
DSCR
•Refresh control resister
Address
000626H
bit 15
bit 0
RFCR
Initial value
- - XXXXXXB
0 0 - - - 0 0 0B
R/W
•External pin control resister
Address
000628H
00062AH
bit 15
bit 0
EPCR0
EPCR1
Initial value
- - - - 1 1 0 0B
- 1 1 1 1 1 1 1B
- - - - - - - 1B
1 1 1 1 1 1 1 1B
W
W
Initial value
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B
R/W
R/W
•DRAM control resister 4, 5
Address
00062CH
00062EH
bit 15
bit 0
DMCR4
DMCR5
•Little endian resister
Address
0007FEH
bit 15
bit 8 bit 7
LER
bit 0
(MODR)
Initial value
- - - - - 0 0 0B
W
Initial value
XXXXXXXXB
W
•Mode resister
Address
0007FFH
bit 15
bit 8 bit 7
(MODR)
R/W
W
X
58
bit 0
LER
: Readable and writable
: Write only
: Unused
: Indeterminate
MB91107/108
(2) Block diagram
A-OUT
ADDRESS BUS DATA BUS
32
32
EXTERNAL
DATA BUS
write buffer
switch
read buffer
switch
MUX
DATA BLOCK
ADDRESS BLOCK
+1or+2
EXTERNAL
ADDRESS BUS
inpage
address buffer
shifter
CS0 ∼ CS7
ASR
AMR
comparator
DRAM control
underflow
DMCR
RAS0, RAS1
CS0L, CS1L
CS0H, CS1H
DW0, DW1
refresh counter
from TBT
External pin control block
All blocks control
registers & control
RD
WR0, WR1
BRQ
BGRNT
CLK
RDY
59
MB91107/108
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(AVSS = VSS = 0.0 V)
Symbol
Value
Min.
Max.
Unit
Remarks
Power supply voltage
VCC
VSS − 0.3
VSS + 4.0
V
*1
Analog supply voltage
AVCC
VSS − 0.3
VSS + 4.0
V
*2
Analog reference voltage
AVRH
VSS − 0.3
VSS + 4.0
V
*2
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Analog pin input voltage
VIA
VSS − 0.3
AVCC + 0.3
V
Output voltage
VO
VSS − 0.3
VCC + 0.3
V
“L” level maximum output current
IOL
10
mA
*3
“L” level average output current
IOLAV
8
mA
*4
“L” level total maximum output current
ΣIOL
100
mA
“L” level total average output current
ΣIOLAV
50
mA
*5
IOH
−10
mA
*3
“H” level average output current
IOHAV
−4
mA
*4
“H” level total maximum output
current
ΣIOH
−50
mA
ΣIOHAV
−20
mA
Power consumption
PD
500
mW
Operating temperature
TA
0
+70
°C
Tstg
−55
+150
°C
“H” level maximum output current
“H” level total average output current
Storage temperature
*5
*1 : VCC must not be less than VSS – 0.3 V.
*2 : Make sure that the voltage does not exceed VCC + 0.3 V, such as when turning on the device.
*3 : Maximum output current is a peak current value measured at a corresponding pin.
*4 : Average output current is an average current for a 100 ms period at a corresponding pin.
*5 : Average total output current is an average current for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
60
MB91107/108
2. Recommended Operating Conditions
Parameter
Symbol
VCC
Power supply voltage
(AVSS = VSS = 0.0 V)
Value
Min.
Max.
3.0
3.6
Unit
Normal operation
V
VCC
3.0
3.6
Analog supply voltage
AVCC
VSS − 0.3
VSS + 3.6
V
Analog reference voltage
AVRH
AVSS
AVCC
V
TA
0
+70
°C
Operating temperature
Remarks
Retaining the RAM state in
stop mode
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
61
MB91107/108
3. DC Characteristics
Parameter
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin name
Condition
Value
Min.
Typ.
Max.
Unit
VIH
Input pin except for hysteresis input
0.7 × VCC
VCC + 0.3
V
VIHS
*1
0.8 × VCC
VCC + 0.3
V
VIL
Input pin except for hysteresis input
VSS − 0.3
0.25 × VCC
V
VILS
*1
VSS − 0.3
0.2 × VCC
V
“H” level output
voltage
VOH
All output pins
VCC = 3.0 V
IOH = −4.0 mA
VCC − 0.5
V
“L” level output
voltage
VOL
All output pins
VCC = 3.0 V
IOL = 8.0 mA
0.4
V
ILI
All output pins
VCC = 3.6 V
0.45 V<VI < VCC
−5
+5
µA
“H” level input
voltage
“L” level input
voltage
Input leak
current (Hi-Z Output leak current)
Remarks
Hysteresis
input
Hysteresis
input
Pull-up
resistance
RPULL
RST
VCC = 3.6 V
VI = 0.45 V
12
25
100
kΩ
Pull-down
resistance
RDOWN
BRQ
VCC = 3.6 V
VI = 3.3 V
12
25
100
kΩ
150
(Four
multiplication
mA )
FC = 12.5 MHz
VCC = 3.3 V
80
ICCS
FC = 12.5 MHz
VCC = 3.3 V
40
120
ICCH
TA = +25 °C
VCC = 3.3 V
5
µA Stop mode
10
pF
ICC
Power supply
current*2
Input
capacitance
VCC
CIN
Except for VCC,
AVCC, AVSS,
VSS
Operation
at 50 MHz
mA
Sleep
mode
*1 : Hysteresis input pin : NMI, RST, P40 to P47, P50 to P57, P60 to P67, P70, P81, P85, PA1 to PA6, PB0 to PB7,
PE0 to PE7, PF0 to PF7, PG0 to PG7, PH0 to PH7, PI0, PI1
*2 : The MB91V107 (development model) has larger supply current than the production models because it contains
an development tool interface circuit.
62
MB91107/108
4. AC Characteristics
•Measurement Conditions
The following conditions applies to measurement items unless otherwise specified.
•AC characteristics measurement conditions
Input
VCC
Output
VIH
VOH
VIL
VOL
0V
VIH
1 / 2 × VCC
VOH
1 / 2 × VCC
VIL
1 / 2 × VCC
VOL
1 / 2 × VCC
VCC = 3.0 V to 3.6 V
Note: The rise/fall time of input is 10 ns or less.
•Load conditions
Output pin
C = 50 pF
63
MB91107/108
(1) Clock Timings
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Sym- Pin
bol name
Parameter
Value
Condition
Unit
Min.
Max.
12.5
12.5
MHz
80
ns
Remarks
Clock frequency (1)
FC
X0
X1
Clock cycle time
tC
X0
X1
Frequency shift ratio ∗1
(when locked)
∆f
5
%
Clock frequency (2)
FC
X0
X1
10
25
MHz
Self-oscillation
(divide-by-2 input)
Clock frequency (3)
FC
X0
X1
10
25
MHz
External clock
(divide-by-2 input)
Clock cycle time
tC
X0
X1
40
100
ns
PWH
PWL
X0
X1
12.5 to
25 MHz
20
ns
Input to X0, X1
PWH
X0
Less than
12.5 MH
25
ns
Input to X0 only
Input clock rising/falling
time
tCR
tCF
X0
X1
8
ns
(tCR + tCF)
Internal operating clock
frequency
fCP
0.625 × 2
50
fCPP
0.625 × 2
25
tCP
tCPP
Input clock pulse width
Internal operating clock
cycle time
20
40
Self-oscillation 12.5 MHz
Internal operation at 50 MHz
(Using PLL, 4 multiplication)
MHz CPU system
MHz Peripheral system
1600*
2
ns
CPU system
1600*
2
ns
Peripheral system
*1 : Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock
multiplication system.
∆f =
α
f0
+
+α
× 100 (%) Center frequency f0
−α
−
*2 : These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and
a 1/8 gear.
64
MB91107/108
• Clock timing rating measurement conditions
tC
0.8 VCC
0.2 VCC
PWL
PWH
tCR
tCF
• Operation warranty range
Power supply
VCC
(V)
Normal operation warranty range (TA = 0 °C to +70 °C).
Net masked area are fCPP.
3.6
3.0
fCP / fCPP
0
0.625
25
50
(MHz)
Internal clock
• External / internal clock setting range
fCP / fCPP (MHz)
Max. internal clock frequency setting
fCP
50
CPU
LL system
(12.5 MHz / 4 multiplication)
Peripheral
fCPP
25
12.5
divide-by-2 system
5
0
0
10
25
fC
(MHz)
External clock
Self-oscillation
General oscillation input clock
Note: •When using PLL, the external clock must be used need 12.5 MHz.
•PLL oscillation stabilizing period > 100 µs
•The setting of internal clock must be within above ranges.
65
MB91107/108
(2) Clock Output Timing
Parameter
Cycle time
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
tCYC
CLK
CLK↑→CLK↓
tCHCL
CLK
CLK↓→CLK↑
tCLCH
CLK
Value
Condition
Min.
Max.
tCP
2 × tCP
Unit
ns
Remarks
*1
Using the doubler
1 / 2 × tCYC − 10 1 / 2 × tCYC + 10
ns
*2
1 / 2 × tCYC − 10 1 / 2 × tCYC + 10
ns
*3
tCYC
tCHCL
CLK
tCLCH
VOH
VOH
VOL
*1 : tCYC is a frequency for 1 clock cycle including a gear cycle.
*2 : Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,
respectively.
Min. : (1 – n/2) × tCYC – 10
Max. : (1 – n/2) × tCYC + 10
Select a gear cycle of × 1 when using the doubler.
*3 : Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,
respectively.
Min.: n/2 × tCYC – 10
Max.: n/2 × tCYC + 10
Select a gear cycle of × 1 when using the doubler.
66
MB91107/108
The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR
(gear control register) is as follows. However, in this chart source oscillation input means X0 input clock.
Source oscillation input
(When using the doublure)
• PLL system
(CHC bit of GCR set
to “0”)
(a) Gear × 1 CLK pin
CCK1/0 : “00”
tCYC
tCYC
Source oscillation input
• 2 dividing system
(CHC bit of GCR set
to “1”)
(a) Gear × 1 CLK pin
CCK1/0 : “00”
(b) Gear × 1/2 CLK pin
CCK1/0 : “01”
(c) Gear × 1/4 CLK pin
CCK1/0 : “10”
(d) Gear × 1/8 CLK pin
CCK1/0 : “11”
tCYC
tCYC
tCYC
tCYC
67
MB91107/108
(3) Reset Input Ratings
Parameter
Reset input time
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
Condition
tRSTL
RST
Value
Min.
Max.
tCP × 5
tRSTL
RST
0.2 VCC
68
Unit
ns
Remarks
MB91107/108
(4) Power-on Reset
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
Condition
Power supply rising
time
tR
VCC
Power supply shut
off time
tOFF
Oscillation stabilizing
time
tOSC
Parameter
Value
Unit
Remarks
18
ms
VCC < 0.2 V
before the power
supply rising
1
ms
Repeated operations
2 × tC × 220
+ 100 µs
ns
Min.
Max.
VCC = 3.3 V
VCC
tR
VCC
0.9 VCC
0.2 V
tOFF
•Notes
1) Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply
voltage.
VCC
Not less than 3 V
A voltage rising rate of 50 mV/
ms or less is recommended.
VSS
2) Set RST pin to “L” level when turning on the device, at least the tRSTL duration after the supply voltage reaches
VCC is necessary before turning the RST to “H” level.
VCC
tOSC
(Oscillation stabilizing
RST
tRSTL
3) If the supply voltage goes below the lower limit of the guaranteed operating voltage range, be sure to restart
the power supply from the VSS level. This is because an internal power-on reset must be generated to restart
operation without allowing the internal circuit to run out of control.
The guaranteed operating voltage range of MB91107 is from 3.0 to 3.6 V.
69
MB91107/108
(5) Normal Bus Access Read/write Operation
Parameter
Symbol
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Pin name
Condition
Value
Unit
Min.
Max.
15
ns
15
ns
Remarks
CS0 to CS7 delay time
tCHCSL
CS0 to CS7 delay time
tCHCSH
Address delay time
tCHAV
CLK
A24 to A00
15
ns
Data delay time
tCHDV
CLK
D31 to D16
15
ns
RD delay time
tCLRL
15
ns
RD delay time
tCLRH
15
ns
WR0, WR1 delay time
tCLWL
15
ns
WR0, WR1 delay time
tCLWH
15
ns
Valid address → valid data
input time
tAVDV
3 / 2 × tCYC − 25
ns
*1
*2
RD ↓→ valid data input time
tRLDV
tCYC − 10
ns
*1
10
ns
0
ns
Data set up → RD ↑ time
tDSRH
RD ↑→ data hold time
tRHDX
CLK
CS0 to CS7
CLK
RD
CLK
WR0 to WR1
A24 to A00
D31 to D16
RD
D31 to D16
*1: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC × extended cycle number for
delay) to this rating.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively.
Equation: (2 – n/2) × tCYC – 25
70
MB91107/108
tCYC
BA2
BA1
CLK
2.4 V
2.4 V
2.4 V
0.8 V
0.8 V
tCHCSH
tCHCSL
CS0 ∼ CS7
2.4 V
0.8 V
tCHAV
A24 ∼ A00
2.4 V
0.8 V
2.4 V
0.8 V
tCLRL
tCLRH
RD
2.4 V
0.8 V
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
D31 ∼ D16
Read
2.4 V
0.8 V
tDSRH
tCLWL
WR0 ∼ WR1
2.4 V
0.8 V
tCLWH
tCHDV
D31 ∼ D16
2.4 V
0.8 V
Write
2.4 V
0.8 V
71
MB91107/108
(6) Ready Input Timing
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin name
RDY set up time → CLK ↓
tRDYS
RDY
CLK
CLK ↓→ RDY hold time
tRDYH
CLK
RDY
Parameter
Condition
Value
Max.
15
ns
0
ns
tCYC
CLK
2.4 V
2.4 V
0.8 V
tRDYH
tRDYS
RDY
(When wait
is inserted.)
RDY
(When no wait
is inserted.)
72
0.8 V
2.4 V
Unit
Min.
tRDYS
2.4 V
0.8 V
0.8 V
tRDYH
Remarks
MB91107/108
(7) Hold Timing
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin name
BGRNT delay time
tCHBGL
BGRNT delay time
tCHBGH
CLK
BGRNT
Parameter
Pin floating → BGRNT ↓ time
tXHAL
BGRNT ↑→ pin valid time
tHAHV
Condition
BGRNT
Value
Unit
Min.
Max.
6
ns
6
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
Remarks
Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change.
tCYC
CLK
2.4 V
2.4 V
2.4 V
2.4 V
BRQ
tCHBGL
BGRNT
2.4 V
0.8 V
tXHAL
Each pin
tCHBGH
tHAHV
High impedance
73
MB91107/108
(8) Normal DRAM Mode Read/Write Cycle
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin name
RAS delay time
tCLRAH
RAS delay time
tCHRAL
CLK
RAS
CAS delay time
tCLCASL
CAS delay time
tCLCASH
ROW address delay time
tCHRAV
COLUMN address delay time
tCHCAV
DW delay time
tCHDWL
DW delay time
tCHDWH
Output data delay time
tCHDV1
RAS ↓→ valid data input time
tRLDV
CAS ↓→ valid data input time
tCLDV
CAS ↑→ data hold time
tCADH
Parameter
Condition
Value
Unit Remarks
Min.
Max.
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
CLK
D31 to D16
15
ns
RAS
D31 to D16
5 / 2 × tCYC − 16
ns
*1
*2
tCYC − 17
ns
*1
0
ns
CLK
CAS
CLK
A24 to A00
CLK
DW
CAS
D31 to D16
*1 : When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
*2 : Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,
respectively.
•Equation: (3 – n/2) × tCYC – 16
74
MB91107/108
tCYC
Q1
CLK
Q2
Q3
2.4 V
Q4
Q5
0.8 V
0.8 V
2.4 V
2.4 V
0.8 V
2.4 V
RAS
0.8 V
tCHRAL
tCLRAH
tCLCASL
tCLCASH
CAS
2.4 V
0.8 V
tCHCAV
tCHRAV
2.4 V
0.8 V
A24 to A00
2.4 V
ROW address 0.8
V
2.4 V
0.8 V
COLUMN address
2.4 V
0.8 V
tRLDV
tCLDV
2.4 V
0.8 V
D31 to D16
tCADH
Read
2.4 V
DW
0.8 V
tCHDWL
D31 to D16
2.4 V
0.8 V
2.4 V
0.8 V
Write
tCHDWH
2.4 V
0.8 V
tCHDV1
75
MB91107/108
(9) Normal DRAM Mode Fast Page Read/Write Cycle
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin name
RAS delay time
tCLRAH
CLK, RAS
CAS delay time
tCLCASL
CAS delay time
tCLCASH
CLK
CAS
COLUMN address delay time
tCHCAV
Parameter
CLK
A24 to A00
DW delay time
tCHDWH
CLK, DW
Output data delay time
tCHDV1
CLK
D31 to D16
CAS ↓→ valid data input time
tCLDV
CAS ↑→ data hold time
tCADH
Condition
CAS
D31 to D16
* : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
76
Value
Unit Remarks
Min.
Max.
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
tCYC − 17
ns
0
ns
*
MB91107/108
Q5
CLK
2.4 V
Q4
Q5
0.8 V
0.8 V
Q4
Q5
2.4 V
0.8 V
tCLRAH
2.4 V
RAS
tCLCASL
tCLCASH
2.4 V
CAS
0.8 V
tCHCAV
A24 to A00 COLUMN address
2.4 V
0.8 V
2.4 V
0.8 V
COLUMN address
tCADH
tCLDV
D31 to D16
2.4 V
0.8 V
Read
COLUMN address
Read
2.4 V
0.8 V
Read
tCHDWH
2.4 V
DW
tCHDV1
D31 to D16
2.4 V
0.8 V
Write
2.4 V
0.8 V
2.4 V
0.8 V
Write
77
MB91107/108
(10) Single DRAM Timing
Symbol
Pin name
RAS delay time
tCLRAH2
RAS delay time
tCHRAL2
CLK
RAS
CAS delay time
tCHCASL2
CAS delay time
tCHCASH2
ROW address delay time
tCHRAV2
COLUMN address delay
time
tCHCAV2
DW delay time
tCHDWL2
DW delay time
tCHDWH2
Parameter
78
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Output data delay time
tCHDV2
CAS ↓→ Valid data input
time
tCLDV2
CAS ↑→ data hold time
tCADH2
Condition
CLK
CAS
CLK
A24 to A00
CLK
DW
CLK,
D31 to D16
CAS
D31 to D16
Value
Unit Remarks
Min.
Max.
15
ns
15
ns
n / 2 × tCYC
+ tCHCASH2
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
(1 − n / 2) × tCYC
− 17
ns
0
ns
MB91107/108
∗1
tCYC
Q1
2.4 V
CLK
Q2
Q3
2.4 V
0.8 V
2.4 V
RAS
Q4S
Q4S
Q4S
2.4 V
2.4 V
2.4 V
0.8 V
tCHRAL2
tCLRAH2
tCHCASL2
tCHCASH2
2.4 V
CAS
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
A24 to A00
ROW address
tCHRAV2
2.4 V
0.8 V
COLUMN-0
COLUMN-1
COLUMN-2
0.8 V
tCHCAV2
tCADH2
tCLDV2
2.4 V
(Read)
DW
2.4 V
0.8 V
(Read)
tCHDWH2
tCHDWL2
∗2
D31 to D16
(Write)
2.4 V
Read-0 0.8 V Read-1 0.8 V Read-2
D31 to D16
2.4 V
0.8 V
tCHDV2
Write-0
2.4 V
2.4 V
0.8 V
tCHDV2
2.4 V
0.8 V
2.4 V
Write-1
0.8 V
Write-2
0.8 V
*1 : Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.
*2 :
indicates the timing when the bus cycle begins from the high speed page mode.
79
MB91107/108
(11) Hyper DRAM Timing
Symbol
Pin name
RAS delay time
tCLRAH3
RAS delay time
tCHRAL3
CLK
RAS
CAS delay time
tCHCASL3
CAS delay time
tCHCASH3
ROW address delay time
tCHRAV3
COLUMN address delay time
tCHCAV3
RD delay time
tCHRL3
Parameter
80
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
RD delay time
tCHRH3
RD delay time
tCLRL3
DW delay time
tCHDWL3
DW delay time
tCHDWH3
Output data delay time
tCHDV3
CAS ↓→ valid data input time
tCLDV3
CAS ↓→ data hold time
tCADH3
Condition
CLK
CAS
CLK
A24 to A00
CLK
RD
CLK
DW
CLK
D31 to D16
CAS
D31 to D16
Value
Unit Remarks
Min.
Max.
15
ns
15
ns
n / 2 × tCYC
+ tCHCASH3
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
tCYC − 17
ns
0
ns
MB91107/108
∗1
tCYC
Q1
CLK
2.4 V
Q2
Q3
0.8 V
2.4 V
RAS
Q4H
2.4 V
2.4 V
Q4H
Q4H
2.4 V
2.4 V
0.8 V
0.8 V
tCHRAL3
tCLRAH3
tCHCASL3
tCHCASH3
CAS
0.8 V
2.4 V
0.8 V
0.8 V
COLUMN-1
COLUMN-2
2.4 V
2.4 V
0.8 V
A24 to A00
ROW address
tCHRAV3
2.4 V
0.8 V
tCHCAV3
COLUMN-0
0.8 V
∗2
RD
(Read)
0.8 V
2.4 V
0.8 V
tCHRL3
tCHRH3
tCLRL3
tCLDV3
tCADH3
2.4 V
Read-0
0.8 V
D31 to D16
(Read)
DW
2.4 V
0.8 V
(Read)
tCHDWH3
tCHDWL3
∗2
D31 to D16
(Write)
2.4 V
Read-1 0.8 V
2.4 V
0.8 V
tCHDV3
Write-0
2.4 V
2.4 V
0.8 V
tCHDV3
2.4 V
0.8 V
2.4 V
Write-1
0.8 V
Write-2
0.8 V
*1 : Q4S indicates Q4HR (Read) of Single DRAM cycle or Q4HW (Write) cycle.
*2 :
indicates the timing when the bus cycle begins from the high speed page mode.
81
MB91107/108
(12) CBR Refresh
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin name
RAS delay time
tCLRAH
RAS delay time
tCHRAL
CLK
RAS
CAS delay time
tCLCASL
CAS delay time
tCLCASH
Parameter
RAS
82
15
ns
15
ns
15
ns
15
ns
R3
0.8 V
0.8 V
R4
0.8 V
2.4 V
0.8 V
tCHRAL
0.8 V
tCLCASL
DW
2.4 V
2.4 V
tCLRAH
CAS
Max.
CLK
CAS
R2
Unit
Min.
tCYC
R1
CLK
Value
Condition
2.4 V
tCLCASH
Remarks
MB91107/108
(13) Self Refresh
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin name
RAS delay time
tCLRAH
RAS delay time
tCHRAL
CLK
RAS
CAS delay time
tCLCASL
CAS delay time
tCLCASH
Parameter
tCYC
SR1
CLK
2.4 V
CLK
CAS
SR2
2.4 V
Condition
SR3
Value
Unit Remarks
Min.
Max.
15
ns
15
ns
15
ns
15
ns
SR3
2.4 V
0.8 V
0.8 V
tCHRAL
tCLRAH
2.4 V
0.8 V
RAS
CAS
2.4 V
0.8 V
tCHCASL
tCLCASH
83
MB91107/108
(14) UART Timing
Parameter
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol Pin name
Condition
Unit Remarks
Min.
Max.
8 tCYCP
ns
−80
80
ns
100
ns
Serial clock cycle time
tSCYC
SCLK ↓→ SOUT delay time
tSLOV
Valid SIN → SCLK ↑
tIVSH
SCLK ↑→ valid SIN hold time
tSHIX
60
ns
Serial clock “H” pulse width
tSHSL
4 tCYCP
ns
Serial clock “L” pulse width
tSLSH
4 tCYCP
ns
150
ns
60
ns
60
ns
SCLK ↓→ SOUT delay time
tSLOV
Valid SIN → SCLK ↑
tIVSH
SCLK ↑→ valid SIN hold time
tSHIX
Internal shift
clock mode
External shift
clock mode
Notes: • This rating is for AC characteristics in CLK synchronous mode.
• tCYCP: A cycle time of peripheral system clock
84
Value
MB91107/108
• Internal shift clock mode
tSCYC
2.4 V
SCLK
0.8 V
tSLOV
2.4 V
SOUT
0.8 V
tSHIX
tIVSH
SIN
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
SCLK
0.2 VCC
tSLOV
2.4 V
SOUT
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.2 VCC
85
MB91107/108
(15) Trigger System Input Timing to
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Value
Symbol
Pin name
Condition
Min.
Max.
A/D start trigger input time
tATGX
ATG
5 tCYCP
ns
PPG start trigger input time
tPTGR
TRG0 to
TRG3
5 tCYCP
ns
Parameter
Note : tCYCP: A cycle time of peripheral system clock
tATGX
ATG
TRG0 to TRG3
86
0.2 VCC
Unit Remarks
MB91107/108
(16) DMA Controller Timing
Parameter
DREQ input pulse
width
DACK delay time
(Normal bus)
(Normal DRAM)
EOP delay time
(Normal bus)
(Normal DRAM)
DACK delay time
(Single DRAM)
(Hyper DRAM)
EOP delay time
(Single DRAM)
(Hyper DRAM)
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
Symbol
Pin name
tDRWH
DREQ0 to
DREQ2
tCLDL
tCLDH
tCLEL
tCLEH
tCHDL
tCHDH
tCHEL
tCHEH
Value
Condition
Max.
2 tCYC
ns
6
ns
6
ns
6
ns
6
ns
n / 2 × tCYC
ns
6
ns
n / 2 × tCYC
ns
6
ns
CLK
DACK0 to
DACK2
CLK
EOP0 to EOP2
Unit
Min.
CLK
DACK0 to
DACK2
CLK
EOP0 to EOP2
Remarks
tCYC
CLK
2.4 V
2.4 V
0.8 V
0.8 V
tCLDL
tCLEL
DACK0 to DACK2
EOP0 to EOP2
(Normal bus)
(Normal DRAM)
tCLDH
tCLEH
2.4 V
0.8 V
DACK0 to DACK2
EOP0 to EOP2
(Single DRAM)
(Hyper DRAM)
2.4 V
0.8 V
tCHDL
tCHEL
tCHEH
tCHDH
tDRWH
DREQ0 to DREQ2
2.4 V
2.4 V
87
MB91107/108
5. A/D Converter Block Electrical Characteristics
(AVCC = VCC = +3.0 V to +3.6 V, AVSS = VSS = 0.0 V, AVRH = +3.0 V to +3.6 V, TA = 0 °C to +70 °C)
Symbol
Pin name
Resolution
Total error
Parameter
Value
Unit
Min.
Typ.
Max.
10
10
bit
±4.0
LSB
Linearity error
±3.0
LSB
Differentiation linearity error
±2.5
LSB
Zero transition voltage
VOT
AN0 to AN3
−1.5
+0.5
+2.5
LSB
Full-scale transition voltage
VFST
AN0 to AN3
AVRH − 4.5
AVRH − 1.5
AVRH + 0.5
LSB
Conversion time
5.6*
µs
Analog port input current
IAIN
AN0 to AN3
0.1
10
µA
Analog input voltage
VAIN
AN0 to AN3
AVSS
AVRH
V
AVRH
AVSS
AVCC
V
500
µA
5*2
µA
500
µA
2
5*
µA
4
LSB
Reference voltage
IA
Power supply current
AVCC
IAH
IR
Reference voltage supply
current
IRH
Conversion variance between
channels
AVRH
AN0 to AN3
1
*1: AVCC = VCC = 3.0 V to 3.6 V(for a machine clock of 25 MHz).
*2: Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.6 V)
Notes: • As the absolute value of AVRH decreases, relative error increases.
• Output impedance of external circuit of analog input under following conditions;
Output impedance of external circuit < 7 kΩ.
If output impedance of external circuit is too high, analog voltage sampling time may be too short for
accurate sampling.
•Analog input circuit model plan
Sample and hold circuit
C0
Analog input
Comparator
RON1
RON2
RON3
RON4
C1
RON1 : 5 kΩ
RON2 : 620 Ω
RON3 : 620 Ω
RON4 : 480 Ω
C0 : 2 pF
C1 : 2 pF
Note: Listed values are for reference purposes only.
88
RONX, CX are preliminary value.
MB91107/108
6. A/D Converter Glossary
• Resolution
The smallest change in analog voltage detected by A/D converter.
• Linearity error
A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000
0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”).
• Differential linearity error
A deviation of a step voltage for changing the LSB of output code from ideal input voltage
Linearity error
3FF
Differential linearity error
Ideal value
Actual conversion characteristic
N+1
3FE
{1 LSB × (N − 1) + VOT}
Actual conversion
characteristic
VFST
Digital output
Digital output
3FD
(Measured
value)
004
VNT
(Measured
value)
Actual conversion
characteristic
003
N
N−1
V(N + 1)T
002
VNT
(Measured value)
value)
Actual conversion
characteristic
Ideal value
001
VOT
N−2
(Measured
value)
AVRL
AVRH
AVRL
AVRH
Analog input
Linearity error of digital output N
Analog input
=
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
Differential linearity error of digital output N
1 LSB =
VFST − VOT
1022
1 LSB (Ideal value) =
(Measured
=
V (N + 1) T − VNT
1 LSB
[LSB]
−1
[LSB]
[V]
AVRH − AVRL
1024
[V]
VOT : A voltage for causing transition of digital output from (000) H to (001) H
VFST : A voltage for causing transition of digital output from (3FE) H to (3FF) H
VNT : A voltage for causing transition of digital output from (N − 1) to N
89
MB91107/108
• Total error
A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error
3FF
1.5 LSB
3FE
Actual conversion
characteristic
Digital output
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Measured
value)
Actual conversion
characteristic
Ideal value
003
002
001
0.5 LSB
AVRL
AVRH
Analog input
Total error of digital output N =
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
[LSB]
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage for causing transition of digital output from (N − 1) to N
90
MB91107/108
■ REFERENCE DATA
(2) “L” level output voltage
“H” level output voltage vs. power supply voltage
“L” level output voltage vs. power supply voltage
140.0
4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
2.7
135.0
130.0
VOL (V)
VOH (V)
(1) “H” level output voltage
150.0
105.0
3.0
3.3
VCC (V)
3.6
100.0
2.7
3.9
(CMOS input)
3.3
VCC (V)
3.6
3.9
(Hysteresys input)
3.3
VCC (V)
3.6
3.9
Input level vs. power supply voltage
(Hysteresys )
VIN (V)
VIH
VIL
3.0
3.0
(4) “H”level input / “L” level input voltage
Input level vs. power supply voltage
(CMOS )
VIN (V)
120.0
110.0
(3) “H” level input / “L” level input voltage
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
2.7
125.0
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
2.7
VIH
VIL
3.0
3.3
VCC (V)
3.6
3.9
91
MB91107/108
(5) Power supply current
Power supply current (sleep mode) vs.
power supply current
Power supply current vs. voltage
60.0
3.0
3.3
VCC (V)
3.6
3.3
VCC (V)
3.6
3.9
A/D conversion block Power supply current
vs. power supply voltage (25 MHz)
350
300
IA (µA)
ICCH (µA)
3.0
400
250
200
150
100
50
3.0
3.3
VCC (V)
3.6
3.9
280
260
IR (µA)
25 MHz
20.0
450
300
240
220
200
180
92
30.0
0.0
2.7
3.9
A/D conversion block reference voltage supply
current vs. voltage (25 MHz)
160
2.7
40.0
10.0
Power supply current (stop mode) vs.
power supply voltage
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
2.7
ICCS (mA)
25 MHz
50 MHz
50.0
50 MHz
ICC (mA)
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
2.7
3.0
3.3
AVRH (V)
3.6
3.9
0
2.7
3.0
3.3
AVCC (V)
3.6
3.9
MB91107/108
(6) Pull-up / pull-down resistance
Pull-down resistance vs. power supply voltage
Pull-up resistance vs. power supply voltage
100.0
R (Ω)
R (Ω)
100.0
10.0
2.7
3.0
3.3
VCC (V)
3.6
3.9
10.0
2.7
3.0
3.3
VCC (V)
3.6
3.9
93
MB91107/108
■ INSTRUCTIONS (165 INSTRUCTIONS)
1. How to Read Instruction Set Summary
Mnemonic
ADD
* ADD
↓
(1)
Rj,
Ri
#s5, Ri
,
,
↓
(2)
Type
OP
CYC
NZVC
Operation
A
C
,
,
A6
A4
,
,
1
1
,
,
CCCC
CCCC
,
,
Ri + Rj → Ri
Ri + s5 → Ri
,
,
↓
(3)
↓
(4)
↓
(5)
↓
(6)
↓
(7)
Remarks
(1) Names of instructions
Instructions marked with * are not included in CPU specifications. These are extended instruction codes
added/extended at assembly language levels.
(2) Addressing modes specified as operands are listed in symbols.
Refer to “2. Addressing mode symbols” for further information.
(3) Instruction types
(4) Hexa-decimal expressions of instructions
(5) The number of machine cycles needed for execution
a: Memory access cycle and it has possibility of delay by Ready function.
b: Memory access cycle and it has possibility of delay by Ready function.
If an object register in a LD operation is referenced by an immediately following instruction, the interlock
function is activated and number of cycles needed for execution increases.
c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or
if the instruction belongs to instruction format A group, the interlock function is activated and number of
cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number
of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
For a, b, c and d, minimum execution cycle is 1.
(6) Change in flag sign
• Flag change
C : Change
– : No change
0 : Clear
1 : Set
• Flag meanings
N : Negative flag
Z : Zero flag
V : Over flag
C : Carry flag
(7) Operation carried out by instruction
94
MB91107/108
2. Addressing Mode Symbols
Ri
Rj
R13
Ps
Rs
CRi
CRj
#i8
: Register direct (R0 to R15, AC, FP, SP)
: Register direct (R0 to R15, AC, FP, SP)
: Register direct (R13, AC)
: Register direct (Program status register)
: Register direct (TBR, RP, SSP, USP, MDH, MDL)
: Register direct (CR0 to CR15)
: Register direct (CR0 to CR15)
: Unsigned 8-bit immediate (–128 to 255)
Note: –128 to –1 are interpreted as 128 to 255
#i20
: Unsigned 20-bit immediate (–0X80000 to 0XFFFFF)
Note: –0X7FFFF to –1 are interpreted as 0X7FFFF to 0XFFFFF
#i32
: Unsigned 32-bit immediate (–0X80000000 to 0XFFFFFFFF)
Note: –0X80000000 to –1 are interpreted as 0X80000000 to 0XFFFFFFFF
#s5
: Signed 5-bit immediate (–16 to 15)
#s10
: Signed 10-bit immediate (–512 to 508, multiple of 4 only)
#u4
: Unsigned 4-bit immediate (0 to 15)
#u5
: Unsigned 5-bit immediate (0 to 31)
#u8
: Unsigned 8-bit immediate (0 to 255)
#u10
: Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)
@dir8
: Unsigned 8-bit direct address (0 to 0XFF)
@dir9
: Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)
@dir10
: Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)
label9
: Signed 9-bit branch address (–0X100 to 0XFC, multiple of 2 only)
label12
: Signed 12-bit branch address (–0X800 to 0X7FC, multiple of 2 only)
label20
: Signed 20-bit branch address (–0X80000 to 0X7FFFF)
label32
: Signed 32-bit branch address (–0X80000000 to 0X7FFFFFFF)
@Ri
: Register indirect (R0 to R15, AC, FP, SP)
@Rj
: Register indirect (R0 to R15, AC, FP, SP)
@(R13, Rj)
: Register relative indirect (Rj: R0 to R15, AC, FP, SP)
@(R14, disp10) : Register relative indirect (disp10: –0X200 to 0X1FC, multiple of 4 only)
@(R14, disp9) : Register relative indirect (disp9: –0X100 to 0XFE, multiple of 2 only)
@(R14, disp8) : Register relative indirect (disp8: –0X80 to 0X7F)
@(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only)
@Ri+
: Register indirect with post-increment (R0 to R15, AC, FP, SP)
@R13+
: Register indirect with post-increment (R13, AC)
@SP+
: Stack pop
@–SP
: Stack push
(reglist)
: Register list
95
MB91107/108
3. Instruction Types
MSB
Type A
Type B
LSB
16 bits
OP
Rj
Ri
8
4
4
OP
i8/o8
Ri
4
8
4
Type C
OP
u4/m4
Ri
8
4
4
ADD, ADDN, CMP, LSL, LSR and ASR instructions only
Type *C’
Type D
Type E
Type F
96
OP
s5/u5
Ri
7
5
4
OP
u8/rel8/dir/reglist
8
8
OP
SUB-OP
Ri
8
4
4
OP
rel11
5
11
MB91107/108
4. Detailed Description of Instructions
• Add/subtract operation instructions (10 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
ADD
* ADD
Rj, Ri
#s5, Ri
A
C’
A6
A4
1
1
C C C C Ri + Rj → Ri
C C C C Ri + s5 → Ri
ADD
ADD2
#i4, Ri
#i4, Ri
C
C
A4
A5
1
1
C C C C Ri + extu (i4) → Ri
C C C C Ri + extu (i4) → Ri
ADDC
Rj, Ri
A
A7
1
C C C C Ri + Rj + c → Ri
ADDN
* ADDN
Rj, Ri
#s5, Ri
A
C’
A2
A0
1
1
– – – – Ri + Rj → Ri
– – – – Ri + s5 → Ri
ADDN
ADDN2
#i4, Ri
#i4, Ri
C
C
A0
A1
1
1
– – – – Ri + extu (i4) → Ri
– – – – Ri + extu (i4) → Ri
SUB
Rj, Ri
A
AC
1
C C C C Ri – Rj → Ri
SUBC
Rj, Ri
A
AD
1
C C C C Ri – Rj – c → Ri
SUBN
Rj, Ri
A
AE
1
– – – – Ri – Rj → Ri
Remarks
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
Add operation with
sign
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
Subtract operation with
carry
• Compare operation instructions (3 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
CMP
* CMP
Rj, Ri
#s5, Ri
A
C’
AA
A8
1
1
C C C C Ri – Rj
C C C C Ri – s5
CMP
CMP2
#i4, Ri
#i4, Ri
C
C
A8
A9
1
1
C C C C Ri + extu (i4)
C C C C Ri + extu (i4)
Remarks
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
• Logical operation instructions (12 instructions)
Mnemonic
Type
OP
Cycle N Z V C
AND
AND
ANDH
ANDB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
82
84
85
86
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri &
(Ri) &
(Ri) &
(Ri) &
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
OR
OR
ORH
ORB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
92
94
95
96
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri
(Ri)
(Ri)
(Ri)
|
|
|
|
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
EOR
EOR
EORH
EORB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
9A
9C
9D
9E
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri ^
(Ri) ^
(Ri) ^
(Ri) ^
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
Operation
Remarks
97
MB91107/108
• Bit manipulation arithmetic instructions (8 instructions)
Mnemonic
BANDL
BANDH
* BAND
BORL
BORH
* BOR
BEORL
BEORH
* BEOR
BTSTL
BTSTH
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
Type
OP
Cycle N Z V C
C
80
1 + 2a – – – – (Ri) & = (F0H + u4)
Manipulate lower 4 bits
C
81
1 + 2a – – – – (Ri) & = ((u4<<4) + 0FH)
Manipulate upper 4 bits
–
*1
Remarks
– – – – (Ri) & = u8
C
90
1 + 2a – – – – (Ri) | = u4
Manipulate lower 4 bits
C
91
1 + 2a – – – – (Ri) | = (u4<<4)
Manipulate upper 4 bits
–
*2
– – – – (Ri) | = u8
C
98
1 + 2a – – – – (Ri) ^ = u4
Manipulate lower 4 bits
C
99
1 + 2a – – – – (Ri) ^ = (u4<<4)
Manipulate upper 4 bits
–
*3
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
Operation
– – – – (Ri) ^ = u8
C
88
2+a
0 C – – (Ri) & u4
Test lower 4 bits
C
89
2+a
C C – – (Ri) & (u4<<4)
Test upper 4 bits
*1: Assembler generates BANDL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BANDH if “u8&0xF0” leaves an active bit. Depending on the value in the “u8” format, both BANDL and BANDH
may be generated.
*2: Assembler generates BORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BORH if “u8&0xF0” leaves an active bit.
*3: Assembler generates BEORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BEORH if “u8&0xF0” leaves an active bit.
• Add/subtract operation instructions (10 instructions)
Mnemonic
Type
OP
Cycle N Z V C
MUL
MULU
MULH
MULUH
Rj, Ri
Rj, Ri
Rj, Ri
Rj, Ri
A
A
A
A
AF
AB
BF
BB
5
5
3
3
CCC
CCC
CC–
CC–
DIVOS
DIVOU
DIV1
DIV2
DIV3
DIV4S
* DIV
Ri
Ri
Ri
Ri
E
E
E
E
E
E
97 – 4
97 – 5
97 – 6
97 – 7
9F – 6
9F – 7
Ri
*1
1
1
d
1
1
1
–
–
–
–
–
–
–
–
* DIVU
Ri
*2
–
–
–
C
C
–
–
C
–
–
–
–
–
–
–
–
–
–
–
Operation
Rj × Ri → MDH, MDL
Rj × Ri → MDH, MDL
Rj × Ri → MDL
Rj × Ri → MDL
–
–
C
C
–
–
C MDL/Ri → MDL,
MDL%Ri → MDH
– C – C MDL/Ri → MDL,
MDL%Ri → MDH
Remarks
32-bit × 32-bit = 64-bit
Unsigned
16-bit × 16-bit = 32-bit
Unsigned
Step calculation
32-bit/32-bit = 32-bit
Unsigned
*1: DIVOS, DIV1 × 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.
*2: DIVOU and DIV1 × 32 are generated. A total instruction code length of 66 bytes.
98
MB91107/108
• Shift arithmetic instructions (9 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LSL
* LSL
LSL
LSL2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
B6
B4
B4
B5
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri<<Rj → Ri
Ri<<u5 → Ri
Ri<<u4 → Ri
Ri<<(u4 + 16) → Ri
Logical shift
LSR
* LSR
LSR
LSR2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
B2
B0
B0
B1
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri>>Rj → Ri
Ri>>u5 → Ri
Ri>>u4 → Ri
Ri>>(u4 + 16) → Ri
Logical shift
ASR
* ASR
ASR
ASR2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
BA
B8
B8
B9
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri>>Rj → Ri
Ri>>u5 → Ri
Ri>>u4 → Ri
Ri>>(u4 + 16) → Ri
Logical shift
• Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer
instruction) (3 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
LDI: 32
LDI: 20
#i32, Ri
#i20, Ri
E
C
9F – 8
9B
3
2
– – – – i32 → Ri
– – – – i20 → Ri
LDI: 8
* LDI
#i8, Ri
# {i8 | i20 | i32}, Ri
*1
B
C0
1
– – – – i8 → Ri
{i8 | i20 | i32} → Ri
Remarks
Upper 12 bits are zeroextended
Upper 24 bits are zeroextended
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.
If an immediate value contains relative value or external reference, assembler selects i32.
• Memory load instructions (13 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
(Rj) → Ri
(R13 + Rj) → Ri
(R14 + disp10) → Ri
(R15 + udisp6) → Ri
(R15) → Ri, R15 + = 4
(R15) → Rs, R15 + = 4
Remarks
LD
LD
LD
LD
LD
LD
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp10), Ri
@(R15, udisp6), Ri
@R15 +, Ri
@R15 +, Rs
A
A
B
C
E
E
04
00
20
03
07 – 0
07 – 8
b
b
b
b
b
b
LD
@R15 +, PS
E
07 – 9
1+a+b
LDUH
LDUH
LDUH
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp9), Ri
A
A
B
05
01
40
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp9) → Ri
Zero-extension
Zero-extension
Zero-extension
LDUB
LDUB
LDUB
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp8), Ri
A
A
B
06
02
60
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp8) → Ri
Zero-extension
Zero-extension
Zero-extension
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
C C C C (R15) → PS, R15 + = 4
Rs: Special-purpose
register
NoteThe relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8 → o8 = disp8:Each disp is a code extension.
disp9 → o8 = disp9>>1:Each disp is a code extension.
disp10 → o8 = disp10>>2:Each disp is a code extension.
udisp6 → u4 = udisp6>>2:udisp4 is a 0 extension.
99
MB91107/108
• Memory store instructions (13 instructions)
Mnemonic
Type
OP
Cycle N Z V C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Ri → (Rj)
Ri → (R13 + Rj)
Ri → (R14 + disp10)
Ri → (R15 + usidp6)
R15 – = 4, Ri → (R15)
R15 – = 4, Rs → (R15)
Remarks
ST
ST
ST
ST
ST
ST
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp10)
Ri, @(R15, udisp6)
Ri, @–R15
Rs, @–R15
A
A
B
C
E
E
14
10
30
13
17 – 0
17 – 8
a
a
a
a
a
a
–
–
–
–
–
–
Word
Word
Word
ST
PS, @–R15
E
17 – 9
a
– – – – R15 – = 4, PS → (R15)
STH
STH
STH
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp9)
A
A
B
15
11
50
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp9)
Half word
Half word
Half word
STB
STB
STB
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp8)
A
A
B
16
12
70
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp8)
Byte
Byte
Byte
Rs: Special-purpose
register
NoteThe relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8 → o8 = disp8:Each disp is a code extension.
disp9 → o8 = disp9>>1:Each disp is a code extension.
disp10 → o8 = disp10>>2:Each disp is a code extension.
udisp6 → u4 = udisp6>>2:udisp4 is a 0 extension.
• Transfer instructions between registers/special-purpose registers transfer instructions
(5 instructions)
Mnemonic
100
Type
OP
Cycle N Z V C
Operation
MOV
Rj, Ri
A
8B
1
– – – – Rj → Ri
MOV
Rs, Ri
A
B7
1
– – – – Rs → Ri
MOV
Ri, Rs
A
B3
1
– – – – Ri → Rs
MOV
MOV
PS, Ri
Ri, PS
E
E
17 – 1
07 – 1
1
c
– – – – PS → Ri
C C C C Ri → PS
Remarks
Transfer between
general-purpose
registers
Rs: Special-purpose
register
Rs: Special-purpose
register
MB91107/108
• Non-delay normal branch instructions (23 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
JMP
@Ri
E
97 – 0
2
– – – – Ri → PC
CALL
label12
F
D0
2
CALL
@Ri
E
97 – 1
2
– – – – PC + 2 → RP,
PC + 2 + rel11 × 2 → PC
– – – – PC + 2 → RP, Ri → PC
E
97 – 2
2
– – – – RP → PC
D
1F
3+3a
RET
INT
#u8
Remarks
Return
– – – – SSP – = 4, PS → (SSP),
SSP – = 4,
PC + 2 → (SSP),
0 → I flag,
0 → S flag,
(TBR + 3FC – u8 × 4) → PC
INTE
E
9F – 3 3 + 3a – – – – SSP – = 4, PS → (SSP),
For emulator
SSP – = 4,
PC + 2 → (SSP),
0 → S flag,
(TBR + 3D8 – u8 × 4) → PC
RETI
E
97 – 3 2 + 2a C C C C (R15) → PC, R15 – = 4,
(R15) → PS, R15 – = 4
BNO
BRA
BEQ
BNE
BC
BNC
BN
BP
BV
BNV
BLT
BGE
BLE
BGT
BLS
BHI
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
E1
E0
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
1
2
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Non-branch
PC + 2 + rel8 × 2 → PC
PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0
Notes: • “2/1” in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.
• The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and
assembler discription label9 and label12 are as follows.
label9 → rel8 = (label9 – PC – 2)/2
label12 → rel11 = (label12 – PC – 2)/2
• RETI must be operated while S flag = 0.
101
MB91107/108
• Branch instructions with delays (20 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
JMP:D
@Ri
E
9F – 0
1
– – – – Ri → PC
CALL:D
label12
F
D8
1
CALL:D
@Ri
E
9F – 1
1
– – – – PC + 4 → RP,
PC + 2 + rel11 × 2 → PC
– – – – PC + 4 → RP, Ri → PC
E
9F – 2
1
– – – – RP → PC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F1
F0
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RET:D
BNO:D
BRA:D
BEQ:D
BNE:D
BC:D
BNC:D
BN:D
BP:D
BV:D
BNV:D
BLT:D
BGE:D
BLE:D
BGT:D
BLS:D
BHI:D
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Remarks
Return
Non-branch
PC + 2 + rel8 × 2 → PC
PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0
Notes: • The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and
assembler discription label9 and label12 are as follows.
label9 → rel8 = (label9 – PC – 2)/2
label12 → rel11 = (label12 – PC – 2)/2
• Delayed branch operation always executes next instruction (delay slot) before making a branch.
• Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other
instruction is stored, this device may operate other operation than defined.
The instruction described “1” in the other cycle column than branch instruction.
The instruction described “a”, “b”, “c” or “d” in the cycle column.
102
MB91107/108
• Direct addressing instructions
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
DMOV
DMOV
DMOV
DMOV
DMOV
DMOV
@dir10,
R13,
@dir10,
@R13+,
@dir10,
@R15+,
R13
@dir10
@R13+
@dir10
@–R15
@dir10
D
D
D
D
D
D
08
18
0C
1C
0B
1B
b
a
2a
2a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir10) → R13
R13 → (dir10)
(dir10) → (R13), R13 + = 4
(R13) → (dir10), R13 + = 4
R15 – = 4, (dir10) → (R15)
(R15) → (dir10), R15 + = 4
Word
Word
Word
Word
Word
Word
DMOVH
DMOVH
DMOVH
DMOVH
@dir9,
R13,
@dir9,
@R13+,
R13
@dir9
@R13+
@dir9
D
D
D
D
09
19
0D
1D
b
a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir9) → R13
R13 → (dir9)
(dir9) → (R13), R13 + = 2
(R13) → (dir9), R13 + = 2
Half word
Half word
Half word
Half word
DMOVB
DMOVB
DMOVB
DMOVB
@dir8,
R13,
@dir8,
@R13+,
R13
@dir8
@R13+
@dir8
D
D
D
D
0A
1A
0E
1E
b
a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir8) → R13
R13 → (dir8)
(dir8) → (R13), R13 + +
(R13) → (dir8), R13 + +
Byte
Byte
Byte
Byte
NoteThe relations between the dir field of TYPE-D in the instruction format and the assembler description from
disp8 to disp10 are as follows:
disp8 → dir + disp8:Each disp is a code extension
disp9 → dir = disp9>>1:Each disp is a code extension
disp10 → dir = disp10>>2:Each disp is a code extension
• Resource instructions (2 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LDRES
@Ri+,
#u4
C
BC
a
– – – – (Ri) → u4 resource
Ri + = 4
u4: Channel number
STRES
#u4,
@Ri+
C
BD
a
– – – – u4 resource → (Ri)
Ri + = 4
u4: Channel number
• Co-processor instructions (4 instructions)
Mnemonic
COPOP
COPLD
COPST
COPSV
#u4, #CC, CRj, CRi
#u4, #CC, Rj, CRi
#u4, #CC, CRj, Ri
#u4, #CC, CRj, Ri
Type
OP
E
E
E
E
9F – C
9F – D
9F – E
9F – F
Cycle N Z V C
2+a
1 + 2a
1 + 2a
1 + 2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Calculation
Rj → CRi
CRj → Ri
CRj → Ri
Remarks
No error traps
103
MB91107/108
• Other instructions (16 instructions)
Type
OP
NOP
E
9F – A
1
– – – – No changes
ANDCCR #u8
ORCCR #u8
D
D
83
93
c
c
C C C C CCR and u8 → CCR
C C C C CCR or u8 → CCR
STILM
#u8
D
87
1
– – – – i8 → ILM
Set ILM immediate
value
ADDSP
#s10
D
A3
1
– – – – R15 + = s10
ADD SP instruction
EXTSB
EXTUB
EXTSH
EXTUH
Ri
Ri
Ri
Ri
E
E
E
E
97 – 8
97 – 9
97 – A
97 – B
1
1
1
1
–
–
–
–
LDM0
(reglist)
D
8C
*4
Load-multi R0 to R7
LDM1
(reglist)
D
8D
*4
* LDM
(reglist)
– – – – (R15) → reglist,
R15 increment
– – – – (R15) → reglist,
R15 increment
– – – – (R15 + +) → reglist,
STM0
(reglist)
D
8E
*
Store-multi R0 to R7
STM1
(reglist)
D
8F
*6
* STM2
(reglist)
*5
– – – – R15 decrement,
reglist → (R15)
– – – – R15 decrement,
reglist → (R15)
– – – – reglist → (R15 + +)
ENTER
#u10
*2
Mnemonic
LEAVE
XCHB
@Rj, Ri
*1
*3
Cycle N Z V C
–
6
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Remarks
Sign extension 8 → 32 bits
Zero extension 8 → 32 bits
Sign extension 16 → 32 bits
Zero extension 16 → 32 bits
Load-multi R8 to R15
Load-multi R0 to R15
Store-multi R8 to R15
Store-multi R0 to R15
D
0F
1+a
– – – – R14 → (R15 – 4),
R15 – 4 → R14,
R15 – u10 → R15
Entrance processing
of function
E
9F – 9
b
– – – – R14 + 4 → R15,
(R15 – 4) → R14
Exit processing of
function
A
8A
2a
– – – – Ri → TEMP,
(Rj) → Ri,
TEMP → (Rj)
For SEMAFO
management
Byte data
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler
description s10 is as follows.
s10 → s8 = s10>>2
*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler
description u10 is as follows.
u10 → u8 = u10>>2
*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,
assembler generates LDM1. Both LDM0 and LDM1 may be generated.
*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following
calculation; a × (n – 1) + b + 1 when “n” is number of registers specified.
*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,
assembler generates STM1. Both STM0 and STM1 may be generated.
*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following
calculation; a × n + 1 when “n” is number of registers specified.
104
MB91107/108
• 20-bit normal branch macro instructions
Mnemonic
Operation
Remarks
* CALL20
label20, Ri
Next instruction address → RP, label20 → PC
Ri: Temporary register
*1
* BRA20
* BEQ20
* BNE20
* BC20
* BNC20
* BN20
* BP20
* BV20
* BNV20
* BLT20
* BGE20
* BLE20
* BGT20
* BLS20
* BHI20
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20 → PC
if (Z = = 1) then label20 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*1: CALL20
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL
label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
CALL
@Ri
*2: BRA20
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
JMP
@Ri
*3: Bcc20 (BEQ20 to BHI20)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20 #label20, Ri
JMP
@Ri
false:
105
MB91107/108
• 20-bit delayed branch macro instructions
Mnemonic
Operation
Remarks
* CALL20:D label20, Ri
Next instruction address + 2 → RP, label20 → PC
Ri: Temporary register
*1
* BRA20:D
* BEQ20:D
* BNE20:D
* BC20:D
* BNC20:D
* BN20:D
* BP20:D
* BV20:D
* BNV20:D
* BLT20:D
* BGE20:D
* BLE20:D
* BGT20:D
* BLS20:D
* BHI20:D
label20 → PC
if (Z = = 1) then label20 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
*1: CALL20:D
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
CALL:D @Ri
*2: BRA20:D
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
JMP:D @Ri
*3: Bcc20:D (BEQ20:D to BHI20:D)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20 #label20, Ri
JMP:D @Ri
false:
106
MB91107/108
• 32-bit normal macro branch instructions
Mnemonic
Operation
Remarks
* CALL32
label32, Ri
Next instruction address → RP, label32 → PC
Ri: Temporary register
*1
* BRA32
* BEQ32
* BNE32
* BC32
* BNC32
* BN32
* BP32
* BV32
* BNV32
* BLT32
* BGE32
* BLE32
* BGT32
* BLS32
* BHI32
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32 → PC
if (Z = = 1) then label32 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*1: CALL32
(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL
label12
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
CALL
@Ri
*2: BRA32
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
JMP
@Ri
*3: Bcc32 (BEQ32 to BHI32)
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:32 #label32, Ri
JMP
@Ri
false:
107
MB91107/108
• 32-bit delayed macro branch instructions
Mnemonic
Operation
Remarks
* CALL32:D label32, Ri
Next instruction address + 2 → RP, label32 → PC
Ri: Temporary register
*1
* BRA32:D
* BEQ32:D
* BNE32:D
* BC32:D
* BNC32:D
* BN32:D
* BP32:D
* BV32:D
* BNV32:D
* BLT32:D
* BGE32:D
* BLE32:D
* BGT32:D
* BLS32:D
* BHI32:D
label32 → PC
if (Z = = 1) then label32 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
*1: CALL32:D
(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
CALL:D @Ri
*2: BRA32:D
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
JMP:D @Ri
*3: Bcc32:D (BEQ32:D to BHI32:D)
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:32 #label32, Ri
JMP:D @Ri
false:
108
MB91107/108
■ ORDERING INFORMATION
Part number
MB91107PFV
MB91108PFV
Package
Remarks
120-pin Plastic LQFP
(FPT-120P-M21)
109
MB91107/108
■ PACKAGE DIMENSIONS
120-pin Plastic LQFP
(FPT-120P-M21)
18.00±0.20(.709±.008)SQ
16.00±0.10(.630±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
LEAD No.
1
30
0.50(.020)
C
0~8°
"A"
31
0.22±0.05
(.009±.002)
0.08(.003)
M
0.145
.006
+0.05
–0.03
+.002
–.001
0.45/0.75
(.018/.030)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
1998 FUJITSU LIMITED F120033S-2C-2
Dimensions in mm (inches)
110
MB91107/108
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.