LF2246 LF2246 DEVICES INCORPORATED 11 x 10-bit Image Filter 11 x 10-bit Image Filter DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 66 MHz Data and Coefficient Input and Computation Rate ❑ Four 11 x 10-bit Multipliers with Individual Data and Coefficient Inputs and a 25-bit Accumulator ❑ User-Selectable Fractional or Integer Two’s Complement Data Formats ❑ Fully Registered, Pipelined Architecture ❑ Input and Output Data Registers, with User-Configurable Enables ❑ Three-State Outputs ❑ Fully TTL Compatible ❑ Ideally Suited for Image Processing and Filtering Applications ❑ Replaces TRW/Raytheon/Fairchild TMC2246 ❑ 120-pin PQFPP The LF2246 consists of an array of four 11 x 10-bit registered multipliers followed by a summer and a 25-bit accumulator. All multiplier inputs are user accessible and can be updated every clock cycle with either fractional or integer two’s complement data. The pipelined architecture has fully registered input and output ports and an asynchronous three-state output enable control to simplify the design of complex systems. The pipeline latency for all inputs is five clock cycles. Storage for mixing and filtering coefficients can be accomplished by holding the data or coefficient inputs over multiple clock cycles. A 25-bit accumulator path allows cumulative word growth which may be internally rounded to 16 bits. Output data is updated every clock cycle and may be held under user control. All inputs, outputs, and controls are registered on the rising edge of clock, except for OEN. The LF2246 operates at a clock rate of 66 MHz over the full temperature and supply voltage ranges. The LF2246 is applicable for performing pixel interpolation in image manipulation and filtering applications. The LF2246 can perform a bilinear interpolation of an image (4pixel kernels) at real-time video rates when used with an image resampling sequencer. Larger kernels or more complex functions can be realized by utilizing multiple devices. Unrestricted access to all data and coefficient input ports provides the LF2246 with considerable flexibility in applications such as digital filters, adaptive FIR filters, mixers, and other similar systems requiring high-speed processing. LF2246 BLOCK DIAGRAM D19–0 C110–0 ENB1 D29–0 C210–0 ENB2 D39–0 C310–0 ENB3 D49–0 C410–0 ENB4 ENSEL 10 11 10 11 10 22 11 10 11 22 ACC 25 OCEN MS FSEL LS OEN CLK TO ALL REGISTERS S15–0 Video Imaging Products 2-11 08/16/2000–LDS.2246-K LF2246 DEVICES INCORPORATED FIGURE 1A. 11 x 10-bit Image Filter INPUT FORMATS TABLE 1. Coefficient Data Fractional Two’s Complement (FSEL = 0) 9 8 7 –20 2–1 2–2 2 1 0 2–7 2–8 2–9 (Sign) 10 9 8 –21 20 2–1 2 1 0 2–7 2–8 2–9 (Sign) Integer Two’s Complement (FSEL = 1) 9 8 7 –29 28 27 2 1 0 22 21 20 (Sign) FIGURE 1B. 10 9 8 –210 29 28 2 1 0 22 21 20 (Sign) OUTPUT FORMATS Fractional Two’s Complement (FSEL = 0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 (Sign) Integer Two’s Complement (FSEL = 1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 (Sign) Controls Power ENB1–ENB4 — Input Enable The ENBN (N = 1, 2, 3, or 4) input allows either or both the DN and CN registers to +5 V power supply. All pins must be be updated on each clock cycle. When connected. ENBN is LOW, registers DN and CN are both strobed by the next rising edge of Clock CLK. When ENBN is HIGH and ENSEL CLK — Master Clock is LOW, register DN is strobed while The rising edge of CLK strobes all en- register CN is held. If both ENBN and abled registers. All timing specifica- ENSEL are HIGH, register DN is held, tions are referenced to the rising edge of and register CN is strobed (Table 1). CLK. ENSEL — Enable Select VCC and GND D19–0–D49–0 — Data Input D1–D4 are 10-bit data input registers. The LSB is DN0 (Figure 1a). C110–0–C410–0 — Coefficient Input C1–C4 are 11-bit coefficient input registers. The LSB is CN0 (Figure 1a). Outputs S15–0 — Data Output The current 16-bit result is available on the S15–0 outputs (Figure 1b). INPUT REGISTER HELD ENB1-4 ENSEL 1 1 Data ‘N’ 1 0 Coefficient ‘N’ 0 X None X = “Don’t Care” ‘N’ = 1, 2, 3, or 4 OCEN — Clock Enable When OCEN is LOW, data in the premux register (accumulator output) is loaded into the output register on the next rising edge of CLK. When OCEN is HIGH, data in the pre-mux register is held preventing the output register’s contents from changing (if FSEL does not change). Accumulation continues internally as long as ACC is HIGH, despite the state of OCEN. FSEL — Format Select SIGNAL DEFINITIONS Inputs INPUT REGISTER CONTROL The ENSEL input in conjunction with the individual input enables ENB1– ENB4 determines whether the data or the coefficient input registers will be held on the next rising edge of CLK (Table 1). When the FSEL input is LOW, the data input during the current clock cycle is assumed to be in fractional two’s complement format, and the upper 16 bits of the accumulator are presented at the output. Rounding of the accumulator result to 16 bits is performed if the accumulator control input ACC is LOW. When FSEL is HIGH, the data input is assumed to be in integer two’s complement format, and the lower 16 bits of the accumulator are presented at the output. No rounding is performed when FSEL is HIGH. ACC — Accumulator Control The ACC input determines whether internal accumulation is performed on the data input during the current clock cycle. If ACC is LOW, no accumulation is performed, the prior accumulated sum is cleared, and the current sum of products is output. If FSEL is also LOW, OEN — Output Enable When the OEN signal is LOW, the cur- one-half LSB rounding to 16 bits is perrent data in the output register is avail- formed on the result. This allows sumable on the S15–0 pins. When OEN is mations without propagating roundoff HIGH, the outputs are in a high-imped- errors. When ACC is HIGH, the emerging product is added to the sum of the ance state. previous products, without additional rounding. Video Imaging Products 2-12 08/16/2000–LDS.2246-K LF2246 DEVICES INCORPORATED 11 x 10-bit Image Filter MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –2.0 mA VOL Output Low Voltage VCC = Min., IOL = 4.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max 2.4 Unit V 0.4 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±10 µA Output Leakage Current (Note 12) ±40 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 100 mA ICC2 VCC Current, Quiescent (Note 7) 6 mA CIN Input Capacitance TA = 25°C, f = 1 MHz 10 pF COUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF Video Imaging Products 2-13 08/16/2000–LDS.2246-K LF2246 DEVICES INCORPORATED 11 x 10-bit Image Filter SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol Parameter tCYC Cycle Time tPWL Clock Pulse Width Low tPWH Clock Pulse Width High tS Input Setup Time tH Input Hold Time tD Output Delay tDIS Three-State Output Disable Delay (Note 11) tENA Three-State Output Enable Delay (Note 11) LF2246– 25 123456789012345678901234 123456789012345678901234 123456789012345678901234 123456789012345678901234 33* 123456789012345678901234 123456789012345678901234 123456789012345678901234 123456789012345678901234 Min Max 123456789012345678901234 123456789012345678901234 123456789012345678901234 123456789012345678901234 33 123456789012345678901234 123456789012345678901234 123456789012345678901234 123456789012345678901234 123456789012345678901234 15 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tPWH Clock Pulse Width High tS Input Setup Time tH Input Hold Time tD Output Delay tDIS Three-State Output Disable Delay (Note 11) tENA Three-State Output Enable Delay (Note 11) LF2246– 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 * 33 25* 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 Min Max Min Max 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 33 25 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 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123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE Video Imaging Products 2-14 08/16/2000–LDS.2246-K LF2246 DEVICES INCORPORATED 11 x 10-bit Image Filter NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. where 4 10. Each parameter is shown as a min- 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 30 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency Video Imaging Products 2-15 08/16/2000–LDS.2246-K LF2246 DEVICES INCORPORATED 11 x 10-bit Image Filter ORDERING INFORMATION 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 ENSEL ENB4 ENB1 ENB2 ENB3 D49 D48 D47 D46 D45 D44 D43 D42 D41 GND D40 C410 C49 VCC C48 C47 C46 C45 C44 C43 C42 C41 C40 C30 C31 120-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Top View C32 C33 C34 C35 C36 C37 C38 C39 C310 D30 D31 D32 D33 D34 D35 D36 D37 D38 GND D39 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 C110 C19 C18 C17 C16 GND C15 C14 C13 VCC C12 C11 C10 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C210 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 CLK FSEL ACC OCEN OEN S15 S14 GND S13 S12 S11 VCC S10 S9 S8 GND S7 S6 S5 VCC S4 S3 S2 GND S1 S0 D19 D18 D17 D16 Plastic Quad Flatpack (Q1) Speed 0°C to +70°C — COMMERCIAL SCREENING 25 ns 15 ns LF2246QC25 LF2246QC15 –40°C to +85°C — COMMERCIAL SCREENING Video Imaging Products 2-16 08/16/2000–LDS.2246-K LF2246 DEVICES INCORPORATED 11 x 10-bit Image Filter ORDERING INFORMATION 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 120-pin 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 2 3 4 5 6 7 8 9 10 11 12 13 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 ACC FSEL ENB4 D49 D46 D43 D40 C49 C47 C44 C42 C30 C35 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 S15 OEN CLK ENB1 D48 D44 GND VCC C45 C41 C31 C33 C36 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 D 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C34 C37 C39 S13 S14 OCEN 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 KEY 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 E 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C38 C310 D30 S11 S12 GND 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 F 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Top View S9 S10 VCC D31 D32 D33 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Through Package 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 G 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 S7 S8 GND D35 D36 D34 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 (i.e., Component Side Pinout) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 H 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 S6 S5 VCC GND D38 D37 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 J 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 D27 D29 D39 S4 S3 GND 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 K 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 S2 S1 D18 D23 D26 D28 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 L 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 S0 D17 D15 D12 C19 GND VCC C20 C24 C28 D20 D24 D25 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 M 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 D19 D14 D11 C110 C17 C15 C13 C10 C22 C25 C29 D21 D22 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 N 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 D16 D13 D10 C18 C16 C14 C12 C11 C21 C23 C26 C27 C210 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Discontinued Package 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Ceramic Pin Grid Array (G4) Speed 0°C to +70°C — COMMERCIAL SCREENING –40°C to +80°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Video Imaging Products 2-17 08/16/2000–LDS.2246-K