HA13609ANT Three-Phase Brushless Motor Driver ADE-207-232 (Z) 1st. Edition May 1997 Description The HA13609ANT is a 3-phase brushless motor driver IC with digital speed control. It is designed for use as a PPC or LBP scanner motor driver and provides the functions and features listed below. Function • • • • • • • • • • • • • • • Power MOS and power bipolar transistor driver circuits 16-bit serial interface Variable-speed digital speed control circuit Digital PLL Digital ready circuit PWM oscillator circuit Charge pump circuit Integrating amplifier circuit Current limit circuit Overshoot prevention circuit Braking function (with braking compete signal) Forward/reverse direction circuit Hall open circuit protection Watchdog timer (LVI, POR, and RST outputs) Stuck rotor protection Features • • • • • • • • High breakdown voltage (50V/30mA) power transistor drive circuit PWM drive Variable speed control is possible (varying the servo filter constants is not required) Selectable rotation control method (discriminator control, PLL plus discriminator control) Selectable feedback type (voltage or current) Allows both PWM frequency switching and 100% duty operation Selectable current limiting level Braking mode selection (reverse braking, regeneration braking) HA13609ANT Block Diagram VSS (5 V) VPS C101 VSS = Bip use C102 10 to 50 V= MOS use VSS 21 R101 25 Hall amplifier 42 U+ + U 41 U– – U 40 V+ + V 39 V– – 38 W+ + W 37 W– – W Hu Hv Hw VSS Matrix Open circuit protection R102 R126 R/F RWD/FWD 20 1.25 V R127 22 P.O.R V FH × 3 Overshoot preven- OSI tion 33 32 31 C106 fPWM – BRAKE 40 k + PWM comp. No/8 Counter Monitor output 7 (Ready: Low) – Error amp + 27 Current feedback input 17 Error amplifier input MASK DATA OUT 4 CLK 1 fMAX = 8 MHz ENABLE 2 Serial port (16 bits) DATA 3 FH × 3 Rotation monitor output 6 VSS 34 Duty 100 L.V.I BRAKE 35 (Push-pull) 12 PWM OSC C108 RST 8 36 (Open collector) 1.4 V MOTOR ON BRAKE (2 bit) DUTY 100 READY O.S.I ON VRef (2 bit) MASK CONTROL RWD/FWD D1 (2 bit) D2 (2 bit) PLL SEL OR Icp, PC ON VP (3 bit) fPWM (2 bit) MODE SEL D1 + AMP – 29 MR 28 Waveform shaping Current sense – VSS MASK R106 + 24 VRef 1.1 V Stuck rotor protector Buffer 9 OSC Ready Precharge 10 30 R3 15 R7 Charge pump PLL 11 16 C3 Discriminator 19 R1 Vp 1M 23 Integral – + CONT. Ready ±4, ±8% Programmable discriminator (1024 to 4095) D2 – + C105 PC D1 D2 13 Vp 14 R4 R6 20 p 2 8 MHz MAX R107 18 VRef Icp × 2 SPEED CLK 5 (0.2 to 5 kHz) 26 C4 20 p R5 HA13609ANT Pin Functions Pin No. Pin Name Function 1 CLK Serial port reference signal input 2 ENABLE Serial port data write/latch signal input 3 DATA Serial port data input 4 DATA OUT Serial port data transfer complete signal output 5 SPEED CLK Speed command signal input 6 TACHO OUT Rotation monitor (MR, Hall ×3) output 7 READY Ready and braking done (no/8) output (open collector output) 8 RST Power supply (V SS ) monitor output. High when a reduced power-supply voltage is detected. 9 OSC IN Oscillator circuit input. Reference signal for all circuits other than the serial port. 10 OSC OUT Oscillator circuit output 11 S-GND Small-signal ground 12 PWM OSC Connection for the capacitor that sets the oscillator frequency. 13 PLL OUT SPEED CLK vs. speed detection signal speed comparison output 14 DIS OUT SPEED CLK vs. speed detection signal phase comparison output 15 INTEG IN Integrating amplifier input 16 CP OUT Charge pump and integrating amplifier output 17 ERROR AMP IN Error amplifier input 18 BUFFER OUT Buffer amplifier output. Connect to pin 17 when current feedback is selected. 19 R1 Charge pump output current and PWM oscillator frequency setting 20 LVI Reduced voltage detection level setting 21 VSS Small-signal circuit power supply. 5.5V maximum 22 POR Power-on reset delay time setting 23 LOCK PRO Motor rotation constraint mode coil current on/off time setting 24 VRef Current limit setting 25 VPS Output driver power supply. 50V maximum 26 C Sense Motor coil current detection 27 CFB Current feedback input 28 MR IN – Speed detection input 29 MR IN + Speed detection input 30 P-GND Output driver ground 3 HA13609ANT Pin Functions (cont) Pin No. Pin Name Function 31, 33, 35 U, V, W Lower arm driver push-pull output. Driven by a PWM signal. (Connect power NMOS or NPN transistors.) 32, 34, 36 U, V, W Upper arm driver open drain output. (Connect a power PMOS or PNP transistor.) 37 to 42 U+, U– V+, V– W+, W– Hall signal inputs 4 HA13609ANT Serial Port Input Data Structure MSB LSB A4 A3 A2 Dummy Dummy A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Mode control A0 = 1 Data control A0 = 0 DATA OUT DATA CLK ENABLE Serial port (16 bits) A0 Decoder Mode control register (11 bits) A0 = 1 Mode control Data control register (11 bits) A0 = 0 Data control Mode Control Register (A0 = 1) Bit 1 Symbol MD1 BRAKE 1 MD2 BRAKE 2 MD3 DUTY 100 MOTOR OFF 1 0 1 0 1 1 BRAKE OFF Brake Brake Brake 1 2 3 DUTY 100% DUTY MD4 READY 4% MD5 O.S.I ON Active MD6 VRef 1 MD6 MD7 MD7 VRef 2 VRef MD8 MASK ×2 MD9 CONTROL Discriminator Discriminator + PLL MD10 R/F Reverse Forward MD0 MOTOR ON MOTOR ON MD1 MD2 0 0 0 8% *1 *2 Non Active 0 0 VRef ×2 1 0 ← ×1 0 1 ← ×0.75 1 1 ← ×0.5 ×1 *3 5 HA13609ANT Data Select Register (A0 = 0) Symbol Bit DD0 D1 A DD1 D1 B DD2 D2 A DD3 D2 B DD4 PLLSEL1 OR Icp 1 0 DD0 DD1 D1 0 0 1/1 1 0 1/2 0 1 1/4 1 1 1/8 DD2 DD3 D2 0 0 1/1 1 0 1/2 0 1 1/4 1 1 1/8 1 0 1 1 1 0 ← ← ← ×100% ×75% ×50% ×25% 0 0 0 1 0 1 0 0 1 0 0 0 0 0 DD5 DD4 DD5 PLLSEL2 OR PC ON PLL OUT(Vp-p) DD6 VP1 DD7 VP2 DD6 DD7 DD8 DD8 VP3 VP (V) 2.2 +0.15 +0.3 +0.45 DD9 fPWM1 DD9 DD10 0 0 DD10 fPWM2 fPWM fPWM ×1 1 0 ← ×1.4 0 1 ← ×1.9 1 1 ← ×2.8 *4 1 1 0 1 0 1 0 1 1 1 1 1 +0.6 –0.15 –0.3 –0.45 *5 *6 Notes: 1. Off: The brake function does not operate. Brake 1: Braking up to No/8. Brake 2: Braking up to No/8, and then regenerative braking. Brake 3: Regenerative braking. The No/8 signal is output. During a braking operation, when the MR frequency when braking completes cannot be detected in the circuit (During braking, the speed detection signal for under setting is not output over the 2/D1 occurrence. Thus this occurs more easily for lower settings.), reverse rotation may continue in some cases. Note that this bit is also used to set the rotation monitor output (FH × 3 or the MR frequency). FH × 3 is only output from the rotation monitor when motor on (MD0 = 1) and brake 3 are selected. 2. The ready setting range has the following manufacturing variation: 4.3% ±25% (@MD4 = 1) 8.6% ±25% (@MD4 = 0) 3. This function masks the current limiter input (pin 27) (incorrect operation due to the recovery current). See page 20 for details. 4. The PLL output setting indicates a change relative to 3.5 Vp-p. See the electrical characteristics. This is valid when MD9 = 0 (PLL control). Note that DD4 also functions as the Icp selection in discriminator control mode. VR1 Icp = 4 · R1 DD4 = 1 . . . . . Icp × 2 @MD9 = 1 DD4 = 0 . . . . . Icp × 1 6 HA13609ANT DD5 also controls the PC on function to reduce motor rotation overshoot when MD9 is 1 (discriminator control). This function does not operate when D9 is 0. The precharge voltage (i.e., the integrator output voltage initial clamp voltage) can be set by Vp1 to Vp3 (DD6 to DD8). The figure shows the precharge operation. MD0 or MD10 Ready lock range (MD4) NO Integrator output Vp 0V Precharge 5. The Vp setting indicates the change relative to 2.2V. See the electrical characteristics. 6. Indicates the change relative to f PWM. See the setting formula. 7 HA13609ANT Timing Chart (Forward Mode) Hu + Hv Hw Vhys Hall amplifier input 0 – VOH1 U output VOL VOH1 V output VOL VOH1 W output VOL VOH U output PWM PWM VOL VOH V output PWM PWM VOL VOH W output PWM VOL 8 PWM HA13609ANT Serial Port Timing Chart tr, tf < 20 nsec, tsu, th > 20 nsec The tr and tf times are stipulated tw > 40 nsec at 10% and 90%, respectively. th ENABLE tsu th 50% tsu CLK 50% tw A4 DATA tsu th tw A3 D1 tsu 50% D0 tsu 50% DATA OUT td1 ≤ 50 nsec td2 ≤ 50 nsec Braking Function Input and Output Logic Serial Port Input Output MOTOR ON (MD0) BRAKE 1 (MD1) BRAKE 2 (MD2) R/F (DD10) Rotation Direction Braking 1 * * 0 Forward OFF * * 1 Reverse OFF 0 0 * — OFF *2 * * 0 Reverse Brake *3 * * 1 Forward 0 *1 Notes: 1. OFF: The braking function does not operate. 2. The IC goes to standby mode. 3. See the description of mode control for details on the braking operation. 9 HA13609ANT Braking set N1 Braking or regeneration braking Forward 0 Reverse Regeneration braking N2 MDO (MOTOR ON) MD10 (R/F) MD1 (BRAKE1) to MD2 (BRAKE2) *3 tset up Rotation monitor output set Braking set *1 *3 thold SPEED CLK input Monitor output (open drain) Rotation monitor output set *2 N1 N2 Ready Ready *3 tset up N1 *4 No/8 detection Ready Notes: 1. The IC goes to standby mode when MOTOR ON, BRAKE1, and BRAKE2 are all 0. 2. Hold the data values here. 3. thold, tset up > 1 ×4 fSPEED CLK 4. The No/8 (braking completion) function does not operate when BRAKE1 and BRAKE2 are 0. Note that the No/8 detection signal is initialized to the high level in the mode in note 1 (standby mode). 10 HA13609ANT Basic Application Circuit (Bipolar Transistor Circuit, Discriminator + PLL, Voltage Feedback, and Hall Elements) VSS VPS C101 VSS R101 21 25 VSS VPS R114 R108 42 U+ Hu U 36 Q1 D1 41 U– 40 V+ Hv U 35 R109 Q2 D2 R117 39 V– R115 38 W+ Hw R110 37 W– V 34 R126 20 LVI R127 V 33 VSS R102 Q3 R111 Q4 D3 D4 R118 R116 R112 22 P.O.R C108 W 32 8 RST W 31 Q5 R113 Q6 D5 D6 R119 7 Monitor output R120 4 DATA OUT Current limiter 26 MPU C107 1 CLK VSS C106 2 ENABLE RNF PWMOSC 12 R106 3 DATA VRef 24 R107 C105 5 SPEED CLK Lock protection 23 VSS MR Current feedback input 27 29 MR IN+ Error amplifier input 17 Buffer amplifier output 18 Rotation monitor 6 output Integrator output 16 28 MR IN– C103 C3 9 OSC IN X’tal R105 C104 PLL 30 R7 19 10 OSC OUT 11 R3 Integrator input 15 13 R1 Discriminator 14 R4 R6 C4 R5 11 HA13609ANT Application Circuits Application Circuit 1 (Discriminator) Error amplifier input 17 Buffer amplifier output 18 Integrator output 16 C3 Integrator input 15 PLL Discriminator 13 14 C1 R2 19 R1 Application Circuit 2 (MOS Transistor Circuit) VSS VPS C101 C102 21 25 VSS VPS ZD1 R114 R108 U 36 U 35 M1 R109 M2 D1 D2 R117 ZD2 R115 R110 V 34 V 33 M3 R111 M4 D3 D4 R118 ZD3 R116 R112 W 32 W 31 M5 R113 M6 R119 RNF 12 D5 D6 HA13609ANT Application Circuit 3 (Current Feedback) RNF R125 Current feedback input 27 R121 Error amplifier input 17 C110 Buffer amplifier output 18 Application Circuit 4 (Hall IC input) VSS R103 C101 R104 VSS 21 VSS R122 IC 42 U+ 41 U– R123 IC 40 V+ 39 V– R124 IC 38 W+ 37 W– Application Circuit 5 (External Reset Input) VSS R126 20 LVI External reset input H: standby 22 P.O.R C108 8 RST 13 HA13609ANT External Components Part No. Recommended Value Purpose Note R101, R102 — Hall element bias current 12 R103, R104 — Hall IC applications, Hall input voltage 14 R105 1MΩ Oscillator stabilization R106, R107 — Current limiter reference voltage 15 R108 to R113 — Power transistor base current limiter 16 R114 to R119 — Power transistor base-emitter resistors (gate-source resistors) 16 R120 ≥ 4.7kΩ Current limiter filter 13 R121 — Current feedback input filter 9 R122 to R124 — Hall IC output current 14 R125 — Current feedback input gain adjustment 10 R126, R127 — LVI operating voltage, external reset input pull up 11 RNF — Current detection 1 R1 ≥ 1.5kΩ Integration constant, PWM carrier frequency 2, 3, 5 R2 — Integration constant 2 R3 to R7 — Integration constant 3 C101, C102 ≥ 0.1µF Power supply stabilization C103, C104 10p to 50pF Oscillator stabilization 7 C105 — Lock protection operation time 4 C106 — PWM carrier frequency 5 C107 — Current limiter filter 13 C108 — Power-on reset delay time 11 C110 — Current feedback input filter 9 C111 to C113 — Hall output stabilization 8 C1 — Integration constant 2 C2 — Integration constant 2 C3, C4 — Integrator filter 3 ZD1 to ZD3 ≈ 20V MOS power transistor gate destruction protection 8 D1 to D6 — Fly wheel diodes 8 X’tal 4 to 8MHz Oscillator 6, 7 Notes: 1. Current limiter operates according to the following formula: V Iop = Ref [A] RNF Here, V Ref is the value according to the VRef select function. 14 HA13609ANT 2. Use the following formulas as a guideline for setting the integration constant (@MD9 = 1). To minimize rotation deviation, set R1 to a relatively small value. 2π ωo ≤ · f · D1 [rad/s] 20 MR R1 = 9.55 · VR1 · KT · R2 ·A 4 · J · ωo · No [Ω] However, R1 must be in the range 1.5kΩ ≤ R1 ≤ 15kΩ. C1 = 1 / (√10 · ωo · R2) [F] C2 = 10 · C1 [F] : Rotation speed [min–1 ] : MR frequency [Hz] : Divider determined by D1 select : Charge pump bias voltage 1.16 [V] : Motor torque constant [N·m/A] : Motor moment of inertia [kg·m2] : PWM comparator current gain [A/V] 2Vps – 0.83VE – Vsat Voltage feedback method: A = Rm · Vosc Here, No f MR D1 VR1 KT J A Current feedback method: A = GB RNF VPS : Power system power-supply voltage [V] VE : Motor back EMF [V P-P/T·T] Vsat : External transistor saturation voltage [V] (See the electrical characteristics) Rm : Motor coil resistance [Ω/T·T] Vosc : PWM amplitude voltage [V P-P] (See the electrical characteristics) GB : Buffer amplifier gain [V/V] (See the electrical characteristics) 3. Use the following formulas as guidelines for setting the integrator filter: First determine the angular frequency of ωP for DIS OUT and PLL OUT. ωP = 2π · fMR · D1 [rad/s] Determine the angular frequency of ωM for Motor. 9.55 1 Vref · KT · – TL [rad/s] ωM ≈ No J RNF Determine the ωo. ωo = √ωP · ωM [rad/s] Determine the integrator’s DC gain G(E) . J · ωo 1 G(E) = · 9.55 · KT · A Z Kø · D1 · 2π · · PLL SEL ωo 60 Here, Kø : PLL gain = 0.28 TL : Rated load torque PLL SEL : PLL output ratio Vref : Current limiter reference voltage Z : MR pulse per round [V/rad/s] [N·m] [V] [P/R] 15 HA13609ANT Set C3 and derive the integration constants from following formulas. R6 = 0 Ω 1 R3 = ωP · C3 R5 = R3 G(E) 1 2 · R5 · ωo R7 = R5 C4 = Next, determine R4 to match the phase of PLL OUT. (3.46 – VP) R3 R4 = (VP – 1.2) – (1.9 – VP) · R3 / R5 Here, VP : See the electrical characteristics. When log ωP/ω M is greater than 2, a phase advance to compensate for this phenomenon is required. Use the following formula to set the phase advance; C5 · R8 > 20 · 2 ωP R4 DIS R6 R7 R8 PLL C4 R5 C5 4. The following formulas determine the stuck rotor protect detection time t LP (detects the current limiter operating time), the output off time t OFF, and the setup time tset. The figures show the operating waveforms. tLP = ∆V1 · C105 ≈ 0.09 × 106 · C105 [sec] Isink ∆V2 tOFF = · C105 ≈ 0.32 × 106 · C105 [sec] Isource V tset = LH2 · C105 ≈ 0.0005 × 106 · C105 [sec] Is See the electrical characteristics for the definitions of ∆V1, ∆V2, Isink, Isource, and Is. Standby (MD0k to 2 = Low) Enable Current limiter operation IRNF 0 Lock VLH1 protect VLH2 pin VLL 0 ∆V1 ∆V2 tLP tset tOFF tLP Output off Note that a capacitor with a leakage current sufficiently smaller that Isource must be used for C105. 16 HA13609ANT 5. The PWM carrier frequency fPWM is determined by the following formula: 1 [Hz] fPWM = 0.0489 C106 · R1 6. The relationships between the crystal oscillator frequency fOSC and the speed command clock f CLK , the speed detection signal fMR, and the discriminator resolution (number of counts) C are shown below. f CLK = fMR·D1 f OSC = fCLK ·1 / D2·C [Hz] However, C must be in the range 1024 ≤ C ≤ 4095 Here, D1 : The MR signal divisor determined by D1 select D2 : The crystal oscillator frequency divisor determined by D2 select. Configuration of the speed control and phase control blocks when @MD9 = 0 Buffer amplifier Speed signal fMR D1 fMR’ 16 C3 R3 – + SPEED CLK fCLK CLK counter Discriminator counter setting X’tal fOSC D2 Discriminator (1024 to 4095) Charge pump 15 R7 19 4Icp PLL PLL SEL Discriminator R1 Vp Discriminator output 14 4% pulse R4 PLL output 13 R5 R6 C4 Note: If possible, Tr and Tf for the SPEED CLK signal should be under 20 ns when using this circuit. 17 HA13609ANT Timing in phase control mode fMR' A ≈ 3.6 V Discriminator output ≈0V A ACC ACC A × 4% ACC A × 4% DEC ≈ 3.6 V PLL output ≈ 1.85 V ≈0V ACC ACC DEC ACC ∆Vo Integrator output Configuration of the speed control block when @MD9 = 1 Speed signal fMR D1 SPEED CLK fCLK fMR’ Buffer amplifier CLK counter Discriminator counter setting X’tal fOSC D2 Discriminator (1024 to 4095) 16 C2 R2 C1 Charge pump R1 19 4Icp R1 Note: If possible, Tr and Tf for the SPEED CLK signal should be under 20 ns when using this circuit. 18 HA13609ANT 7. The table below lists reference values for the stabilization capacitors C103 and C104 for the crystal oscillator element according to the frequency used. X’tal (MHz) C103, C104 (pF) 4 to 6 ≈ 20 to 40 6 to 8 ≈ 10 to 20 Use a resonance resistance of under 50Ω as a criterion for selecting the crystal element used. 8. Include these components if required. 9. The cutoff frequency of the filter formed by C110 and R121 should be between 3 and 10 times the PWM oscillator frequency. 10. The gain, GCTL, from the error amplifier input to RNF is given be the following formula: Rif GCTL = 1 + R125 11. The formulas below determine the relationship between capacitor C108, which sets the power on reset (POR) delay time, and the resistors R126 and R127, which set LVI. R126 [V] VLVI = VSD 1 + R127 However, V LVI > 3V VHYS = R126 · IHYS [V] However, V LVI – VHYS > 2.5V t POR = 0.052 × 10 6 · C108 [sec] The time t POR is the time required for the oscillator to reach stability. This time should be 20ms or longer. VSD, IHYS: See the electrical characteristics. VHYS VLVI VSS < 2.0 V 0V POR 2.0 V 1.3 V 0V tPOR tPOR RST 0V When using an external reset input to set the IC to the standby state, pin 20 must be set to a low level that is under 0.4V. 12. When the Hall inputs are common mode input, the open circuit protection circuit makes the output transistors non-operational. When all the Hall input phases are open, the lower side output transistors become non-operational. The output transistors will be disabled if one or two phases are disconnected (become open) only when the Hall inputs are common mode. 19 HA13609ANT 13. When setting up the current limiter filter consisting of R120 and C107, R120 should be 4.7kΩ or larger, and C107 and R120 should function as a filter for the recovery current. This filter masks the recovery current due to internal circuits for the current limiter input (pin 26) and the C107 discharge operation determines the PWM off time (by making the current limiter input a low impedance). See the figures. 1/fPWM ON ON Output (U to W) VRNF C107 discharge tMASK tMASK Current limiter input voltage (pin 26) ≈0V For recovery current masking: 48 64 to fosc fosc @MD8 = 1 tMASK = 24 32 to fosc fosc @MD8 = 0 tMASK = [SEC] [SEC] 14. Use the formula below as a guideline for determining the values of R103, R104, and R122 to R124 when a Hall IC is used. R103 // R104 = R122 to R124 < 20kΩ 15. Take the current limiter input current (see the electrical characteristics) into consideration when determining the values for R106 and R107. 16. Determine the values of R108 to R119 based on the characteristics of the output power transistors used and the output driver characteristics (see the electrical characteristics). 17. Design the wiring in applications so that the potential of the pin 11 ground (the small-signal ground) does not become higher than that of the pin 30 ground (the output stage ground) as shown in the figure. VSS 20 11 30 HA13609ANT Absolute Maximum Ratings Item Symbol Rated Value Unit Note Power-supply voltage VSS 5.5 V 1 VPS VSS to 50 V 2 Input voltage VIN VSS V 3 Output voltage Vout 50 V 4 Output current Iout 30 mA 5 Allowable power dissipation PT 0.8 W Operating temperature Topr –20 to 70 °C Storage temperature Tstg –55 to +125 °C Notes: 1. A surge voltage of 6.0V is allowed for up to 10ms. Note that the operating range is as follows: VSS = 4.25 to 5.5V 2. The maximum is VSS if bipolar transistors are used as the output transistors. The maximum is 50 V if bipolar transistors are used as the output transistors. 3. Applies to the logic input pins 1, 2, 3, 5, and 9, and to the analog input pins 17, 20, 24, 26 to 29, and 37 to 42. 4. Applies to the output pins 32, 34, and 36, and to pin 7, the monitor output pin. 5. Applies to the output pins 31 to 36. The maximum value for the monitor output pin is 10mA. 21 HA13609ANT Electrical Characteristics Test Condition Applicable Pins Notes mA MD0 to 2 = 0, VSS = 5.5V 21 6 25 mA MD0 to 2 = 1, VSS = 5.5V 0.13 0.5 mA MD0 to 2 = 0, VPS = 50V 25 6 — 2.5 3.5 mA MD0 to 2 = 1, no load, VPS = 50V IIL — –50 –100 µA Input highlevel current IIH — 0 ±10 µA Input lowlevel voltage VIL — — 1.5 V Input highlevel voltage VIH 3.5 — — V Clock frequency fCLK 4 — 20 MHz Output highlevel voltage VOH1 3.5 4.6 — V IOH = 0.5mA Output lowlevel voltage VOL1 — 0.25 0.4 V IOL= 0.5mA Input resistance Rh — 10 ±25% kΩ Commonmode input voltage range Vh 1.5 — VSS–1.5 V Differentialmode input voltage range Vd 70 — VSS/2 mV Hysteresis VHYS — 40 — mV Rh = 400Ω Output highlevel voltage VOH2 VPS–1.8 VPS–1.6 — V IOH = 20mA, VPS = VSS VOH2 10 12.5 15 V IOH = 1mA, VPS = 24V VOH2 5.5 9.0 — V IOH = 1mA, VPS = 12V Item Symbol Min Typ Max Unit Current drain ISSO — 3.0 6.5 ISS — 15 IPSO — IPS Input lowlevel current Logic inputs Logic outputs Hall amplifier Output drivers 22 1 to 3, 5, 9 9 4, 6, 8, 10 37 to 42 1, 2 31, 33, 35 HA13609ANT Electrical Characteristics (cont) Symbol Min Typ Max Unit Test Condition Applicable Pins Output leakage current ILEAK — — ±100 µA VOH1 = 50V 32, 34, 36 Output lowlevel voltage VOL2 — 0.15 0.3 V IOL = 20mA 31 to 36 Output response time TPHI — — 1.0 µs IO = 10mA TPLH — — 1.0 µs Item Output drivers 3 PWM oscillator and Oscillator lowlevel voltage VL — 1.1 ±10% V PWM comparator Oscillator highlevel voltage VH — 2.8 ±10% V Oscillator frequency range fPWM 2 — 30 kHz Oscillator frequency precision ferr1 — 7.7 ±10% kHz Comparator hysteresis VPHYS — 50 — mV Input current IIN1 — — ±10 µA Vi = 0 to 2V 24, 26 Offset voltage VOFF –15 –25 –40 mV Vi = 0.5 to 2V 26 Common-mode input voltage range VCM 1.5 — VSS –1.5 V Differentialmode input voltage range VDIFF 60 — VSS mVP-P Gain Gain — 32 — dB f = 1kHz Input current IIN2 — — ±20 µA Vi = 1.4V I28 –146 –95 –62 µA Vi = 0V I29 –67 –53 –39 µA Vi = 0V Input current ratio Iratio 1.45 — 2.25 — I28 / I29 Input sensitivity VS 15 — — mV Current limiter Speed detection amplifier Notes 12 2 fPWM × 1, R1 = 6.2kΩ, C106 = 1000pF 2 28, 29 2 6 2 23 HA13609ANT Electrical Characteristics (cont) Symbol Min Typ Max Unit Test Condition Applicable Pins Oscillator frequency range fosc 4 — — MHz X’tal 9, 10 Oscillator frequency precision ferr2 — — ±0.01 % X’tal = 8MHz Program -mable Count range N 1024 — 4095 Count discriminator Operating frequency fdis — — 20 MHz Count error DC 0 — 1LSB — R1 voltage VR1 — 1.16 ±10% V R1 = 1.5kΩ 19 Charge current ICP+ — 190 ±10% µA R1 = 1.5kΩ, 16 Discharge current ICP– — 190 ±10% µA Vo = 2.0V Current ratio ICP+/ICP– 0.8 1.0 1.2 — Leakage current Ioff1 — — ±100 nA Clamp voltage Vclamp 2.8 3.0 — V Digital ready Lock range manufacturing variation ∆N — — ±25 % 7 Precharge Clamp voltage (1) Vcp(1) — Vp ±10% V 16 Buffer amplifier Internal reference voltage Vref — 1.15 ±10% V 16 Output resistance Ro 9.8 14 18.2 kΩ 18 Maximum output voltage VB(MAX) — 0.7 ±10% V Voltage gain GB –8 –6 –4 dB Input current IIN3 — — ±150 nA Offset voltage Voff — –25 –50 mV Voltage gain Ge — 60 — dB Gain-bandwidth product Be — 0.1 — MHz Feedback resistance Rif — 40 ±25% kΩ Item Clock oscillator Charge pump Error amplifier 24 Notes 2 14, 16 4 Vi = 1.5V Vi = 1.5V Vi = 2.5V 17, 27 2 2 VSS = 5V HA13609ANT Electrical Characteristics (cont) Symbol Min Typ Max Unit Test Condition Applicable Pins Internal reference voltage Vp — 2.2 ±10% V DD6 to 8 = 0 15, 16 Internal reference voltage difference ∆Vp — 2.2+∆Vp ±10% V Input current IIN4 — — ±250 nA Vi = 1.5V Output voltage VOH3 2.75 3.0 — V Io = 0.5mA VOL3 — — 0.9 V Io = 0.5mA Voltage gain GI — 60 — dB Vi = 2.5V Gainbandwidth product BI — 0.3 — MHz PLL and offset Output highlevel voltage VOH4 — 3.6 ±10% V discriminator output Output lowlevel voltage VOL4 — 0.1 0.2 V Monitor output Output leakage current ILEAK2 — — 50 Output lowlevel voltage VOL5 — 0.2 Minimum detection time tLP — Output off time tOFF High-level Item Integrating amplifier Stuck rotor protector Notes 2 2 Io = 0.1mA 13, 14 µA VOH = 50V 7 0.4 V IOL = 10mA 40 ±25% ms C105 = 0.47µF — 165 ±25% ms VLH1 3.0 3.2 — V voltage VLH2 2.5 2.7 — V Low-level voltage VLL — 1.4 1.6 V Potential ∆V1 — 1.9 ±10% V VLH1–VLL difference ∆V2 — 1.35 ±10% V VLH2–VLL Detection-time sink current ISINK — 25 ±30% µA Pin 23 voltage = 2.5V Output off source current ISource — 5.0 ±30% µA Pin 23 voltage = 2.5V Standby-mode source current IS — 4.7 ±35% mA Pin 23 voltage = VLH 23 2 2 25 HA13609ANT Electrical Characteristics (cont) Symbol Min Typ Max Unit Test Condition Applicable Pins Internal reference voltage Vsd 1.13 1.21 1.29 V Turn on 20 Hysteresis current IHYS — 50 ±25% µA Output voltage maintained range VLV 2.0 — — V Delay time tPOR — 24.5 ±25% ms Item LVI P.O.R 21 C108 = 0.47µF 8, 22 Notes: 1. Timing chart 2. Design target values. These are not tested at delivery time. 3. The figure below stipulates the output response time. This is not tested at delivery time. 90% 10% TPLH TPHL 4. Stipulated at the discriminator input frequency. 5. See the timing charts. 6. Stipulated at conditions in which the OSC input is fixed. 26 Notes HA13609ANT Reference Data Current Drain vs. Supply Voltage Current Drain vs. Supply Voltage 30 4 Tj = 25°C Current Drain IPS, IPSO (mA) Current Drain ISS, ISSO (mA) Tj = 25°C 20 ISS 10 3 IPS 2 1 ISSO IPSO 0 1.5 2.5 3.5 4.5 0 10 20 30 40 50 Supply Voltage VSS (V) Supply Voltage VPS (V) Output Driver Low-Level Voltage vs. Output Current Output Driver High-Level Voltage vs. Output Current 0.4 C 5° Tj 0.3 = 12 = °C 25 0.2 Tj 0.1 – Tj = 20° C 0 0 0 5.5 10 20 Output Current IO (mA) 30 Output Driver High-Level Voltage VOH (V) Output Driver Low-Level Voltage VOL (V) 0 15 Tj = 125°C Tj = 25°C VPS = 50 V 10 Tj = –20°C Tj = 125°C 5 Tj = 25°C VPS = 50 V Tj = –20°C 0 0 10 20 30 Output Current IO (mA) 27 HA13609ANT PWM Frequency vs. Junction Temperature R1 Voltage vs. Junction Temperature 1.4 C106 = 1000 pF R1 = 6.2 kΩ fPWM × 1 9.0 R1 = 6.2 kΩ R1 Voltage VR1 (V) PWM Frequency fPWM (kHz) 10.0 8.0 7.0 –20 10 40 70 100 125 –20 40 70 100 Junction Temperature Tj (°C) Error Amplifier Rif vs. Junction Temperature Integrator vs. Junction Temperature 125 2.4 Integrator Reference Voltage VP (V) Error Amplifier Rif (kΩ) 10 Junction Temperature Tj (°C) 60 50 40 30 10 40 70 100 Junction Temperature Tj (°C) 28 1.2 1.1 70 –20 1.3 125 2.3 2.2 2.1 2.0 –20 10 40 70 100 Junction Temperature Tj (°C) 125 HA13609ANT Monitor Output vs. Output Current Lock Protector vs. Junction Temperature 300 0.3 5° = Tj 12 C 0.2 Tj = 0.1 Tj = 25° C °C –20 Lock Protector tLP, tOFF (ms) Monitor Output VOL (V) 0.4 C105 = 0.47 µ 200 tOFF 100 tLP 0 0 2 4 6 8 0 –20 10 10 40 70 100 Output Current IO (mA) Junction Temperature Tj (°C) LVI Reference Voltage vs. Junction Temperature POR Delay Time vs. Junction Temperature 1.4 125 30 POR Delay Time tPOR (ms) LVI Reference Voltage VSD (V) C108 = 0.47 µ 1.3 1.2 1.1 –20 10 40 70 100 Junction Temperature Tj (°C) 125 25 20 15 –20 10 40 70 100 125 Junction Temperature Tj (°C) 29 HA13609ANT Package Dimensions Unit: mm 37.34 38.0 Max 22 1.0 21 1 0.89 1.78 ± 0.25 0.48 ± 0.10 0.51 Min 1.27 Max 2.54 Min 5.10 Max 13.4 14.6 Max 42 15.24 0.10 0.25 +– 0.05 1° – 13° Hitachi Code JEDEC Code EIAJ Code Weight 30 DP-42SA — SC-551-42 4.42 g Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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