HD74AC182/HD74ACT182 Carry Lookhead Generator Description The HD74AC182/HD74ACT182 is a high-speed carry lookahead generator. It is generally used with the HD74AC181 or HD74AC381 4-bit arithmetic logic unit to provide high-speed lookahead over word lengths of more than four bits. Features • Outputs Source/Sink 24 mA • HD74ACT182 has TTL-Compatible Inputs Pin Arrangement G1 1 16 VCC P1 2 15 P2 G0 3 14 G2 P0 4 13 Cn G3 5 12 Cn+X P3 6 11 Cn+y 10 G P 7 GND 8 9 Cn+z (Top view) HD74AC182/HD74ACT182 Logic Symbol P0 G0 P1 G1 P2 G2 P3 G3 G Cn P Cn+x Cn+y Pin Names Cn G0, G2 G1 G3 P 0, P 1 P2 P3 C n + x to Cn + z G P 2 Carry Input Carry Generate Inputs (Active Low) Carry Generate Input (Active Low) Carry Generate Input (Active Low) Carry Propagate Inputs (Active Low) Carry Propagate Input (Active Low) Carry Propagate Input (Active Low) Carry Outputs Carry Generate Output (Active Low) Carry Propagate Output (Active Low) Cn+z HD74AC182/HD74ACT182 Logic Diagram Cn G0 P0 Cn+x G1 P1 G2 P2 Cn+y G3 P3 Cn+z G P Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Functional Description The HD74AC182/HD74ACT182 carry lookahead generator accepts up to four pairs of Active Low Carry Propagate (P 0 to P 3) and Carry Generate (G 0 to G 3) signals and an Active High Carry input (Cn) and provides anticipated Active High carries (Cn + x, C n + y , Cn + z ) across four groups of binary adders. The HD74AC182/HD74ACT182 also has Active Low Carry Propagate ( P) and Carry Generate (G) outputs which may be used for further level of lookahead. The logic equations provided at the outputs are: C n + x = G0 + P0Cn C n + y = G1 + P1G0 + P1P0C n C n + z = G2 + P2G1 + P2P1G0 + P2P1P 0C n G = G3 + P3G2 + P3P2G1 + P3P2P 1G0 P = P3P 2P 1P 0 Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input operand mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are identical in both cases. Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by dropping the last HD74AC182/HD74ACT182. 3 HD74AC182/HD74ACT182 Truth Table Inputs Outputs Cn G0 P0 X H H L L H X L X L X H H X L H X X X H H L X H H H X L L H X H X L X X X L X H X L X X L H H X L X L H X X X X X H H L X X X H H H X L X H H H X H X L L H X H X H X L X X X X X L X H X X X L X X L H X L X X L X L H H X L X L X L H X X X X X H H H X X X H H H X H X H H H X H X H H H X H X H X H X X X X X L X L X X X L X X L L X L X X L X L L L X L X L X L L H : L : X : 4 G1 P1 G2 P2 G3 P3 Cn + x Cn + y Cn + z G P H X X X H X H X X H X X H X H X X X H H L L L L L High Voltage Level Low Voltage Level Immaterial HD74AC182/HD74ACT182 DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C Maximum ICC/input (HD74ACT182) I CCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V, Ta = Worst case AC Characteristics: HD74AC182 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Propagation delay t PLH 3.3 1.0 8.0 10.5 1.0 11.5 ns 5.0 1.0 5.5 8.0 1.0 9.0 3.3 1.0 8.0 10.5 1.0 11.5 5.0 1.0 5.5 8.0 1.0 9.0 3.3 1.0 9.5 12.0 1.0 13.0 5.0 1.0 7.5 10.0 1.0 11.0 3.3 1.0 9.0 12.0 1.0 13.0 5.0 1.0 7.0 10.0 1.0 11.0 3.3 1.0 10.5 13.0 1.0 14.0 5.0 1.0 8.0 10.5 1.0 11.5 3.3 1.0 11.5 14.0 1.0 15.5 5.0 1.0 9.0 11.5 1.0 12.5 Pn to P Propagation delay t PHL Pn to P Propagation delay t PLH Cn to Cn + x, y, z Propagation delay t PHL Cn to Cn + x, y, z Propagation delay t PLH Pn or Gn to Cn + x, y, z Propagation delay Pn or Gn to Cn + x, y, z Note: t PHL ns ns ns ns ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 5 HD74AC182/HD74ACT182 AC Characteristics: HD74ACT182 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Propagation delay Pn to P t PLH 5.0 1.0 7.0 9.0 1.0 10.0 ns Propagation delay Pn to P t PHL 5.0 1.0 8.0 10.0 1.0 11.0 ns Propagation delay Cn to Cn + x, y, z t PLH 5.0 1.0 9.0 11.0 1.0 12.0 ns Propagation delay Cn to Cn + x, y, z t PHL 5.0 1.0 9.0 11.0 1.0 12.0 ns Propagation delay Pn or Gn to Cn + x, y, z t PLH 5.0 1.0 9.0 11.0 1.0 12.0 ns Propagation delay Pn or Gn to Cn + x, y, z t PHL 5.0 1.0 10.0 12.5 1.0 13.5 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 50.0 pF VCC = 5.0 V 6 Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 0.13 M 1.10 Max 0.65 Max 0.10 *Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 *0.17 ± 0.05 0.15 ± 0.04 0.08 *0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-16DA — — 0.05 g Cautions 1. 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