ETC HD74AC283/HD74CT283

HD74AC283/HD74ACT283
4-bit Binary Full Adder with Fast Carry
ADE-205-388 (Z)
1st. Edition
Sep. 2000
Description
The HD74AC283/HD74ACT283 high-speed 4-bit binary full adder with internal carry lookahead accepts
two 4-bit binary works (A0 – A3, B0 – B 3) and a Carry input (C0). It generates the binary Sum outputs (S0 –
S 3) and the Carry output (C4) from the most significant bit. The HD74AC283/HD74ACT283 will operate
with either active High or active Low operands (positive or negative logic).
Features
• Outputs Source/Sink 24 mA
• HD74ACT283 has TTL-Cmpatible Inputs
Pin Arrangement
S1 1
16 VCC
B1 2
15 B2
A1 3
14 A2
S0 4
13 S2
A0 5
12 A3
B0 6
11 B3
C0 7
10 S3
GND 8
9 C4
(Top view)
HD74AC283/HD74ACT283
Logic Symbol
A0 B0 A1 B1 A2 B2 A3 B3
C0
C4
S0
S1
S2
S3
Pin Names
A0 – A3
B0 – B3
C0
S0 – S3
C4
A Operand Inputs
B Operand Inputs
Carry Input
Sum Outputs
Carry Output
Functional Description
The HD74AC283/HD74ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0).
The binary sum appears on the Sum (S0 – S3) and outgoing carry (C4) outputs. The binary weight of the
various inputs and outputs is indicated by the subscript numbers, representing powers of two.
20 (A0 + B0 + C0) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4
Where (+) = plus
Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily
assigned to pins 5, 6 and 7 for DIPS. Due to the symmetry of the binary add function, the
HD74AC283/HD74ACT283 can be used either with all inputs and outputs active High (positive logic) or
with all inputs and outputs active Low (negative logic). See Figure a. Note that if C0 is not used it must be
tied Low for active High logic or tied High for active Low logic.
Due to pin limitations, the intermediate carries of the HD74AC283/HD74ACT283 are not brought out for
use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a
carry out from, an intermediate stage. Figure b shows how to make a 3-bit adder. Tying the operand inputs
of the fourth adder (A 3, B3) Low makes S3 dependent only on, and equal to, the carry from the third adder.
Using somewhat the same principle Figure c shows a way of dividing the HD74AC283/HD74ACT283 into
a 2-bit and a 1-bit adder. The third stage adder (A2, B 2, S 2) is used merely as a means of getting a carry
(C10) signal into the fourth stage (via A 2 and B2) and bringing out the carry from the second stage on S2.
Note that as long as A 2 and B2 are the same, whether High or Low, they do not influence S2. Similarly,
when A 2 and B2 are the same the carry into the third stage does not influence the carry out of the third
2
HD74AC283/HD74ACT283
stage. Figure d shows a method of implementing a 5-input encoder, where the inputs are equally weighted.
The outputs S0, S 1 and S2 present a binary number equal to the number of inputs I1 – I5 that are true. Figure
e shows one method of implementing a 5-input majority gate. When three or more of the inputs I1 – I5 are
true, the output M5 is true.
Fig. a Active HIGH varsus Active LOW Interpretation
C0
A0
A1
A2
A3
B0
B1
B2
B3
S0
S1
S2
S3
C4
Logic levels
L
L
H
L
H
H
L
L
H
H
H
L
L
H
Active HIGH
0
0
1
0
1
1
0
0
1
1
1
0
0
1
Active LOW
1
1
0
1
0
0
1
1
0
0
0
1
1
0
Active HIGH: 0 + 10 + 9 = 3 + 16
Active LOW: 1 + 5 + 6 = 12 + 0
L
A0 B0 A1 B1 A2 B2 A3 B3
C0
C4
S0
S1
S2
S3
C3
Fig. b 3-bit Adder
C10
C0
A0 B0 A1 B1
A10 B10
A0 B0 A1 B1
A2 B2 A3 B3
C0
C4
S0
S1
S2
S3
S0
S1
C2
S10
C11
Fig. c 2-bit and 1-bit adders
3
HD74AC283/HD74ACT283
I3
I1
I2
L
I4
I5
A0 B0 A1 B1 A2 B2 A3 B3
C0
C4
S0
S1
S2
20
21
22
S3
Fig. d 5-Input Encoder
I3
I1
I2
I4
I5
A0 B0 A1 B1 A2 B2 A3 B3
C0
C4
S0
S1
S2
S3
M5
Fig. e 5-Input Majority Gate
4
HD74AC283/HD74ACT283
Logic Diagram
C0
A0
S0
B0
A1
B1
A2
S1
B2
A3
S2
B3
S3
C4
Please note that this diagram is provided only for the understanding of logic operations and shoudl not be
used to estimate propagation delays.
DC Characteristics (unless otherwise specified)
Item
Symbol
Max
Unit
Condition
Maximum quiescent supply current
I CC
80
µA
VIN = VCC or ground, VCC = 5.5 V,
Ta = Worst case
Maximum quiescent supply current
I CC
8.0
µA
VIN = VCC or ground, VCC = 5.5 V,
Ta = 25°C
Maximum ICC/input (HD74ACT283)
I CCT
1.5
mA
VIN = VCC – 2.1 V, VCC = 5.5 V,
Ta = Worst case
5
HD74AC283/HD74ACT283
AC Characteristics: HD74AC283
Ta = +25°C
CL = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Item
Symbol
VCC (V)*1
Min
Typ
Max
Min
Max
Unit
Propagation delay
t PLH
3.3
1.0
11.5
15.0
1.0
16.5
ns
5.0
1.0
9.5
11.5
1.0
12.5
3.3
1.0
10.5
14.0
1.0
15.5
5.0
1.0
8.5
10.5
1.0
11.5
3.3
1.0
14.0
17.0
1.0
18.5
5.0
1.0
11.5
13.5
1.0
14.5
3.3
1.0
13.5
16.5
1.0
18.0
5.0
1.0
11.0
13.0
1.0
14.0
3.3
1.0
9.5
12.5
1.0
15.5
5.0
1.0
7.5
9.5
1.0
10.5
3.3
1.0
10.0
13.0
1.0
14.0
5.0
1.0
8.0
10.0
1.0
11.0
3.3
1.0
11.5
14.5
1.0
16.0
5.0
1.0
9.5
11.5
1.0
12.5
3.3
1.0
12.0
15.0
1.0
16.5
5.0
1.0
10.0
12.0
1.0
13.0
C0 to S n
Propagation delay
t PHL
C0 to S n
Propagation delay
t PLH
An or Bn to S n
Propagation delay
t PHL
An or Bn to S n
Propagation delay
t PLH
C0 to C4
Propagation delay
t PHL
C0 to C4
Propagation delay
t PLH
An or Bn to C4
Propagation delay
An or Bn to C4
Note:
6
t PHL
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
ns
ns
ns
ns
ns
ns
ns
HD74AC283/HD74ACT283
AC Characteristics: HD74ACT283
Ta = +25°C
CL = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Item
Symbol
VCC (V)*1
Min
Typ
Max
Min
Max
Unit
Propagation delay
C0 to S n
t PLH
5.0
1.0
11.5
13.5
1.0
14.5
ns
Propagation delay
C0 to S n
t PHL
5.0
1.0
10.0
12.0
1.0
13.0
ns
Propagation delay
An or Bn to S n
t PLH
5.0
1.0
13.0
15.0
1.0
16.5
ns
Propagation delay
An or Bn to S n
t PHL
5.0
1.0
12.0
14.0
1.0
15.5
ns
Propagation delay
C0 to C4
t PLH
5.0
1.0
9.0
11.0
1.0
12.0
ns
Propagation delay
C0 to C4
t PHL
5.0
1.0
10.0
12.0
1.0
13.0
ns
Propagation delay
An or Bn to C4
t PLH
5.0
1.0
11.0
13.0
1.0
14.0
ns
Propagation delay
An or Bn to C4
t PHL
5.0
1.0
11.5
13.5
1.0
14.5
ns
Note:
1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Symbol
Typ
Unit
Condition
Input capacitance
CIN
4.5
pF
VCC = 5.5 V
Power dissipation capacitance
CPD
60.0
pF
VCC = 5.0 V
7
HD74AC283/HD74ACT283
Package Dimensions
Unit: mm
19.20
20.00 Max
6.30
9
1
7.40 Max
16
8
1.3
0.48 ± 0.10
7.62
2.54 Min 5.06 Max
2.54 ± 0.25
0.51 Min
1.11 Max
+ 0.13
0.25 – 0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
DP-16
Conforms
Conforms
1.07 g
Unit: mm
10.06
10.5 Max
9
1
8
1.27
*0.42 ± 0.08
0.40 ± 0.06
0.10 ± 0.10
0.80 Max
*0.22 ± 0.05
0.20 ± 0.04
2.20 Max
5.5
16
0.20
7.80 +– 0.30
1.15
0° – 8°
0.70 ± 0.20
0.15
0.12 M
*Dimension including the plating thickness
Base material dimension
8
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
FP-16DA
—
Conforms
0.24 g
HD74AC283/HD74ACT283
Unit: mm
9.9
10.3 Max
9
1
8
*0.42 ± 0.08
0.40 ± 0.06
*0.22 ± 0.03
0.20 ± 0.03
0.635 Max
+ 0.11
1.27
0.14 – 0.04
1.75 Max
3.95
16
+ 0.10
6.10 – 0.30
1.08
0° – 8°
0.67
0.60 +– 0.20
0.15
0.25 M
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
*Dimension including the plating thickness
Base material dimension
FP-16DN
Conforms
Conforms
0.15 g
Unit: mm
4.40
5.00
5.30 Max
16
9
1
8
0.65
1.10 Max
0.65 Max
0.10
*Dimension including the plating thickness
Base material dimension
6.40 ± 0.20
0.07 +0.03
–0.04
0.20 ± 0.06
1.0
0.13 M
*0.17 ± 0.05
0.15 ± 0.04
0.08
*0.22 +– 0.07
0° – 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-16DA
—
—
0.05 g
9
HD74AC283/HD74ACT283
Cautions
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copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
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products.
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Colophon 2.0
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