HD74AC194 4-bit Bidirectional Unviersal Shift Register Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load, shift right (in the direction Q 0 toward Q3); shift left; inhibit clock (do nothing). Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S 0 and S 1, high. The data are loaded into their respective flip-flops and appear at the output after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial date for this mode is entered at the shift right data input. When S 0 is low and S1 is high, data shifts left synchronously and new data is entered at the shifts left serial input. Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be changed only when the clock input is high. Features • Asynchronous Master Reset • Hole (Do Nothing) Mode • Outputs Source/Sink 24 mA HD74AC194 Pin Arrangement MR 1 16 VCC DSR 2 15 Q0 P0 3 14 Q1 P1 4 13 Q2 P2 5 12 Q3 P3 6 11 CP DSL 7 10 S1 GND 8 9 S0 (Top view) Logic Symbol DSR P0 P1 P2 P3 DSL S0 S1 CP MR Q0 Q1 Q2 Pin Names S 0, S 1 P 0 to P3 DSR DSL CP MR Q0 to Q3 2 Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs Q3 HD74AC194 Logic Diagram DSL P3 P2 P1 P0 DSR S0 S1 D D D D C C C C C Q CL CL C Q CL CL C Q CL CL C Q CL CL CP MR Q3 Q2 Q1 Q0 Mode Select Table Inputs Output Operating Mode MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Reset L X X X X X L L L L Hold H L L X X X q0 q1 q2 q3 Shift Left H H L X L X q1 q2 q3 L H H L X H X q1 q2 q3 H H L H L X X L q0 q1 q2 H L H H X X H q0 q1 q2 H H H X X pn p0 p1 p2 p3 Shift Right Parallel Load H : HIGH Voltage Level L : LOW Voltage Level pn (qn) : Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition X : Immaterial 3 HD74AC194 Timing Diagram CP Mode S0 Control Inputs S1 MR Parallel Data Inputs Parallel DSH DSL P0 H P1 L P2 H Data Inputs L P3 Q0 Outputs Q1 Q2 Q3 Shift Right Clear Shift Left Inhibit Load Clear DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C 4 HD74AC194 AC Characteristics: HD74AC194 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Maximum clock f max 3.3 7.5 — 65 5.0 100 — 85 3.3 1.0 — 13.0 1.0 15.0 5.0 1.0 — 10.0 1.0 11.5 3.3 1.0 — 13.0 1.0 15.0 5.0 1.0 — 10.0 1.0 11.5 3.3 1.0 — 10.5 1.0 12.5 5.0 1.0 — 8.0 1.0 9.0 frequency Propagation delay t PLH CP to Qn Propagation delay t PHL CP to Qn Propagation delay t PHL MR to Q n Note: Max Min Max Unit MHz ns ns ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74AC194 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time, HIGH or LOW t su 3.3 — 5.5 7.0 ns 5.0 — 4.0 5.0 3.3 — 2.0 3.0 5.0 — 1.5 2.0 3.3 — 6.0 7.5 5.0 — 4.5 5.5 3.3 — 0.0 0.0 5.0 — 0.0 0.0 3.3 — 0.5 0.5 5.0 — 0.5 0.5 3.3 — 5.5 7.0 5.0 — 4.5 5.0 Pn or D SR or DSL to CP Hold time, HIGH or LOW th Pn or D SR or DSL to CP Setup time, HIGH or LOW t su Sn to CP Hold time, HIGH or LOW th Sn to CP Recovery time t rec MR to CP Pulse width Note: tw ns ns ns ns ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 5 HD74AC194 Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 100 pF VCC = 5.0 V 6 Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 0.13 M 1.10 Max 0.65 Max 0.10 *Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 *0.17 ± 0.05 0.15 ± 0.04 0.08 *0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-16DA — — 0.05 g Cautions 1. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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