HD74AC374/HD74ACT374 Octal D-Type Flip-Flops with 3-State Output Description The HD74AC374/HD74ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate Dtype inputs for each flip-flop and 3-state outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. Features • • • • • • • • • Buffered Positive Edge-Triggered Clock 3-State Outputs for Bus-Oriented Applications Outputs Source/Sink 24 mA See HD74AC273/HD74ACT273 for Reset Version See HD74AC373/HD74ACT373 for Transparent Latch Version See HD74AC574/HD74ACT574 for Broadside Pinout Version See HD74AC564/HD74ACT564 for Broadside Pinout Version with Inverted Outputs HD74ACT374 has TTL-Compatible Inputs HD74AC374/HD74ACT374 Pin Arrangement OE 1 20 VCC O0 2 19 O7 D0 3 18 D7 D1 4 17 D6 O1 5 16 O6 O2 6 15 O5 D2 7 14 D5 D3 8 13 D4 O3 9 12 O4 Gnd 10 11 CP (Top view) Logic Symbol D0 D1 D2 D3 D4 D5 D6 D7 CP OE O0 O1 O2 O3 O4 O5 O6 O7 Pin Names D0 – D7 CP OE O0 – O7 2 Data Inputs Clock Pulse Input 3-State Output Enable Input 3-State Outputs HD74AC374/HD74ACT374 Functional Description The HD74AC374/HD74ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the Low-to-High Clock (CP) transition. With the Output Enable (OE) Low, the contents of the eight flip-flops are available at the outputs. When the OE is High, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Truth Table Inputs Outputs OE On H L H L L L H Z CP Dn X H L X Z X : : : : High Voltage Level Low Voltage Level Immaterial High Impedance : Low-to-High Transition Logic Diagram D0 D1 D2 D3 D4 D5 D6 D7 CP D CP D CP D CP D CP D CP D CP D CP D CP Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 HD74AC374/HD74ACT374 DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C Maximum ICC/input (HD74ACT374) I CCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V, Ta = Worst case AC Characteristics: HD74AC374 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum clock f max 3.3 60 110 — 60 — MHz 5.0 100 155 — 100 — 3.3 1.0 11.0 13.5 1.0 15.5 5.0 1.0 8.0 9.5 1.0 10.5 3.3 1.0 10.0 12.5 1.0 14.0 5.0 1.0 7.0 9.0 1.0 10.0 3.3 1.0 9.5 11.5 1.0 13.0 5.0 1.0 7.0 8.5 1.0 9.5 3.3 1.0 9.0 11.5 1.0 13.0 5.0 1.0 6.5 8.5 1.0 9.5 3.3 1.0 10.5 12.5 1.0 14.5 5.0 1.0 8.0 11.0 1.0 12.5 3.3 1.0 8.0 11.5 1.0 12.5 5.0 1.0 6.5 8.5 1.0 10.0 frequency Propagation delay t PLH CP to On Propagation delay t PHL CP to On Output enable time Output enable time Output disable time Output disable time Note: 4 t PZH t PZL t PHZ t PLZ 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V ns ns ns ns ns ns HD74AC374/HD74ACT374 AC Operating Requirements: HD74AC374 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time, HIGH or LOW t su 3.3 2.0 5.5 6.0 ns 5.0 1.0 4.0 4.5 3.3 –1.0 1.0 1.0 Dn to CP 5.0 –4.0 1.5 1.5 CP pulse width, HIGH or LOW t w 3.3 4.0 5.5 6.0 5.0 2.5 4.0 4.5 Dn to CP Hold time, HIGH or LOW Note: th ns ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Characteristics: HD74ACT374 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum clock frequency f max 5.0 100 160 — 90 — MHz Propagation delay CP to On t PLH 5.0 1.0 8.5 10.0 1.0 11.5 ns Propagation delay CP to On t PHL 5.0 1.0 8.0 9.5 1.0 11.0 ns Output enable time t PZH 5.0 1.0 8.0 9.5 1.0 10.5 ns Output enable time t PZL 5.0 1.0 8.0 9.0 1.0 10.5 ns Output disable time t PHZ 5.0 1.0 8.5 11.5 1.0 12.5 ns Output disable time t PLZ 5.0 1.0 7.0 8.5 1.0 10.0 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V 5 HD74AC374/HD74ACT374 AC Operating Requirements: HD74ACT374 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time, HIGH or LOW Dn to CP t su 5.0 1.0 7.0 5.5 ns Hold time, HIGH or LOW Dn to CP th 5.0 0.0 1.5 1.5 ns CP pulse width, HIGH or LOW t w 5.0 2.0 7.0 5.0 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 80.0 pF VCC = 5.0 V 6 Unit: mm 24.50 25.40 Max 6.30 11 1 7.00 Max 20 10 1.30 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 1.27 Max 2.54 Min 5.08 Max 0.89 7.62 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-20N — Conforms 1.26 g Unit: mm 12.6 13 Max 11 1 10 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 20 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DA — Conforms 0.31 g Unit: mm 12.8 13.2 Max 11 1 10 0.20 ± 0.10 0.935 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 *0.27 ± 0.05 0.25 ± 0.04 2.65 Max 7.50 20 0.25 10.40 +– 0.40 1.45 0° – 8° 0.57 0.70 +– 0.30 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DB Conforms — 0.52 g Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.22+0.08 –0.07 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 *Dimension including the plating thickness Base material dimension 0.07 +0.03 –0.04 0.10 *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.65 Max 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-20DA — — 0.07 g Cautions 1. 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