Preliminary
M61540FP
6ch Electronic Volume with 5 Input Selector
REJ03F0117-0100Z
Rev.1.0
May.31.2004
Description
M61540FP is an audio signal processor for home audio. This IC contains 6 channel electronic volume, gain control,
input selector and 2 band tone control.
Features
• Electric Volume
•
•
•
•
6 channel independent Electronic Volume with High Voltage Transistor.
(0 to –99dB/1dBstep, –∞dB)
6 channel independent Gain Control (0, 6, 12, 18dB)
L/R channel 5 Input Selector
6 channel Input
Bass: –14 to + 14dB(2dB step),
Treble: –14 to + 14dB(2dB step)
Can use 2 Input for REC Output
Built-in ADC out
Gain Control
Input Selector
Multi Channel Input
Tone Control
• REC Output
• ADC Out
Recommended Operating Condition
Supply Voltage Range
AVCC = 7.0V(typ), AVEE = –7.0V(typ), DVDD = 3.0 to 5.5V
System Block Diagram
Multi
Rin
REC OUT
(4) (5)
Multi
Lin
Lch Tone RchTone CLOCK DATA
MCU I/F
I nput sel ector
1
Lch 2
3
Tone
Volume
Volume
1
Rch 2
3
I nput sel ector
Input
ATT
Multi
Out L Cin
for
ADC Multi
SWin
Input
ATT Out R Multi
for SLin
ADC Multi
Bass&
Treble
Gain Control
Bass&
Treble
Gain Control
Volume
Gain Control
Volume
Gain Control
Volume
Gain Control
SRin
GND
(4) (5)
REC OUT
Rev.1.0, May.31.2004, page 1 of 16
VOL GND
Rout
Gain Control
Volume
DGND
Lout
DVDD AVEE AVCC
Cout
SWout
SLout
SRout
M61540FP
Preliminary
BA SR1
BA SR2
L OUT
ROUT
DGND
CL OCK
DA TA
DV DD
COUT
SWOUT
Block Diagram and Pin Configuration
20
19
18
17
16
15
14
13
12
11
MCU I/F
Gain
Control
Gain
Control
DVDD
10 SLOUT
BASL2 21
-+
+ -
9 SROUT
BASL1 22
Gain
Control
Bass
/Tre
TRER 23
Bass
/Tre
Gain
Control
Gain
Control
8 AGND
-+
TREL 24
Gain
Control
-+
-+
-+
7 SRIN
25K
25K
25K
25K
Cch Vol SWch Vol SLch Vol SRch Vol
50K
Rch Vol
AGND 25
6 SLIN
50K
Lch Vol
INR1 26
INL1 27
INR2 28
INL2 29
Logic
5 SWIN
50K
4 CIN
50K
Input ATT
+
-
50K
+
-
50K
3 RIN
50K
2 LIN
Input ATT
+
-
+
-
50K
INR3 30
1 AGND
50K
37
38
39
40
A DCL
50K
A DCR
50K
AVCC
A V CC
50K
50K
AVEE
A V EE
50K
A GND
33
34
35
36
I NL 4
(RECL 1)
I NR4
(RECR1)
I NL 5
(RECL 2)
I NR5
(RECR2)
32
I NL 3
Rch
31
(Top View)
Rev.1.0, May.31.2004, page 2 of 16
Lch
M61540FP
Preliminary
Pin Description
Pin No.
Name
1, 8, 25, 32
AGND
Analog Ground
2
3
LIN
RIN
Input pin of L channel (Multi)
Input pin of R channel (Multi)
4
5
CIN
SWIN
Input pin of C channel (Multi)
Input pin of SW channel (Multi)
6
7
SLIN
SRIN
Input pin of SL channel (Multi)
Input pin of SR channel (Multi)
9
10
SROUT
SLOUT
Output pin of SR channel
Output pin of SL channel
11
12
SWOUT
COUT
Output pin of SW channel
Output pin of C channel
13
14
DVDD
DATA
Power supply to internal logic circuit
Input pin of control data
15
16
CLOCK
DGND
Input pin of control clock
Ground of internal logic circuit
17
18
ROUT
LOUT
Output pin of R channel
Output pin of L channel
19, 20
21, 22
BASR1, BASR2
BASL1, BASL2
Frequency characteristic setting pin of R channel tone control (BASS)
Frequency characteristic setting pin of L channel tone control (BASS)
23
24
TRER
TREL
Frequency characteristic setting pin of R channel tone control (Treble)
Frequency characteristic setting pin of L channel tone control (Treble)
26, 28, 30
27, 29, 31
INR1, 2, 3
INL1, 2, 3
Input pin of R channel (Input Selector)
Input pin of L channel (Input Selector)
33, 35
34, 36
INL4, 5/ RECL1, 2
INR4, 5/ RECR1, 2
Input pin of L channel (Input Selector) can use REC output pin
Input pin of R channel (Input Selector) can use REC output pin
37
38
AVEE
AVCC
Negative power supply to internal analog circuit
Positive power supply to internal analog circuit
39, 40
ADCR, ADCL
Output pin for ADC
Rev.1.0, May.31.2004, page 3 of 16
Function
M61540FP
Preliminary
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Unit
Condition
Power Supply
Supply Voltage
16
V
AVCC-AVEE
Power dissipation
Pd
6
1.46
W
DVDD-DGND
Ta≤25°C
Thermal derating
Operating temperature
K
Topr
85.3
–20 to +75
mW/°C
°C
Storage temperature
Tstg
–40 to +125
°C
Ta>25°C
Note: AVEE≤DGND<DVDD≤AVCC
THERMAL DERATINGS (MAXIMUM RATING)
POWER DI SSI PA TI ON pd (W)
2.0
1.46W
1.5
1.0
0.88
0.5
0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE Ta ( °C )
Recommended Operating Conditions
(Ta=25°C, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
Analog Supply Voltage (Positive)
AVCC
4.5
7.0
7.5
V
Analog Supply Voltage (Negative)
AVEE
−7.5
−7.0
−4.5
V
Digital Supply Voltage
Logic “H” level Input Voltage
DVDD
VIH
3.0
DVDD×0.7
3.3
5.5
DVDD
V
V
DGND reference
Logic “L” level Input Voltage
VIL
DGND
DVDD×0.2
V
DGND reference
Note: AVEE≤DGND<DVDD≤AVCC
Rev.1.0, May.31.2004, page 4 of 16
Condition
M61540FP
Preliminary
Relationship Between Data and Clock
Make "H" at the timing which
DATA of D0-D23 make latch.
Data signal is read at the rising edge of CLOCK.
DATA
D0
D2
D1
D21
D3
D23
D22
CLOCK
When DATA is "H", latch signal is
created at the falling edge of CLOCK.
Clock and Data Timings
(D0 to D23)
LATCH
t cr
DATA
75%
25%
tSLD
tSLD
tHLD tSHD tHHD
tHLD
tSC
75%
50%
25%
CLOCK
tf
tr
tWHC
tWLC
Timing Definition of Digital Block
Limits
Parameter
Symbol
Min
Typ
Max
CLOCK cycle time
tcr
8
CLOCK pulse width ("H" level)
CLOCK pulse width ("L" level)
tWHC
tWLC
3.2
3.2
Rising time of clock and data
Falling time of clock and data
tr
tf
0.8
0.8
DATA setup time (Rising time of clock)
DATA setup time (Falling time of clock)
tSHD
tSLD
1.6
1.6
DATA hold time ("H" level)
DATA hold time ("L" level)
tHHD
tHLD
1.6
1.6
CLOCK setup time
tSC
1.6
Rev.1.0, May.31.2004, page 5 of 16
Unit
µs
M61540FP
Preliminary
Power on Reset
This IC built-in the power on reset function.
The voltage of DVDD (13 pin) -DGND (16 pin) less than 2.6V, the serial DATA can not accept.
DVDD(3pin) - DGND(6pin)
(V)
2.6V
(S)
Reset time
After reset is canceled, the serial DATA can accept.
Release of reset.
Note:
AVEE≤DGND<DVDD≤AVCC
Data Control Specification
Initialize all data of the 4 formats when Digital Power supply (DVDD) turns on.
Prohibit using except specified Data code as follows.
Slot1
D0a
D1a D2a
(1) Input Selector
D3a
D4a D5a
(2)
REC
Output
D6a
(3)
ADC
Input
ATT
D7a D8a
(4)
L/R
Vol
Input
D9a D10a D11a D12a D13a D14a D15a D16a D17a D18a D19a D20a D21a D22
(5) Bass/
Tone control Bypass
(6) Treble
0
0
0
0
0
0
0
D23
0
Slot2
D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14b D15b D16b D17b D18b D19b D20b D21b D22 D23
(7)
Lch Gain
Control
(7)
Rch Gain
Control
(8) Lch Volume
(8) Rch Volume
0
0
0
0
0
1
Slot3
D0c
D1c D2c
(7)
Cch Gain
Control
D3c D4c
D5c
D6c D7c
(8) Cch Volume
D8c
D9c D10c D11c D12c D13c D14c D15c D16c D17c D18c D19c D20c D21c D22
(7)
SWch Gain
Control
(8) SWch Volume
0
0
0
0
1
D23
0
Slot4
D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10d D11d D12d D13d D14d D15d D16d D17d D18d D19d D20d D21d D22 D23
(7)
SLch Gain
Control
Note:
(8) SLch Volume
(7)
SRch Gain
Control
No guarantee except for these codes.
Rev.1.0, May.31.2004, page 6 of 16
(8) SRch Volume
0
0
0
0
1
1
M61540FP
Preliminary
Setting Code
It’s initial setting when power is turned on.
(1) Input Selector
Setting
D0a
D1a
D2a
ALL OFF
IN1
0
0
0
1
0
0
IN2
IN3
1
1
0
1
0
0
IN4*
IN5*
0
0
0
1
1
1
Note: *No guarantee except for these codes.
(2) REC Output
REC Output
REC1
REC2
Setting
D3a
D4a
OFF
ON
0
1*1
0
1*2
*1: When IN4 selected, REC1 can not use.
IN4
REC1
D0a
D1a
D2a
D3a
ON
1
OFF
0
0
1
*2: When IN5 selected, REC2 can not use.
IN5
REC2
D0a
D1a
D2a
D4a
ON
1
OFF
0
1
(3) ADC Input ATT
ATT Setting
D5a
D6a
0dB
–6dB
0
0
0
1
–12dB
–18dB
1
1
0
1
(4) L/R Volume Input
Setting
D7a
Selector In
Multi In
0
1
Rev.1.0, May.31.2004, page 7 of 16
1
M61540FP
Preliminary
It’s initial setting when power is turned on.
(6) Treble
(5) Bass/Bypass
ATT Setting
D8a
D9a
D10a
D11a
+14dB
+12dB
1
1
1
1
1
1
1
0
+10dB
+8dB
1
1
1
1
0
0
+6dB
+4dB
1
1
0
0
+2dB
0dB
1
1
−2dB
−4dB
D12a
D13a
D14a
D15a
+14dB
+12dB
1
1
1
1
1
1
1
0
1
0
+10dB
+8dB
1
1
1
1
0
0
1
0
1
1
1
0
+6dB
+4dB
1
1
0
0
1
1
1
0
0
0
0
0
1
0
+2dB
1
0
0
1
0dB
1/0
0
0
0
0
0
0
0
0
1
1
0
−2dB
0
0
0
1
−6dB
−8dB
0
0
0
1
1
0
1
0
−4dB
−6dB
0
0
0
0
1
1
0
1
−10dB
−12dB
0
0
1
1
0
1
1
0
−8dB
−10dB
0
0
1
1
0
0
0
1
−14dB
0
1
1
1
−12dB
−14dB
0
0
1
1
1
1
0
1
Bypass*3
0
0
0
0
*3: Tone control is bypass.
(7) Gain Control
Lch
Rch
D0b
D9b
D1b
D10b
Cch
SWch
D0c
D9c
D1c
D10c
SLch
SRch
D0d
D9d
D1d
D10d
0dB
6dB
0
0
0
1
12dB
18dB
1
1
0
1
ATT
Setting
Rev.1.0, May.31.2004, page 8 of 16
ATT Setting
M61540FP
Preliminary
(8) 6ch Volume
It’s initial setting when power is turned on.
ATT
Lch
Rch
D2b
D11b
D3b
D12b
D4b
D13b
D5b
D14b
D6b
D15b
D7b
D16b
D8b
D17b
Cch
SWch
D2c
D11c
D3c
D12c
D4c
D13c
D5c
D14c
D6c
D15c
D7c
D16c
D8c
D17c
SLch
SRch
D2d
D11d
D3d
D12d
D4d
D13d
D5d
D14d
D6d
D15d
D7d
D16d
D8d
D17d
0dB
0
0
0
0
0
0
0
–1dB
–2dB
0
0
0
0
0
0
0
0
0
0
0
1
1
0
–3dB
–4dB
0
0
0
0
0
0
0
0
0
1
1
0
1
0
–5dB
–6dB
0
0
0
0
0
0
0
0
1
1
0
1
1
0
–7dB
–8dB
0
0
0
0
0
0
0
1
1
0
1
0
1
0
–9dB
–10dB
0
0
0
0
0
0
1
1
0
0
0
1
1
0
–11dB
–12dB
0
0
0
0
0
0
1
1
0
1
1
0
1
0
–13dB
–14dB
0
0
0
0
0
0
1
1
1
1
0
1
1
0
–15dB
–16dB
0
0
0
0
0
1
1
0
1
0
1
0
1
0
–17dB
–18dB
0
0
0
0
1
1
0
0
0
0
0
1
1
0
–19dB
–20dB
0
0
0
0
1
1
0
0
0
1
1
0
1
0
–21dB
–22dB
0
0
0
0
1
1
0
0
1
1
0
1
1
0
–23dB
–24dB
0
0
0
0
1
1
0
1
1
0
1
0
1
0
–25dB
–26dB
0
0
0
0
1
1
1
1
0
0
0
1
1
0
–27dB
–28dB
0
0
0
0
1
1
1
1
0
1
1
0
1
0
–29dB
–30dB
0
0
0
0
1
1
1
1
1
1
0
1
1
0
–31dB
–32dB
0
0
0
1
1
0
1
0
1
0
1
0
1
0
–33dB
–34dB
0
0
1
1
0
0
0
0
0
0
0
1
1
0
–35dB
–36dB
0
0
1
1
0
0
0
0
0
1
1
0
1
0
–37dB
–38dB
0
0
1
1
0
0
0
0
1
1
0
1
1
0
–39dB
–40dB
0
0
1
1
0
0
0
1
1
0
1
0
1
0
Rev.1.0, May.31.2004, page 9 of 16
M61540FP
Preliminary
Lch
Rch
D2b
D11b
D3b
D12b
D4b
D13b
D5b
D14b
D6b
D15b
D7b
D16b
D8b
D17b
Cch
SWch
D2c
D11c
D3c
D12c
D4c
D13c
D5c
D14c
D6c
D15c
D7c
D16c
D8c
D17c
SLch
SRch
D2d
D11d
D3d
D12d
D4d
D13d
D5d
D14d
D6d
D15d
D7d
D16d
D8d
D17d
–41dB
–42dB
0
0
1
1
0
0
1
1
0
0
0
1
1
0
–43dB
–44dB
0
0
1
1
0
0
1
1
0
1
1
0
1
0
–45dB
–46dB
0
0
1
1
0
0
1
1
1
1
0
1
1
0
–47dB
–48dB
0
0
1
1
0
1
1
0
1
0
1
0
1
0
–49dB
–50dB
0
0
1
1
1
1
0
0
0
0
0
1
1
0
–51dB
–52dB
0
0
1
1
1
1
0
0
0
1
1
0
1
0
–53dB
–54dB
0
0
1
1
1
1
0
0
1
1
0
1
1
0
–55dB
–56dB
0
0
1
1
1
1
0
1
1
0
1
0
1
0
–57dB
–58dB
0
0
1
1
1
1
1
1
0
0
0
1
1
0
–59dB
–60dB
0
0
1
1
1
1
1
1
0
1
1
0
1
0
–61dB
–62dB
0
0
1
1
1
1
1
1
1
1
0
1
1
0
–63dB
–64dB
0
1
1
0
1
0
1
0
1
0
1
0
1
0
–65dB
–66dB
1
1
0
0
0
0
0
0
0
0
0
1
1
0
–67dB
–68dB
1
1
0
0
0
0
0
0
0
1
1
0
1
0
–69dB
–70dB
1
1
0
0
0
0
0
0
1
1
0
1
1
0
–71dB
–72dB
1
1
0
0
0
0
0
1
1
0
1
0
1
0
–73dB
–74dB
1
1
0
0
0
0
1
1
0
0
0
1
1
0
–75dB
–76dB
1
1
0
0
0
0
1
1
0
1
1
0
1
0
–77dB
–78dB
1
1
0
0
0
0
1
1
1
1
0
1
1
0
–79dB
–80dB
1
1
0
0
0
1
1
0
1
0
1
0
1
0
–81dB
–82dB
1
1
0
0
1
1
0
0
0
0
0
1
1
0
–83dB
–84dB
1
1
0
0
1
1
0
0
0
1
1
0
1
0
ATT
Rev.1.0, May.31.2004, page 10 of 16
M61540FP
Preliminary
Lch
Rch
D2b
D11b
D3b
D12b
D4b
D13b
D5b
D14b
D6b
D15b
D7b
D16b
D8b
D17b
Cch
SWch
D2c
D11c
D3c
D12c
D4c
D13c
D5c
D14c
D6c
D15c
D7c
D16c
D8c
D17c
SLch
SRch
D2d
D11d
D3d
D12d
D4d
D13d
D5d
D14d
D6d
D15d
D7d
D16d
D8d
D17d
–85dB
–86dB
1
1
0
0
1
1
0
0
1
1
0
1
1
0
–87dB
–88dB
1
1
0
0
1
1
0
1
1
0
1
0
1
0
–89dB
–90dB
1
1
0
0
1
1
1
1
0
0
0
1
1
0
–91dB
–92dB
1
1
0
0
1
1
1
1
0
1
1
0
1
0
–93dB
–94dB
1
1
0
0
1
1
1
1
1
1
0
1
1
0
–95dB
–96dB
1
1
0
1
1
0
1
0
1
0
1
0
1
0
–97dB
–98dB
1
1
1
1
0
0
0
0
0
0
0
1
1
0
–99dB
–∞dB
1
1
1
1
0
1/0
0
1/0
0
1
1
1/0
1
1/0
ATT
Note: No guarantee except for these codes.
Electrical Characteristics
Unless otherwise noted, Ta = 25°C, AVCC = 7V, AVEE = –7V, DVDD = 5V, f = 1kHz, Volume = 0dB,
Input Selector = IN1, Gain Control = 0dB, ADC Input ATT = 0dB, Tone = Bypass
(1) Power supply characteristics
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Test condition
Analog positive power circuit current
AIcc
32
42
mA
With AVCC = 7V and AVEE = –7V
38pin current, when no signal is provided
Analog negative power circuit current
AIee
–42
–32
mA
With AVCC = 7V and AVEE = –7V
37pin current, when no signal is provided
Digital power circuit current
DIdd
2
3
mA
With DVDD = 3.3V,
13pin current, when no signal is provided
Rev.1.0, May.31.2004, page 11 of 16
M61540FP
Preliminary
(2) Input/Output characteristics (OVER ALL)
Limits
Parameter
Symbol Min
Typ
Max
Unit
Input resistance
Maximum
output voltage
Rin
VOM
17
3.8
25
4.4
33
—
Ω
2 to 7, 26, 27 pin
Vrms 2 to 7pin input, 9 to 12,17,18pin output,
THD = 1%, RL = 10kΩ, Output Gain Control = +6dB
Pass gain
Gv
–2.0
0
2.0
dB
Total harmonic
distortion
THD1
—
0.002 0.008 %
THD2
0.01
0.1
Balance of
CBAL
mutual channels
–0.5
0
0.5
dB
Output noise
voltage
1
5
3
15
µVrms JIS-A, Rg = 0Ω, 17,18pin output,
Vono2
1.5
7.2
Vono3
SS1
Selector
separation
Channel
separation
Vono1
Test condition
2 to 7,26,27 pin input, 9 to 12,17,18pin output,
Vi = 0.3Vrms, FLAT
2 to 7pin input, 9 to12, 17,18 pin output,
BW: 400Hz to 30kHz, f = 1kHz, Vo = 0.3Vrms, RL=10kΩ
2 to 7pin input, 9 to 12, 17,18pin output,
BW: 400Hz to 30kHz, f = 1kHz, Vo = 2Vrms, RL = 10kΩ
26,27pin input, 17,18pin output, Vi = 0.3Vrms
Volume = –∞dB setting
Output Gain Control = 0dB
Output Gain Control = +12dB
4.5
22
JIS-A, Rg = 0Ω, 17,18pin output,
Volume = 0dB setting
Output Gain Control = 0dB
Output Gain Control = +12dB
1
5
3
15
JIS-A, Rg = 0Ω, 9 to 12pin output, Output Gain Control = 0dB
Volume = 0dB setting
Output Gain Control = +12dB
—
–90
–70
SS2
—
–90
–70
< Multi Input Selector >
Vo = 1Vrms, Rg = 0Ω, RL = 10kΩ, JIS-A
CS
—
–90
–70
Vo = 1Vrms, Rg = 0Ω, RL = 10kΩ, JIS-A
< Input Selector>
Vo = 1Vrms, Rg = 0Ω, RL = 10kΩ, JIS-A
dB
(3) 6 channel Volume characteristics
Limits
Parameter
Symbol
Min
Typ
Maximum attenuation
ATTmax
—
–100 –95
Volume gain gang error
of mutual channels
Dvol
–0.5
0
Max
Unit
Test condition
dB
Vi = 2Vrms, JIS-A, VOL = –∞dB
+0.5 dB
Volume = 0dB
(4) Tone control characteristics
Unless otherwise noted, Tone ON/OFF = ON
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Test condition
Tone control voltage gain
(Boost/Bass)
Tone control voltage gain
(Cut/Bass)
G (BASS) B
+12
+14
+16
dB
G (BASS) C
–16
–14
–12
dB
f = 100Hz
Bass +14dB setting
f = 100Hz
Bass –14dB setting
Tone control voltage gain
(Boost/Treble)
Tone control voltage gain
(Cut/Treble)
G (TRE) B
+12
+14
+16
dB
G (TRE) C
–16
–14
–12
dB
Balance of mutual channels
BALT
–2
0
+2
dB
Rev.1.0, May.31.2004, page 12 of 16
f = 10kHz
Treble +14dB setting
f = 10kHz
Treble –10dB setting
Bass setting +14, –14dB
Treble setting +14, –14dB
M61540FP
Preliminary
Tone Control
(1) Bass
< Boost >
+
IN
R3
OUT
+
R2
1
f0 =
C1
0.047µ
2 π R1(R2+R3)C1C2
(Hz)
(R2+R3)R1C1C2
C2
0.15µ
Q=
R1
4.7K
R1(C1+C2)+R3C1
Gv = 20 log
R1(C1+C2)+(R2+R3)C1
R1(C1+C2)+R3C1
< Cut >
+
IN
+
R2
f0 =
1
2 π R1(R2+R3)C1C2
C2
0.15 µ
(Hz)
R1(C1+C2)+R3C1
Gv = 20 log
R1(C1+C2)+R3C1
R1(C1+C2)+(R2+R3)C1
Rev.1.0, May.31.2004, page 13 of 16
C1
0.047µ
R1
4.7K
(R2+R3)R1C1C2
Q=
R3
(dB)
OUT
(dB)
M61540FP
Preliminary
(2) Treble
< Boost >
-
+
IN
OUT
+
R5
Gv =20 log
R4
RC
(R4+R5)2+ RC2
2
(dB)
2
R4 +RC
0.022µ
<Cut >
+
IN
2
R5
-
+
OUT
Gv =20 log
0.022 µ
Tone gain Gv (dB)
Curve of characteristics
Frequency f(Hz)
Rev.1.0, May.31.2004, page 14 of 16
2
(R4+R5) + RC
R4
RC
2
R4 +RC
(dB)
2
M61540FP
Preliminary
Application Example
L
R
4.7µ
4.7µ
DVDD
5V
C
SW
4.7K
0.047µ
0.15µ
4.7µ
MCU
4.7µ
100µ 0.1 µ
20
19
18
17
0.15µ
15
14
MCU I/F
Gain
Control
Gain
Control
0.047µ
4.7K
16
13
12
11
DVDD
21
22
Gain
Control
Bass
/Tre
24
Bass
/Tre
Gain
Control
Gain
Control
Gain
Control
-+
-+
-+
7
25K
25K
25K
25K
Cch Vol SWch Vol SLch Vol SRch Vol
50K
Rch Vol
25
6
50K
Lch Vol
2.2 µ
Logic
5
50K
2.2 µ
27
4
50K
2.2 µ
INR2
28
Input ATT
+
-
50K
+
-
2.2µ
INL2
29
50K
Input ATT
+
-
+
-
50K
50K
3
2
2.2 µ
INR3
SR
8
-+
0.022 µ
INL1
4.7µ
9
23
26
SL
-+
+-
0.022µ
INR1
4.7 µ
10
1
30
50K
50K
50K
50K
50K
50K
AVEE
AVCC
37
38
Rch
Rev.1.0, May.31.2004, page 15 of 16
35
2.2 µ
2.2µ
36
39
Lch
40
2.2 µ
100µ 0.1µ100 µ 0.1µ
I NR5
(RECR2)
2.2µ
34
I NL 5
(RECL 2)
I NL 3
2.2µ
33
I NR4
(RECR1)
32
I NL 4
(RECL 1)
31
AVEE AVCC
7V
-7V
ADC
2.2µ
SRIN
2.2µ
2.2 µ
2.2µ
2.2µ
2.2 µ
SLIN
SWIN
CIN
RIN
LIN
M61540FP
Preliminary
Package Dimensions
As of January, 2003
20
40
11
0.13
0.575
0.10
*Dimension including the plating thickness
Base material dimension
Rev.1.0, May.31.2004, page 16 of 16
M
*0.17 ± 0.05
0.15 ± 0.04
10
1.40
1.70 Max
1
*0.25 ± 0.05
0.22 ± 0.04
0.09
0.13+– 0.05
9.0 ± 0.2
31
0.65
Unit: mm
9.0 ± 0.2
7.0
30
21
1.0
0.575
0° – 8°
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass(reference value)
FP-40B
—
Conforms
0.2 g
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0