Preliminary
M61541FP
6ch Electronic Volume with Tone Control
REJ03F0122-0100
Rev.1.0
Sep 09, 2004
Description
M61541FP is an audio signal processor for home audio.
This IC contains 6 channel electronic volume and 2 band tone control.
Features
• Electronic Volume
• Gain Control
• Tone Control
6 channel independent Electronic Volume with High Voltage Transistor.
(0 to –99dB/1dBstep, –∞dB)
6 channel independent Gain Control (0, 6, 12, 18dB)
Bass: –14 to + 14dB(2dB step),
Treble: –14 to + 14dB(2dB step)
Recommended Operating Condition
Supply Voltage Range
AVCC = 7.0V(typ), AVEE = –7.0V(typ), DVDD = 3.0 to 5.5V
Application
• Receiver, AV Amp, Mini Stereo etc.
System Block Diagram
Lch Tone RchTone
Lin
Rin
Volume
Volume
Cin
Volume
SWin
Volume
SLin
Volume
SRin
Rev.1.0 Sep 09, 2004 page 1 of 15
Tone
MCU I/F
Bass&
Treble
Gain Control
Bass&
Treble
Gain Control
Gain Control
Gain Control
Gain Control
Volume
VOL GND
CLOCK DATA
Gain Control
DGND
DVDD AVEE AVCC GND
Lout
Rout
Cout
SWout
SLout
SRout
M61541FP
Preliminary
BA SR1
BA SR2
L OUT
ROUT
DGND
CL OCK
DA TA
DV DD
COUT
SWOUT
Block Diagram and Pin Configuration
20
19
18
17
16
15
14
13
12
11
MCU I/F
Gain
Control
Gain
Control
DVDD
10 SLOUT
-
+
-
BASL2 21
+
9 SROUT
BASL1 22
Gain
Control
Bass
/Tre
TREL 24
Gain
Control
Gain
Control
+
-
+
-
+
-
8 AGND
-
TRER 23
Gain
Control
+
7 SRIN
Bass
/Tre
25k
25k
25k
25k
Cch Vol SWch Vol SLch Vol SRch Vol
25k
Rch Vol
AGND 25
6 SLIN
25k
Lch Vol
Logic
INR 26
5 SWIN
INL 27
4 CIN
N.C 28 N.C.
N.C. 3 N.C
N.C 29 N.C.
N.C. 2 N.C
N.C 30 N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
31
32
33
34
35
36
37
38
39
40
A GND
N.C
N.C
N.C
N.C
A V CC
A V EE
N.C
N.C
N.C.
AVCC
N.C
1 AGND
Rev.1.0 Sep 09, 2004 page 2 of 15
AVEE
M61541FP
Preliminary
Pin Description
Pin No.
Pin Name
Function
1, 8, 25, 32
2, 3, 28, 29, 30, 31,
33, 34, 35, 36, 39, 40
AGND
Analog Ground
NC
NC
4
5
CIN
SWIN
Input pin of C channel
Input pin of SW channel
6
7
SLIN
SRIN
Input pin of SL channel
Input pin of SR channel
9
10
SROUT
SLOUT
Output pin of SR channel
Output pin of SL channel
11
12
SWOUT
COUT
Output pin of SW channel
Output pin of C channel
13
14
DVDD
DATA
Power supply to internal logic circuit
Input pin of control data
15
16
CLOCK
DGND
Input pin of control clock
Ground of internal logic circuit
17
18
ROUT
LOUT
Output pin of R channel
Output pin of L channel
19, 20
21, 22
BASR1, BASR2
BASL1, BASL2
Frequency characteristic setting pin of R channel tone control (BASS)
Frequency characteristic setting pin of L channel tone control (BASS)
23
24
TRER
TREL
Frequency characteristic setting pin of R channel tone control (Treble)
Frequency characteristic setting pin of L channel tone control (Treble)
26
27
RIN
LIN
Input pin of R channel
Input pin of L channel
37
38
AVCC
AVEE
Positive power supply to internal analog circuit
Negative power supply to internal analog circuit
Rev.1.0 Sep 09, 2004 page 3 of 15
M61541FP
Preliminary
Absolute Maximum Ratings
Parameter
Symbol
Power Supply
AVCC-AVEE
DVDD
Power dissipation
Thermal derating
Pd
K
Operating temperature
Storage temperature
Topr
Tstg
Ratings
Unit
16
6
V
1.46
85.3
W
mW/°C
–20 to +75
–40 to +125
°C
°C
Condition
AVCC-AVEE
DVDD-DGND
Ta≤25°C
Ta>25°C
Note: AVEE≤DGND<DVDD≤AVCC
THERMAL DERATINGS (MAXIMUM RATING)
POWER DI SSI PA TI ON pd (W)
2.0
1.46W
1.5
1.0
0.88
0.5
0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE Ta ( °C )
Recommended Operating Conditions
(Ta=25°C, unless otherwise noted.)
Min
Typ
Max
Unit
Analog Supply Voltage (Positive)
Analog Supply Voltage (Negative)
Parameter
AVCC
AVEE
Symbol
4.5
−7.5
7.0
−7.0
7.5
−4.5
V
V
Digital Supply Voltage
Logic “H” level Input Voltage
DVDD
VIH
3.0
DVDD×0.7
3.3
5.5
DVDD
V
V
DGND reference
DGND
DVDD×0.2
V
DGND reference
Logic “L” level Input Voltage
VIL
Note: AVEE≤DGND<DVDD≤AVCC
Rev.1.0 Sep 09, 2004 page 4 of 15
Condition
M61541FP
Preliminary
Relationship Between Data and Clock
Make "H" at the timing which
DATA of D0-D23 make latch.
Data signal is read at the rising edge of CLOCK.
DATA
D0
D1
D2
D3
D21
D22
D23
CLOCK
When DATA is "H", latch signal is
created at the falling edge of CLOCK.
When CLOCK is "L" and latch signal is created,
latch signal is read at the falling edge of DATA.
Clock and Data Timings
DATA
LATCH
t cr
(D0 to D23)
75%
25%
tSLD
tSLD
tHLD tSHD
tSC
75%
50%
25%
CLOCK
tHLD
tHHD
tf
tr
tWHC
tWLC
Timing Definition of Digital Block
Parameter
Symbol
Min
Limits
Typ
Max
CLOCK cycle time
CLOCK pulse width ("H" level)
tcr
tWHC
8
3.2
CLOCK pulse width ("L" level)
Rising time of clock and data
tWLC
tr
3.2
0.8
Falling time of clock and data
DATA setup time (Rising time of clock)
tf
tSHD
1.6
0.8
DATA setup time (Falling time of clock)
DATA hold time ("H" level)
tSLD
tHHD
1.6
1.6
DATA hold time ("L" level)
CLOCK setup time
tHLD
tSC
1.6
1.6
Rev.1.0 Sep 09, 2004 page 5 of 15
Unit
µs
M61541FP
Preliminary
Power on Reset
DVDD(13pin) - DGND(16pin)
This IC built-in the power on reset function.
The voltage of DVDD (13 pin) -DGND (16 pin) less than 2.6V, the serial DATA can not accept.
(V)
2.6 V
(S)
Reset time
After reset is canceled, the serial DATA can accept.
Release of reset.
Note:
AVEE≤DGND<DVDD≤AVCC
Data Control Specification
Initialize all data of the 4 formats when Digital Power supply (DVDD) turns on.
Prohibit using except specified Data code as follows.
Slot1
D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14a D15a D16a D17a D18a D19a D20a D21a D22 D23
1/0 1/0
1/0 1/0 1/0
1/0
1/0 1/0
(1) Bass/
Tone control Bypass
(2) Treble
0
0
0
0
0
0
0
0
Slot2
D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14b D15bD16b D17b D18b D19b D20b D21b D22 D23
(3)
Lch Gain
Control
(4)Lch Volume
(3)
RchGain
Control
(4)Rch Volume
0
0
0
0
0
1
Slot3
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14c D15c D16c D17c D18c D19c D20c D21c D22 D23
(3)
CchGain
Control
(4)Cch Volume
(3)
SWchGain
Control
(4)SWchVolume
0
0
0
0
1
0
Slot4
D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10d D11d D12d D13d D14d D15d D16d D17d D18d D19d D20d D21d D22 D23
(3)
SLch Gain
Control
Note:
(4)SLchVolume
(3)
SRchGain
Control
No guarantee except for these codes.
Rev.1.0 Sep 09, 2004 page 6 of 15
(4)SRchVolume
0
0
0
0
1
1
M61541FP
Preliminary
Setting Code
It’s initial setting when power is turned on.
(1) Bass/Bypass (Tone control is bypass)
(2) Treble
ATT Setting
+14dB
D8a
1
D9a
1
D10a
1
D11a
1
ATT Setting
+14dB
D12a
1
D13a
1
D14a
1
D15a
1
+12dB
+10dB
1
1
1
1
1
0
0
1
+12dB
+10dB
1
1
1
1
1
0
0
1
+8dB
+6dB
1
1
1
0
0
1
0
1
+8dB
+6dB
1
1
1
0
0
1
0
1
+4dB
+2dB
1
1
0
0
1
0
0
1
+4dB
+2dB
1
1
0
0
1
0
0
1
0dB
−2dB
1
0
0
0
0
0
0
1
0dB
−2dB
1/0
0
0
0
0
0
0
1
−4dB
−6dB
0
0
0
0
1
1
0
1
−4dB
−6dB
0
0
0
0
1
1
0
1
−8dB
−10dB
0
0
1
1
0
0
0
1
−8dB
−10dB
0
0
1
1
0
0
0
1
−12dB
−14dB
0
0
1
1
1
1
0
1
−12dB
−14dB
0
0
1
1
1
1
0
1
0
0
0
Bypass*
0
* Tone control is bypass.
(3) Gain Control
Lch
Rch
D0b
D9b
D1b
D10b
Cch
SWch
D0c
D9c
D1c
D10c
SLch
SRch
D0d
D9d
D1d
D10d
0dB
6dB
0
0
0
1
12dB
18dB
1
1
0
1
ATT
Setting
Rev.1.0 Sep 09, 2004 page 7 of 15
M61541FP
Preliminary
(4) 6channel Volume
It’s initial setting when power is turned on.
Lch
D2b
D3b
D4b
D5b
D6b
D7b
D8b
Rch
Cch
D11b
D2c
D12b
D3c
D13b
D4c
D14b
D5c
D15b
D6c
D16b
D7c
D17b
D8c
SWch
SLch
D11c
D2d
D12c
D3d
D13c
D4d
D14c
D5d
D15c
D6d
D16c
D7d
D17c
D8d
SRch
0dB
D11d
0
D12d
0
D13d
0
D14d
0
D15d
0
D16d
0
D17d
0
–1dB
–2dB
0
0
0
0
0
0
0
0
0
0
0
1
1
0
–3dB
–4dB
0
0
0
0
0
0
0
0
0
1
1
0
1
0
–5dB
–6dB
0
0
0
0
0
0
0
0
1
1
0
1
1
0
–7dB
–8dB
0
0
0
0
0
0
0
1
1
0
1
0
1
0
–9dB
–10dB
0
0
0
0
0
0
1
1
0
0
0
1
1
0
–11dB
–12dB
0
0
0
0
0
0
1
1
0
1
1
0
1
0
–13dB
–14dB
0
0
0
0
0
0
1
1
1
1
0
1
1
0
–15dB
–16dB
0
0
0
0
0
1
1
0
1
0
1
0
1
0
–17dB
–18dB
0
0
0
0
1
1
0
0
0
0
0
1
1
0
–19dB
–20dB
0
0
0
0
1
1
0
0
0
1
1
0
1
0
–21dB
–22dB
0
0
0
0
1
1
0
0
1
1
0
1
1
0
–23dB
–24dB
0
0
0
0
1
1
0
1
1
0
1
0
1
0
–25dB
–26dB
0
0
0
0
1
1
1
1
0
0
0
1
1
0
–27dB
–28dB
0
0
0
0
1
1
1
1
0
1
1
0
1
0
–29dB
–30dB
0
0
0
0
1
1
1
1
1
1
0
1
1
0
–31dB
–32dB
0
0
0
1
1
0
1
0
1
0
1
0
1
0
–33dB
–34dB
0
0
1
1
0
0
0
0
0
0
0
1
1
0
–35dB
–36dB
0
0
1
1
0
0
0
0
0
1
1
0
1
0
–37dB
–38dB
0
0
1
1
0
0
0
0
1
1
0
1
1
0
–39dB
–40dB
0
0
1
1
0
0
0
1
1
0
1
0
1
0
–41dB
–42dB
0
0
1
1
0
0
1
1
0
0
0
1
1
0
–43dB
0
1
0
1
0
1
1
ATT
Rev.1.0 Sep 09, 2004 page 8 of 15
M61541FP
Preliminary
Lch
D2b
D3b
D4b
D5b
D6b
D7b
D8b
Rch
Cch
D11b
D2c
D12b
D3c
D13b
D4c
D14b
D5c
D15b
D6c
D16b
D7c
D17b
D8c
SWch
SLch
D11c
D2d
D12c
D3d
D13c
D4d
D14c
D5d
D15c
D6d
D16c
D7d
D17c
D8d
SRch
–44dB
D11d
0
D12d
1
D13d
0
D14d
1
D15d
1
D16d
0
D17d
0
–45dB
–46dB
0
0
1
1
0
0
1
1
1
1
0
1
1
0
–47dB
–48dB
0
0
1
1
0
1
1
0
1
0
1
0
1
0
–49dB
–50dB
0
0
1
1
1
1
0
0
0
0
0
1
1
0
–51dB
–52dB
0
0
1
1
1
1
0
0
0
1
1
0
1
0
–53dB
–54dB
0
0
1
1
1
1
0
0
1
1
0
1
1
0
–55dB
–56dB
0
0
1
1
1
1
0
1
1
0
1
0
1
0
–57dB
–58dB
0
0
1
1
1
1
1
1
0
0
0
1
1
0
–59dB
–60dB
0
0
1
1
1
1
1
1
0
1
1
0
1
0
–61dB
–62dB
0
0
1
1
1
1
1
1
1
1
0
1
1
0
–63dB
–64dB
0
1
1
0
1
0
1
0
1
0
1
0
1
0
–65dB
–66dB
1
1
0
0
0
0
0
0
0
0
0
1
1
0
–67dB
–68dB
1
1
0
0
0
0
0
0
0
1
1
0
1
0
–69dB
–70dB
1
1
0
0
0
0
0
0
1
1
0
1
1
0
–71dB
–72dB
1
1
0
0
0
0
0
1
1
0
1
0
1
0
–73dB
–74dB
1
1
0
0
0
0
1
1
0
0
0
1
1
0
–75dB
–76dB
1
1
0
0
0
0
1
1
0
1
1
0
1
0
–77dB
–78dB
1
1
0
0
0
0
1
1
1
1
0
1
1
0
–79dB
–80dB
1
1
0
0
0
1
1
0
1
0
1
0
1
0
–81dB
–82dB
1
1
0
0
1
1
0
0
0
0
0
1
1
0
–83dB
–84dB
1
1
0
0
1
1
0
0
0
1
1
0
1
0
–85dB
–86dB
1
1
0
0
1
1
0
0
1
1
0
1
1
0
–87dB
–88dB
1
1
0
0
1
1
0
1
1
0
1
0
1
0
–89dB
–90dB
1
1
0
0
1
1
1
1
0
0
0
1
1
0
ATT
Rev.1.0 Sep 09, 2004 page 9 of 15
M61541FP
Preliminary
Lch
D2b
D3b
D4b
D5b
D6b
D7b
D8b
Rch
Cch
D11b
D2c
D12b
D3c
D13b
D4c
D14b
D5c
D15b
D6c
D16b
D7c
D17b
D8c
SWch
SLch
D11c
D2d
D12c
D3d
D13c
D4d
D14c
D5d
D15c
D6d
D16c
D7d
D17c
D8d
SRch
–91dB
D11d
1
D12d
0
D13d
1
D14d
1
D15d
0
D16d
1
D17d
1
–92dB
–93dB
1
1
0
0
1
1
1
1
1
1
0
0
0
1
–94dB
–95dB
1
1
0
0
1
1
1
1
1
1
1
1
0
1
–96dB
–97dB
1
1
1
1
0
0
0
0
0
0
0
0
0
1
–98dB
–99dB
1
1
1
1
0
0
0
0
0
0
1
1
0
1
1/0
1
1/0
1/0
ATT
–∞dB
1
1
1/0
Note: No guarantee except for these codes.
Electrical Characteristics
(Unless otherwise noted, Ta = 25°C, AVCC = 7V, AVEE = –7V, DVDD = 5V, f = 1kHz, Volume = 0dB,
Gain Control = 0dB, Tone = Bypass)
(1) Power supply characteristics
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Analog positive power circuit current
AIcc
32
42
mA
Analog negative power circuit current
AIee
–42
–32
mA
Digital power circuit current
DIdd
2
3
mA
Rev.1.0 Sep 09, 2004 page 10 of 15
Test condition
With AVCC = 7V and AVEE = –7V
37pin current, when no signal is provided
With AVCC = 7V and AVEE = –7V
38pin current, when no signal is provided
With DVDD = 3.3V,
13pin current, when no signal is provided
M61541FP
Preliminary
(2) Input/Output characteristics (OVER ALL)
Limits
Symbol Min
Rin
17
Typ
25
Max
33
Unit
Maximum
output voltage
VOM
3.8
4.4
—
Vrms
Pass gain
Gv
–2.0
0
2.0
dB
Parameter
Input resistance
Total harmonic
THD
distortion
Balance of
CBAL
mutual channels
Output noise
voltage
Channel
separation
—
kΩ
0.0008 0.008
–0.5
0
0.5
Vono1
0.9
4.5
3
15
Vono2
1
5
3
15
Vono3
1
5
3
15
CS
—
–90
–70
Test condition
4 to 7,26,27 pin
4 to 7,26,27pin input, 9 to 12,17,18pin output,
THD = 1%, RL = 10kΩ, Output Gain Control = +6dB
4 to 7,26,27pin input, 9 to 12,17,18pin output,
Vi = 0.3Vrms, FLAT
%
4 to 7,26,27pin input, 9 to 12,17,18pin output,
BW: 400Hz to 30kHz, f = 1kHz, Vo = 0.5Vrms, RL = 10kΩ
dB
26,27pin input, 17,18pin output, Vi = 0.5Vrms, JIS-A
µVrms
JIS-A, Rg = 0Ω, 17,18pin output,
Volume = –∞dB setting
Output Gain Control = 0dB
Output Gain Control = +12dB
JIS-A, Rg = 0Ω, 17,18pin output,
Volume = 0dB setting
Output Gain Control = 0dB
Output Gain Control = +12dB
JIS-A, Rg = 0Ω, 9 to 12pin output, Output Gain Control = 0dB
Volume = 0dB setting
Output Gain Control = +12dB
dB
Vo = 1Vrms, Rg = 0Ω, RL = 10kΩ, JIS-A
(3) 6 channel Volume characteristics
Limits
Parameter
Symbol
Maximum attenuation
ATTmax
Min Typ Max
— –100 –95
Volume gain gang error
of mutual channels
Dvol
–0.5
0
+0.5
Unit
Test condition
dB
Vi = 2Vrms, JIS-A, VOL = –∞dB
dB
Volume = 0dB
(4) Tone control characteristics
(Unless otherwise noted, Tone ON/OFF = ON)
Limits
Parameter
Tone control voltage gain
(Boost/Bass)
Tone control voltage gain
(Cut/Bass)
Tone control voltage gain
(Boost/Treble)
Tone control voltage gain
(Cut/Treble)
Balance of mutual channels
Rev.1.0 Sep 09, 2004 page 11 of 15
Symbol
Min
Typ
Max
Unit
G (BASS) B
+12
+14
+16
dB
G (BASS) C
–16
–14
–12
dB
G (TRE) B
+12
+14
+16
dB
G (TRE) C
–16
–14
–12
dB
BALT
–2
0
+2
dB
Test condition
f = 100Hz
Bass +14dB setting
f = 100Hz
Bass –14dB setting
f = 10kHz
Treble +14dB setting
f = 10kHz
Treble –10dB setting
Bass setting +14, –14dB
Treble setting +14, –14dB
M61541FP
Preliminary
Tone Control
(1) Bass
< Boost >
-
+
IN
OUT
+
[Designed Parameter]
R1=4.7kΩ, C1=0.047µF, C2=0.15µF
R3
Gain
Setting
R2
f0 =
C1
0.047µ
1
2 π R1(R2+R3)C1C2
+14dB
+12dB
+10dB
+8dB
+6dB
+4dB
+2dB
(Hz)
(R2+R3)R1C1C2
C2
0.15µ
Q=
R1
4.7K
R1(C1+C2)+R3C1
Gv = 20 log
R1(C1+C2)+(R2+R3)C1
Designed Parameter
R3(k Ω ) R2(k Ω )
0.19
79.81
5.21
74.66
11.83
68.17
19.99
60.01
30.27
49.73
43.21
36.79
59.49
20.51
(dB)
R1(C1+C2)+R3C1
< Cut >
IN
+
-
-
+
R2
OUT
R3
[Designed Parameter]
R1=4.7kΩ , C1=0.047µF , C2=0.15µF
f0 =
1
2 π R1(R2+R3)C1C2
C2
0.15 µ
(Hz)
R1
4.7K
(R2+R3)R1C1C2
Q=
R1(C1+C2)+R3C1
Gv = 20 log
R1(C1+C2)+R3C1
R1(C1+C2)+(R2+R3)C1
Rev.1.0 Sep 09, 2004 page 12 of 15
C1
0.047µ
(dB)
Designed Parameter
Gain
Setting
R2(k Ω )
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
79.81
74.66
68.17
60.01
49.73
36.79
20.51
R3(k Ω )
0.19
5.21
11.83
19.99
30.27
43.21
59.49
M61541FP
Preliminary
(2) Treble
[Designed Parameter]
RC=0.022µF
< Boost >
+
+
IN
R5
R4
Gv =20 log
Gain
Setting
OUT
(R4+R5)2+ RC2
2
(dB)
R4 +RC
RC
2
+14dB
+12dB
+10dB
+8dB
+6dB
+4dB
+2dB
Designed Parameter
R4(k Ω ) R5(kΩ )
1.03
5.23
1.41
4.85
1.86
4.40
2.40
3.86
3.06
3.20
3.90
2.36
4.95
1.31
0.022µ
2
Gv =20 log
<Cut >
2
R4 +RC
2
IN
(R4+R5) + RC
+
R5
[Designed Parameter]
RC=0.022µF
-
+
OUT
Gain
Setting
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
R4
RC
0.022 µ
Tone gain Gv (dB)
Curve of characteristics
Frequency f(Hz)
Rev.1.0 Sep 09, 2004 page 13 of 15
(dB)
2
Designed Parameter
R5(k Ω )
5.23
4.85
4.40
3.86
3.20
2.36
1.31
R4(kΩ )
1.03
1.41
1.86
2.40
3.06
3.90
4.95
M61541FP
Preliminary
Application Example
0.15 µ
20
4.7k
0.047µ
L
R
4.7µ
4.7µ
+
18
19
+
17
DVDD
3.3V
4.7µ
100 µ 0.1 µ
16
15
14
MCU I/F
Gain
Control
Gain
Control
+
MCU
SW
C
13
+
12
4.7µ
+
11
DVDD
4.7 µ
+
-
10
-
0.047µ
+
4.7 µ
4.7k
22
9
Gain
Control
Bass
/Tre
+
-
+
-
+
+
+
2.2µ
+
Logic
5
50k
2.2 µ
LIN
+
25k
Lch Vol
26
2.2µ
2.2µ
25k
25k
25k
25k
Cch Vol SWch Vol SLch Vol SRch Vol
25k
Rch Vol
6
2.2 µ
2.2µ
SRIN
7
25
RIN
+
+
Bass
/Tre
Gain
Control
+
0.022 µ
24
Gain
Control
8
-
23
Gain
Control
-
0.022 µ
27
4
36
37
N.C.
N.C.
35
38
39
40
N.C.
34
N.C.
N.C.
33
AVEE
N.C.
N.C.
N.C.
32
N.C.
1
N.C.
N.C. 30 N.C.
N.C.
N.C. 2 N.C.
N.C.
N.C. 29 N.C.
N.C.
N.C. 3 N.C.
N.C.
N.C. 28 N.C.
AVCC
+
+
100 µ 0.1 µ100 µ 0.1 µ
AVCC AVEE
7V
-7V
Rev.1.0 Sep 09, 2004 page 14 of 15
SLIN
SWIN
50k
31
SR
+
0.15 µ
SL
+
21
CIN
M61541FP
Preliminary
Package Dimensions
JEITA Package Code
P-LQFP40-7x7-0.65
RENESAS Code
PLQP0040JB-A
Previous Code
FP-40B
MASS[Typ.]
0.2g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
30
21
31
20
bp
Reference
Symbol
D
c
c1
HE
Dimension in Millimeters
Min
Nom
Max
7.0
E
7.0
A2
1.40
*2
E
b1
ZE
Terminal cross section
11
40
1
Index mark
A2
L1
y
9.2
A1
0.08
0.13
0.22
bp
0.20
0.25
0.30
x
M
θ
0.22
0.12
0.17
0.22
0.15
0°
e
8°
0.65
x
0.13
y
0.10
ZD
0.575
ZE
L
L1
Rev.1.0 Sep 09, 2004 page 15 of 15
1.70
c1
c
A
A1
L
Detail F
bp
9.2
9.0
c
θ
*3
9.0
8.8
b1
F
e
8.8
HE
A
10
ZD
HD
0.575
0.40
0.50
1.0
0.60
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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