Revised February 2005 74VHC74 Dual D-Type Flip-Flop with Preset and Clear General Description Features The VHC74 is an advanced high speed CMOS Dual DType Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. ■ High Speed: fMAX 170 MHz (typ) at TA ■ High noise immunity: VNIH VNIL 25qC 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low power dissipation: ICC 2 PA (max) at TA 25qC ■ Pin and function compatible with 74HC74 An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Code: Order Number Package Package Description Number 74VHC74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC74MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC74MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDED J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS011505 www.fairchildsemi.com 74VHC74 Dual D-Type Flip-Flop with Preset and Clear October 1992 74VHC74 Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Truth Table Inputs Description D1 , D2 Data Inputs CK1, CK2 Clock Pulse Inputs CLR1, CLR2 Direct Clear Inputs PR1, PR2 Q1, Q1, Q2, Q2 Outputs CLR PR D CK Function Q Q L H X X L H Clear H L X X H L Preset L L X Direct Preset Inputs H H L Output H H H H H X X H (Note 2) H (Note 2) L H H L Qn Qn No Change Note 2: This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) state. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 4) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) 2.0V to 5.5V 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r 0.3V 0 a 100 ns/V VCC 5.0V r 0.5V 0 a 20 ns/V Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading varaibles. Fairchild does not recommend operation outside databook specifications. 260qC Soldering (10 seconds) Supply Voltage (VCC) Input Voltage (VIN) Note 4: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL VCC (V) TA Min 25qC Typ TA Max 40qC to 85qC Min 2.0 1.50 1.50 3.0 5.5 0.7 VCC 0.7 VCC Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 VIN 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 Quiescent Supply Current 0.0 0.1 IOH V Voltage ICC VIH IOH 50 PA or VIL 4.4 2.0 Input Leakage Current V V LOW Level Output IIN Conditions V 3.0 5.5 HIGH Level Output Units 0.1 IOH VIN V VIH IOL 4 mA 8 mA 50 PA or VIL 3.0 0.36 0.44 4.5 0.36 0.44 0 5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 2.0 20.0 PA VIN VCC or GND 3 V IOL 4 mA IOL 8 mA www.fairchildsemi.com 74VHC74 Absolute Maximum Ratings(Note 3) 74VHC74 AC Electrical Characteristics Symbol fMAX Parameter Maximum Clock TA tPHL Time (CK-Q, Q) 3.3 r 0.3 80 125 70 50 75 45 130 170 110 90 115 75 3.3 r 0.3 5.0 r 0.5 tPLH Propagation Delay Time tPHL (CLR, PR -Q, Q) 40qC to 85qC Typ 5.0 r 0.5 Propagation Delay TA Min Frequency tPLH 25qC VCC (V) 3.3 r 0.3 5.0 r 0.5 Max Min Max MHz MHz 6.7 11.9 1.0 14.0 9.2 15.4 1.0 17.5 4.6 7.3 1.0 8.5 6.1 9.3 1.0 10.5 7.6 12.3 1.0 14.5 10.1 15.8 1.0 18.0 4.8 7.7 1.0 9.0 6.3 9.7 1.0 11.0 10 CIN Input Capacitance 4 CPD Power Dissipation 25 Units 10 ns ns ns ns Conditions CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF pF VCC pF (Note 5) Open Capacitance Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) CPD * VCC * fIN I CC/2 (per F/F). AC Operating Requirements Symbol tW(L) Parameter Minimum Pulse Width (CK) tW(H) tW(L) Minimum Pulse Width (CLR, PR) tS Minimum Setup Time tH Minimum Hold Time tREC Minimum Recovery Time (CLR, PR) VCC (V) (Note 6) 25qC TA 40qC to 85qC Guaranteed Minimum 3.3 6.0 7.0 5.0 5.0 5.0 3.3 6.0 7.0 5.0 5.0 5.0 3.3 6.0 7.0 5.0 5.0 5.0 3.3 0.5 0.5 5.0 0.5 0.5 3.3 5.0 5.0 5.0 3.0 3.0 Note 6: VCC is 3.3 r 0.3V or 5.0 r 0.5V www.fairchildsemi.com TA Typ 4 Units ns ns ns ns ns 74VHC74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHC74 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHC74 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHC74 Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8