Revised April 1999 74VHC112 Dual J-K Flip-Flops with Preset and Clear General Description The VHC112 is an advanced high speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The LOW signal on PR or CLR prevents clocking and forces Q and Q HIGH, respectively. Simultaneous LOW signals on PR and CLR force both Q and Q HIGH. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High speed: fMAX = 200 MHz (typ) at VCC = 5.0V ■ Low power dissipation: ICC = 2 µA (max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Pin and function compatible with 74HC112 Ordering Code: Order Number 74VHC112M 74VHC112SJ 74VHC112MTC 74VHC112N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation DS012123.prf Description J1, J2, K1, K2 Data Inputs CLK1, CLK2 Clock Pulse Inputs (Active Falling Edge) CLR1, CLR2 Direct Clear Inputs (Active LOW) PR1, PR2 Direct Preset Inputs (Active LOW) Q1, Q2, Q1, Q2 Outputs www.fairchildsemi.com 74VHC112 Dual J-K Flip-Flops with Preset and Clear September 1995 74VHC112 Truth Table Inputs Outputs PR CLR CP J K Q Q L H X X X H L H L X X X L H L L X X X H H H H h h Q0 Q0 H H l h L H H H H H h l H L l l Q0 Q0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) 2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT ) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC/GND Current (ICC) ±50 mA VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL VCC (V) TA = 25°C Min Typ TA = −40°C to +85°C Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC HIGH Level 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 VIN = VIH IOH = −50 µA 2.0 0.0 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 Input Leakage Current Quiescent Supply Current or VIL IOH = −4 mA V Output Voltage ICC V V LOW Level IIN Conditions V 3.0 − 5.5 Output Voltage Units IOH = −8 mA VIN = VIH IOL = 50 µA V or VIL IOL = 4 mA 3.0 0.36 0.44 4.5 0.36 0.44 0 − 5.5 ±0.1 ±1.0 µA V IN = 5.5V or GND 5.5 2.0 20.0 µA V IN = VCC or GND 3 V IOL = 8 mA www.fairchildsemi.com 74VHC112 Absolute Maximum Ratings(Note 1) 74VHC112 AC Electrical Characteristics Symbol fMAX Parameter Maximum Clock Propagation Delay tPHL Time (CP to Qn or Qn) Typ 3.3 ± 0.3 110 150 90 120 80 5.0 ± 0.5 150 200 135 120 185 110 3.3 ± 0.3 5.0 ± 0.5 tPLH Propagation Delay Time tPHL (PR or CLR to Qn or Qn) TA = −40°C to +85°C Min Frequency tPLH TA = 25°C VCC (V) 3.3 ± 0.3 5.0 ± 0.5 Max Min Max 100 MHz MHz 8.5 11.0 1.0 13.4 10.0 15.0 1.0 16.5 5.1 7.3 1.0 8.8 6.3 10.5 1.0 12.0 6.7 10.2 1.0 11.7 9.7 13.5 1.0 15.0 4.6 6.7 1.0 8.0 6.4 9.5 1.0 11.0 10 CIN Input Capacitance 4 CPD Power Dissipation 18 Units 10 ns ns ns ns Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF pF VCC = Open pF (Note 3) Capacitance Note 3: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 • n AC Operating Requirements Symbol tW tS tH tREC Parameter VCC (Note 4) (V) TA = 25°C Typ TA = −40°C to +85°C Guaranteed Minimum Minimum Pulse Width 3.3 5.0 5.0 (CP or CLR or PR) 5.0 5.0 5.0 Minimum Setup Time 3.3 5.0 5.0 (Jn or Kn to CPn) 5.0 4.0 4.0 Minimum Hold Time 3.3 1.0 1.0 (Jn or Kn to CPn) 5.0 1.0 1.0 Minimum Recovery Time 3.3 6.0 6.0 (CLR or PR to CP) 5.0 5.0 5.0 Note 4: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V www.fairchildsemi.com 4 Units ns ns ns ns 74VHC112 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com 74VHC112 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC112 Dual J-K Flip-Flops with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued)