Revised June 2005 74LVT162244 • 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs General Description Features The LVT162244 and LVTH162244 contain sixteen noninverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. ■ Input and output interface capability to systems at 5V VCC The LVT162244 and LVTH162244 are designed with equivalent 25: series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162244 and LVTH162244 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH162244), also available without bushold feature (74LVT162244). ■ Live insertion/extraction permitted ■ Power Up/Power Down high impedance provides glitchfree bus loading ■ Outputs include equivalent series resistance of 25: to make external termination resistors unnecessary and reduce overshoot and undershoot ■ Functionally compatible with the 74 series 162244 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device ! 1000V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Order Number 74LVT162244G (Note 1)(Note 2) Package Number BGA54A Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVT162244MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT162244MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH162244G (Note 1)(Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVTH162244MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [Tube] 74LVTH162244MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [Tape and Reel] 74LVTH162244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [Tube] 74LVTH162244MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [Tape and Reel] Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2005 Fairchild Semiconductor Corporation DS012445 www.fairchildsemi.com 74LVT162244 • 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs March 1999 74LVT162244 • 74LVTH162244 Logic Symbol Pin Descriptions Pin Names Description OEn Output Enable Inputs (Active LOW) I0–I15 Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments Connection Diagrams Pin Assignment for SSOP and TSSOP 1 2 3 4 5 6 A O0 NC OE1 OE2 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 G O12 O11 VCC VCC I11 I12 H O14 O13 NC NC I13 I14 J O15 NC OE4 OE3 NC I15 Truth Table Inputs Pin Assignment for FBGA I0–I3 L L L L H H H X Z OE2 I4–I7 O4–O7 L L L L H H (Top Thru View) www.fairchildsemi.com 2 O0–O3 H X Z OE3 I8–I11 O8–O11 L L L L H H H X Z OE4 I12–I15 O12–O15 L L L L H H X Z H H Z Outputs OE1 HIGH Voltage Level High Impedance L LOW Voltage Level X Immaterial The LVT162244 and LVTH162244 contain sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Logic Diagram 3 www.fairchildsemi.com 74LVT162244 • 74LVTH162244 Functional Description 74LVT162244 • 74LVTH162244 Absolute Maximum Ratings(Note 3) Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value Conditions 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Units V V Output in 3-STATE V Output in HIGH or LOW State (Note 4) VI GND mA VO GND mA 64 VO ! VCC Output at HIGH State 128 VO ! VCC Output at LOW State mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage Min Max 2.7 3.6 Units V 0 5.5 V IOH HIGH-Level Output Current 12 mA IOL LOW-Level Output Current 12 mA TA Free Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V 40 85 qC 0 10 ns/V Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC Parameter VIK Input Clamp Diode Voltage (V) TA 40qC to 85qC Min VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC0.2 3.0 2.0 VOL II(HOLD) Output LOW Voltage Bushold Input Minimum Drive II(OD) Bushold Input Over-Drive (Note 5) Current to Change State II Input Current Data Pins IOFF IPU/PD Power Off Leakage Current Power Up/Down 3-STATE Current 0.8 Units 3.0 0.8 75 II V VO d 0.1V or V VO t VCC 0.1V V PA 75 500 PA 500 Conditions 18 mA V V 0.2 3.0 Control Pins 2.0 2.7 3.0 (Note 5) Max 1.2 2.7 IOH 100 PA IOH 12 mA IOL 100 PA IOL 12 mA VI 0.8V VI 2.0V (Note 6) (Note 7) 3.6 10 VI 5.5V 3.6 r1 VI 0V or VCC VI 0V VI VCC 5 3.6 PA 1 0 r100 PA 0–1.5V r100 PA 0V d VI or VO d 5.5V VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled www.fairchildsemi.com 4 Symbol (Continued) VCC Parameter ICCZ Power Supply Current 'ICC Increase in Power Supply Current (Note 8) 40qC to 85qC TA (V) Min Units Conditions Max 3.6 0.19 mA 3.6 0.2 mA VCC d VO d 5.5V, Outputs Disabled One Input at VCC 0.6V Other Inputs at VCC or GND Note 5: Applies to bushold versions only (74LVTH162244). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol (Note 9) Parameter (V) 25qC TA VCC Min Conditions Typ Units Max CL 500: 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 10) Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA Symbol tPLH VCC Parameter 1.4 4.0 1.4 4.8 1.2 3.7 1.2 4.1 1.2 5.1 1.2 6.5 1.4 5.4 1.4 6.9 2.0 5.0 2.0 5.4 1.5 5.0 1.5 5.4 Output Disable Time tPLZ Output to Output Skew (Note 11) Units Max Output Enable Time tOSLH 500: 2.7V Min Propagation Delay Data to Output tOSHL VCC Max tPZL tPHZ 50 pF, RL Min tPHL tPZH 40qC to 85qC, CL 3.3V r 0.3V 1.0 1.0 ns ns ns ns Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance Symbol (Note 12) Parameter Conditions CIN Input Capacitance VCC 0V, VI COUT Output Capacitance VCC 3.0V, VO Note 12: Capacitance is measured at frequency f 0V or VCC 0V or VCC Typical Units 4 pF 8 pF 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVT162244 • 74LVTH162244 DC Electrical Characteristics 74LVT162244 • 74LVTH162244 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 6 74LVT162244 • 74LVTH162244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com 74LVT162244 • 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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