Revised June 2005 74LVT16373 • 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs General Description Features The LVT16373 and LVTH16373 contain sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LVTH16373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16373 and LVTH16373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Input and output interface capability to systems at 5V VCC ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16373), also available without bushold feature (74LVT16373) ■ Live insertion/extraction permitted ■ Power Up/Power Down high impedance provides glitch-free bus loading ■ Outputs source/sink 32 mA/64 mA ■ Functionally compatible with the 74 series 16373 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number Package Number 74LVT16373GX (Note 1) BGA54A (Preliminary) Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVT16373MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16373MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16373GX (Note 1) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVTH16373MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16373MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: BGA package available in Tape and Reel only. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation DS012021 www.fairchildsemi.com 74LVT16373 • 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs January 1999 74LVT16373 • 74LVTH16373 Connection Diagrams Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names Description OEn Output Enable Input (Active LOW) LEn Latch Enable Input I0–I15 Inputs O0–O15 3-STATE Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 LE1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE2 LE2 NC I15 Truth Tables Inputs Pin Assignment for FBGA Outputs LE1 OE1 I0–I7 O0–O7 Z X H X H L L L H L H H L L X Oo Inputs (Top Thru View) H L X Z Oo www.fairchildsemi.com 2 Outputs LE2 OE2 I8–I15 O8–O15 X H X Z H L L L H L H H L L X Oo HIGH Voltage Level LOW Voltage Level Immaterial HIGH Impedance Previous output prior to HIGH-to-LOW transition of LE The LVT16373 and LVTH16373 contain sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVT16373 • 74LVTH16373 Functional Description 74LVT16373 • 74LVTH16373 Absolute Maximum Ratings(Note 3) Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value Conditions 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Units V V Output in 3-STATE V Output in HIGH or LOW State (Note 4) VI GND mA VO GND mA 64 VO ! VCC Output at HIGH State 128 VO ! VCC Output at LOW State mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage Min Max 2.7 3.6 Units V 0 5.5 V IOH HIGH Level Output Current 32 mA IOL LOW Level Output Current 64 mA TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V 40 85 qC 0 10 ns/V Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VIK Input Clamp Diode Voltage TA VCC Parameter (V) 40qC to 85qC Min 2.7 VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) Output LOW Voltage Bushold Input Minimum Drive II(OD) Bushold Input Over-Drive (Note 5) Current to Change State II Input Current Data Pins IOFF IPU/PD Power Off Leakage Current Power Up/Down 3-STATE Output Current Conditions V V VO d 0.1V or 0.8 V VO t VCC 0.1V IOH 100 PA V IOH 8 mA 2.0 II 32 mA IOL 100 PA IOL 24 mA IOL 16 mA 32 mA 2.7 0.5 3.0 0.4 3.0 0.5 IOL 3.0 0.55 IOL 75 V PA 75 500 PA 500 18 mA IOH 0.2 3.0 Control Pins Units 1.2 2.7 3.0 (Note 5) Max 64 mA VI 0.8V VI 2.0V (Note 6) (Note 7) 3.6 10 VI 5.5V 3.6 r1 VI 0V or VCC VI 0V VI VCC 5 3.6 PA 1 0 r100 PA 0–1.5V r100 PA 0V d VI or VO d 5.5V VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V www.fairchildsemi.com 4 Symbol (Continued) VCC Parameter TA (V) 40qC to 85qC Min Units Conditions Max ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ Power Supply Current 3.6 0.19 mA VCC d VO d 5.5V, Outputs Disabled 'ICC Increase in Power Supply Current 3.6 0.2 One Input at V CC 0.6V mA Other Inputs at V CC or GND (Note 8) Note 5: Applies to bushold versions only (74LVTH16373). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol (Note 9) (V) 25qC TA VCC Parameter Min Typ Conditions Units Max CL 500: 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 10) Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA Symbol Parameter VCC 40qC to 85qC, CL 50pF, RL 500: 3.3V r 0.3V Min Max VCC 2.7V Min Units Max tPHL Propagation Delay 1.5 3.9 1.5 4.3 tPLH Dn to On 1.5 3.8 1.5 4.2 tPHL Propagation Delay 1.9 4.2 1.9 4.4 tPLH LE to On 1.6 4.3 1.6 4.8 tPZL Output Enable Time tPZH tPLZ Output Disable Time tPHZ 1.3 4.3 1.3 4.9 1.0 4.3 1.0 5.1 1.5 4.7 1.5 4.8 2.0 5.0 2.0 5.4 ns ns ns ns tS Setup Time, Dn to LE 1.0 0.8 tH Hold Time, Dn to LE 1.0 1.1 ns tW LE Pulse Width 3.0 3.0 ns tOSHL Output to Output Skew (Note 11) tOSLH ns 1.0 1.0 1.0 1.0 ns Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 12) Conditions Typical Units CIN Symbol Input Capacitance Parameter VCC Open, VI 0V or VCC 4 pF COUT Output Capacitance VCC 3.0V, VO 0V or VCC 8 pF Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVT16373 • 74LVTH16373 DC Electrical Characteristics 74LVT16373 • 74LVTH16373 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary www.fairchildsemi.com 6 74LVT16373 • 74LVTH16373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com 74LVT16373 • 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8