PANASONIC MN3674

CCD Linear Image Sensor
MN3674
Color CCD Linear Image Sensor
with 512 Pixels for R and B Colors/1024 Pixels for G Color
■ Overview
The MN3674 is a high responsivity CCD color linear image sensor
with 512 pixels each for R and B and 1024 G pixels, and having low
dark output floating photodiodes in the photodetector region and
CCD analog shift registers for read out.
It can read a 64mm-width color document with a high quality and a
maximum pseudo resolution of 400dpi. In addition to being used as a
color sensor, this device can also be used as a black and white sensor
if only the G row is used, and in this case, it is possible to read a
64mm-width document with a full resolution of 400dpi. Since a one
line delay analog memory is built in so as to compensate for the
difference in the positions of reading out between the R, B rows and
the G row, the configuration of the signal processing circuit becomes
simpler.
■ Pin Assignments
1
NC
NC
OS1
DS1
VSS
øR
ø1
ø SG1
VSS
VSS
NC
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
■ Features
1024
• 2048 floating photodiodes and n-channel buried type CCD shift
registers for read out are integrated in a single chip.
• RGB primary colors type on chip color filters are used for color
separation.
• In order to compensate for the distance between the photodiode
rows for the R, B colors and the G color, the device has a built in
analog memory that can store the signals of one line of the R-B
colors row.
• All clock inputs can be driven by 5V CMOS logic.
• Use of photodiodes with a new structure has made the dark output
voltage very low.
• Large signal output of typically 0.8V at saturation can be obtained.
■ Application
• Color graphic read out in color image scanners, color fax machines,
etc.
(Top View)
C26
WDIP022-G-0470B
NC
NC
OS 2
DS 2
VDD
NC
ø2
ø SG2
øV
NC
NC
MN3674
CCD Linear Image Sensor
■ Block Diagram
OS2
20
DS 2
19
VDD
ø2
ø SG2
øV
18
16
15
14
1
12
1212
121212121212
121212121
1-line delay analog memory
B2 B4
B1 B3
3
R1 B1 R2
B31 D1 D3 G1 G2 G3
R
B
512 512
G G
1023 1024
12
1212
1
B1 to B32 : Black reference pixels
D1 to D8 : Dummy invalid pixels
D
OS1
B32 D2 D4
121212121212
D6 D8
D5 D7
121212121
6
7
DS1 VSS ø R
ø1
4
5
8
9
10
VSS VSS
ø SG1
■ Absolute Maximum Ratings (Ta=25˚C, VSS=0V)
Parameter
Power supply voltage
Input pulse voltage
Symbol
Rating
Unit
VDD
– 0.3 to + 15
– 0.3 to + 15
V
Operating temperature range
VI
Topr
Storage temperature range
Tstg
0 to + 60
V
˚C
–2 5 to + 85
˚C
■ Operating Conditions
• Voltage conditions (Ta=0 to + 60˚C, VSS=0V)
Parameter
Power supply voltage
Symbol
VDD
CCD shift register clock High level
Vø H
CCD shift register clock Low level
Vø L
Vertical transfer clock High level
VVH
Vertical transfer clock Low level
VVL
Shift gate clock High level
VSH
Shift gate clock Low level
VSL
Reset gate clock High level
VRH
Reset gate clock Low level
VRL
Condition
(ø1, ø2)
(øV)
(øSG1, øSG2)
(øR)
min
typ
max
Unit
11.4
4.5
12.0
5.0
13.0
VDD
V
0
0.2
0.5
4.5
5.0
VDD
0
4.5
0.2
5.0
0.5
VDD
V
V
V
V
V
0
0.2
5.0
0.5
VDD
V
4.5
0
0.2
0.5
V
V
MN3674
CCD Linear Image Sensor
• Timing conditions (without 1-line delay operation) (Ta=0 to + 60˚C)
min
typ
max
Unit
fC
See drive timing diagram (3) fC=1/2T
0.1
1.0
3.0
MHz
Reset clock frequency (=data rate)
fR
See drive timing diagram (3) fR=1/2T
0.1
1.0
3.0
MHz
Shift register clock rise time
t Cr
Shift register clock fall time
t Cf
0
0
20
20
50
50
ns
ns
0
0
15
15
50
50
ns
Parameter
Shift register clock frequency
Symbol
Condition
See drive timing diagram (3)
Vertical transfer clock rise time
t Vr
Vertical transfer clock fall time
t Vf
Vertical transfer clock pulse width
t VW
5
10
50
µs
Shift clock 1 rise time
Shift clock 1 fall time
t SG1r
0
15
50
ns
t SG1f
0
15
50
ns
ø SG1 and øV should be the same timing.
See drive timing diagram (1)
See drive timing diagram (1)
ns
Shift clock 1 set up time
t SG1s
t SG1w
0.5
5
1.0
10
2.0
50
µs
Shift clock 1 pulse width
Shift clock 2 rise time
t SG2r
0
15
50
Shift clock 2 fall time
t SG2f
0
15
50
ns
ns
1.0
2.0
µs
50
2
µs
µs
20
µs
Shift clock 2 set up time
t SG2s
Shift clock 2 pulse width
t SG2w
Shift clock 2 hold time
t SG2h
0.5
5
0
Reset clock rise time
t Rr
0
10
1
10
Reset clock fall time
t Rf
0
10
20
ns
ns
See drive timing diagram (1)
Reset clock set up time
t Rs
0.7T
—
—
ns
Reset clock pulse width
t Rw
100
200
—
ns
Reset clock hold time
t Rh
10
125
—
ns
See drive timing diagram (3)
• Timing conditions (during 1-line delay operation) (Ta=0 to + 60˚C)
min
typ
max
Unit
Shift register clock frequency
fC
See drive timing diagram (3) fC=1/2T
0.1
1.0
3.0
MHz
Reset clock frequency (=data rate)
fR
See drive timing diagram (3) fR=1/2T
0.1
1.0
3.0
MHz
Shift register clock rise time
t Cr
Shift register clock fall time
t Cf
0
0
20
20
50
50
ns
ns
0
0
15
15
50
50
ns
0.5
1.0
2.0
µs
5
10
50
µs
Parameter
Symbol
Condition
See drive timing diagram (3)
Vertical transfer clock rise time
t Vr
Vertical transfer clock fall time
t Vf
Vertical transfer clock set up time
t Vs
Vertical transfer clock pulse width
t Vw
Vertical transfer clock hold time
t Vh
0
1
2
µs
Shift clock 1 rise time
Shift clock 1 fall time
t SG1r
15
15
50
50
ns
t SG1f
0
0
Shift clock 1 pulse width
t SG1w
5
10
50
µs
Shift clock 2 rise time
t SG2r
0
15
50
ns
Shift clock 2 fall time
t SG2f
Shift clock 2 pulse width
t SG2w
15
1.0
10
ns
Shift clock 2 set up time
0
0.5
5
50
t SG2s
2.0
50
µs
µs
Reset clock rise time
t Rr
0
10
Reset clock fall time
t Rf
0
10
20
20
ns
ns
—
ns
ø SG1 and øV should be the same timing.
See drive timing diagram (2)
See drive timing diagram (2)
See drive timing diagram (2)
See drive timing diagram (3)
ns
ns
Reset clock set up time
t Rs
Reset clock pulse width
t Rw
100
200
—
ns
Reset clock hold time
t Rh
100
125
—
ns
0.7T
MN3674
CCD Linear Image Sensor
■ Electrical Characteristics
• Clock input capacitance (Ta=–20 to + 60˚C)
Parameter
CCD Shift register clock input capacitance
Symbol
C1 , C 2
Vertical transfer clock input capacitance
CV
Reset clock input capacitance
Shift clock input capacitance
C RS
Condition
VIN =5V
f=1MHz
C SG1, C SG2
min
typ
max
—
200
—
Unit
pF
—
100
—
pF
—
20
—
pF
—
100
—
pF
• DC characteristics
Parameter
Power supply current
Symbol
I DD
Condition
VDD = +12V
min
typ
max
Unit
—
10
20
mA
min
typ
max
Unit
—
50
—
ns
• AC characteristics
Parameter
Signal output delay time
Symbol
t OS
Condition
(a reference value)
■ Optical Characteristics
<Inspection conditions>
• Ta=25˚C, VDD=12V, VøH=VVH=VSH=VRH=5V (pulse), fC=fR=1MHz, Tint (accumulation time)=10ms
• Light source: Daylight fluorescent lamp with IR/UV cutting filter
• Optical system: A slit with an aperture dimensions of 20mm × 20mm is used at a distance of 200mm from the sensor (equivalent
to F=10).
• Load resistance = 100k Ohms
• These specifications apply to the 512 valid R and G pixels and the 1024 valid G pixels excluding the dummy pixels D1 to D8.
Parameter
Responsivity
Photo response non-uniformity
Saturation output voltage
Saturation exposure
Dark signal output voltage
Dark signal output non-uniformity
Shift register total transfer efficiency
Dynamic range
Symbol
min
typ
max
RR
Note 1
Condition
0.70
0.95
1.20
RG
Note 1
1.40
1.80
2.20
RB
PRNU
Note 1
Note 2
0.90
1.20
1.50
—
6
15
VSAT
Note 3
650
800
—
SER
Note 4
0.67
0.84
—
SEG
Note 4
0.36
0.44
—
SEB
0.53
0.67
—
VDRK1
Note 4
OS1, Dark condition, see Note 5
—
0.5
1.0
VDRK2
OS2, Dark condition, see Note 5
—
1.0
2.0
DSNU1
OS1, Dark condition, see Note 6
—
0.1
2.0
DSNU2
OS2, Dark condition, see Note 6
—
0.2
4.0
92
99
—
—
800
—
STTE
DR
Note 7
Unit
V/lx · s
%
mV
lx · s
mV
mV
%
Note 1) Responsivity (R)
This is the value obtained by dividing the average output voltage (V) of the all pixels by the exposure (lx· s).
The exposure (lx· s) is the product of the illumination intensity (lx) and the accumulation time (s).
Since the responsivity changes with the spectral distribution of the light source used, care should be taken when using a
light source other than the daylight type fluorescent lamp specified in the inspection conditions.
Note 2) Photo response non-uniformity (PRNU)
This is defined by the following equation where Xave is the average output voltage of the valid pixels of each of the colors
R, G, and B, and ∆x is the difference between the output voltage of the maximum (or minimum) output pixel and Xave,
when the photodetector region is illuminated with light of a uniform illumination intensity distribution.
x
×100 (%)
PRNU=
Xave
The incident light intensity shall be 50% of the standard saturation llight intensity.
MN3674
CCD Linear Image Sensor
■ Optical Characteristics (continued)
Note 3) Saturation output voltage:
This is the output voltage at the point beyond which it is not possible to maintain the linearity of the photoelectric
conversion characteristics as the exposure is increased. (The exposure at this point is called the saturation exposure.)
Note 4) Saturation Exposure (SE)
This is the exposure beyond which it is not possible to maintain the linearity of the output voltage as the exposure is
increased. When designing the equipment using these devices, make sure that the incident light exposure is set with
sufficient margin so that the CCD never gets saturated.
Note 5) Dark signal output voltage (VDRK)
This is defined as the average of the output from all the valid pixels in the dark condition at Ta=25˚C, Tint=10ms.
Normally, the dark signal output voltage gets doubled for every 8 to 10˚C increase in Ta and is proportional to Tint. The
dark signal output voltage (VDRK2) on the OS2 side will be larger than the dark signal output voltage (VDRK1) on the OS1
side because there is a delay memory on the OS2 side.
Note 6) Dark signal non-uniformity (DSNU)
This is defined as the difference between the maximum value among the output voltages of the all valid pixels at
Ta=25˚Cand Tint=10ms and VDRK.
VDRK
DSNU
Note 7) Dynamic range (DR)
This is defined by the following equation.
DR= VSAT
VDRK
Since the dark signal output voltage is proportional to the accumulation time, the dynamic range becomes wider when the
accumulation time is shorter.
■ Pin Descriptions
Pin No.
Symbol
1
NC
Pin name
2
NC
Non connection
3
OS1
Signal output 1
4
DS1
Compensation output 1
5
6
7
VSS
øR
ø1
Ground
Reset clock
CCD clock (Phase 1)
Condition
Non connection
8
øSG1
CCD shift register clock 1
9
VSS
Ground
10
VSS
11
NC
12
NC
13
NC
Ground
Non connection
Non connection
Non connection
14
øV
Vertical transfer clock
15
øSG2
Shift clock gate 2
16
ø2
CCD clock (Phase 2)
17
NC
18
19
20
VDD
DS 2
OS 2
21
NC
Green pixel output
Non connection
Power supply
Compensation output 2
Signal output 2
Non connection
Non connection
NC
22
Note) Connect all NC pins externally to VSS (GND).
Red and Blue pixel output
MN3674
CCD Linear Image Sensor
■ Construction of the Image Sensor
The MN3674 can be made up of the three sections of—a) photo detector region, b) CCD transfer region (shift register), and c)
output region.
a) Photo detector region
• The photoelectric conversion device consists of an 11µm floating photodiode and a 3µm channel stopper (isolation region) per
pixel, and such pixels are arranged in a linear row with a pitch of 14µm along the main scanning direction.
• The R-B row has 512 pixels each of the red and blue colors arranged alternatingly, and the G row has1024 pixels. The R-B row
and G row are placed with a spacing of one line (14µm) along the sideways scanning direction. The pixels of the G row are
displaced by half the pixel pitch (7µm) relative to the pixels of the R-B row in the main scanning direction.
1 1 2 2· · · · · · · 512 512
R B R B · · · · · · R B
G G G G · · · · · · G G
1 2 3 4 · · · · · · 1023 1024
14µm
14µm 14µm 14µm
• A one line analog delay memory is built in the chip in order to compensate for the difference in the positions of the R-B and G
rows in the sideways scanning direction.
• The photodetector window is a rectangle of dimensions 9µm (Horizontal) × 11µm (Vertical), and the areas other than the
photodetector window are optically shielded.
• The photodetector region has a total of 32 optically shielded (black reference) pixels that can be used as the black level reference,
with 16 pixels each for the R-B row and the G row.
b) CCD Transfer region (shift register)
• The signal charges obtained by photoelectric conversion are transferred to the CCD transfer regions of the respective colors
during the period when the shift gate (øSG) is at the High level. The signal charges transferred to this analog shift register are
successively transferred to the output region.
• A buried type CCD that can be driven by a two phase clock (ø1, ø2) is used for the analog shift register.
c) Output region
• The signal charge transferred to the output region is first sent to the charge to voltage conversion region where it is converted
into a voltage level corresponding to the amount of the signal charge, and then output after impedance conversion in a two stage
source follower amplifier.
• The DC level component not containing the optical signal and the clock noise component are output at the DS pin.
• It is possible to obtain a signal with a high S/N ratio with reduced clock noise, etc., by carrying out differential amplification of
the OS and DS outputs externally.
■ 1-Line delay analog memory
• In order to compensate for the distance between the photodiode rows for the R, B colors and the G color, the device has a built in
analog memory that can store the signals of one line. It is possible to select either to use or not use the delay memory by the
timings of the pulses øV, øSG1, and øSG2, and the two types of read out operation of 512 pixel operation and pseudo 1024 pixel
operation can be obtained accordingly.
(1) 512-pixel operation (no delay memory)
R B
G G
is taken as one pixel thereby making this device a 512-pixel color CCD.
(Each pixel of the color sensor will be a parallelogram of 28µm (horizontal) × 28µm (vertical).)
Sideways scanning
direction
(2) Pseudo 1024-pixel operaation (delay memory is used)
2
4
1022
A 1-line delay operation and interpolation signal processing
1
3
5 · · · · · · 1023
shown in the figure at left are made for the R-B colors.
R B R B R B ··· B R B
G G G G G G ··· G G G
1 2 3 4 5 6 · · · 1022 1024
1023
B R
R B
G
G
or
becomes one pixel during color sensing operation.
* Since the signal from the R-B row gets delayed, configure the optical system and mechanisms so that the sideways scanning is
done first from the R-B row. The R-B row and the G row of the same line will be read out due to the one line delay.
The weighted center of one color pixel can be considered to be at the position of the G pixel.
MN3674
CCD Linear Image Sensor
■ Timing Diagram
• I/O timing (1) (without 1-line delay operation)
ø SG1
øV
ø SG2
ø1
ø2
øR
0
1
2
DS1
OS1
17 18 19 20 21 22
B1
B29 B31
1041
1043 1045
1042 1044 1046
D1 D
3
G1 G2 G3
DS2
OS2
B2
D
G1022 G1024 5 D7
G1021 G1023
Blank feed level
B30 B32
D2 D
4
B1 to B32 : Black reference pixels R1 B1 R2
D1 to D8 : Dummy invalid pixels
B511 B512 D6 D8 Note) Repeat the transfer
R511 R512
pulses (ø1 , ø2) for
more than 1046
periods.
• I/O timing (2) (during 1-line delay operation)
ø SG1
øV
ø SG2
ø1
ø2
øR
0
DS1
OS1
1
2
17 18 19 20 21 22
B1
B29 B31
D1
D3
G1 G2 G 3
DS2
OS2
B2
1041
1043 1045
1042 1044 1046
D
G1022 G1024 5 D7
G1021 G1023
Blank feed level
B30 B32
D2 D
4
B1 to B32 : Black reference pixels R1 B1 R2
D1 to D8 : Dummy invalid pixels
* OS 2 outputs the previous line signal.
B 511 B 512 D6 D8
R 511 R 512
Note) Repeat the transfer
pulses (ø1 , ø2) for
more than 1046
periods.
MN3674
CCD Linear Image Sensor
• Drive timing (1) (read-out during no 1-line delay operation)
t SG1r
90%
ø SG1 50%
10%
t SG1f
t SG1w
t Vr
øV
t Vf
90%
50%
10%
t SG2r
t Vw
t SG2f
t SG2s
90%
50%
10%
t SG2w
ø SG2
ø1 50%
50%
t SG1s
t SG2h
Note) Make sure that the timings of ø SG and ø V are identical.
(If these are not identical, the accumulation time gets shifted and hence the data on
the same line cannot be obtained.)
• Drive timing (2) (read-out during 1-line delay operation)
t SG1r
ø SG1
t SG1f
t Vr
t SG2r
øV
ø SG2
90%
50%
10%
t SG1w
90%
50%
10%
t SG2f
t Vs
90%
50%
10%
ø1 50%
t Vf
t Vw
50%
t SG2s
t SG2w
t Vh
Note) Make sure that the timings of ø SG and ø V are identical.
(If these are not identical, the accumulation time gets shifted and hence the data on
the same line cannot be obtained.)
MN3674
CCD Linear Image Sensor
• Drive timing (3) (during repeated pattern)
90%
ø2
10%
t Cf
90%
50%
10%
t RW
t Cr
ø1
t RS
t Rh
90%
50%
10%
øR
t Rr
DS 1
(DS2)
t OS
t Rf
t Oh
2T
Reference level
OS 1
(OS 2)
50%
Effective signal
output period
■ Graphs and Characteristics
Spectral Response Characteristics
Relative responsivity (%)
100
80
Blue
60
Green
Red
40
20
0
400
500
600
700
Wavelength (nm)
800