Delta Sheet
DS7, 2002-09-16
QuadFALC®
Quad E1/T1/J1 Framer and Line Interface Component for Long and Short
Haul Applications
PEF 22554 HT Version 2.1
PEF 22554 E Version 2.1
Preface
This document describes the changes implemented in the QuadFALC® Version 2.1
related to the previous version 1.3. All functions not mentioned in this document remain
unchanged.
QuadFALC® Version 2.1 is a pin-compatible replacement of QuadFALC® Version 1.x.
Severe errata of QuadFALC® Version 1.3 are fixed. For more information please contact
your local sales office.
Organization of this Document
•
•
•
•
Chapter 1, Overview
Gives a general description of the product differences to its predecessor.
Chapter 2, Electrical Characteristics
Shows the differences in electrical behavior.
Chapter 2.4, Changed Supply Power Test Conditions T1/J1
Shows the mechanical dimensions of the new BGA package.
Chapter 3, Appendix
Shows a screenshot of the available software tool.
Related Documentation
Data Sheet PEF 22554 Version 2.1
Errata Sheet PEB 22554 Version 1.3
Addendum PEB 22554 Version 1.3
Revision History: Previous Version:
Preliminray Delta Sheet
DS 6, 2002-08-19
Major Changes:
“Functional Changes” on Page 2: Additional compare status field (CCR5.6)
“Changed DC Characteristics” on Page 26: Power Supply Currents & LOS Limits,
Delta Sheet
1/30
2002-09-16
QuadFALC®
PEF 22554
Overview
1
Overview
1.1
Functional Changes
The following function has been changed:
•
•
•
•
•
•
•
•
•
Version status in register VSTR changed from 02H to 05H
The boundary scan part number changed to 142, the boundary scan ID changed to
1. A new BSDL file is required.
The pulse mask programming (registers XPM(2:0)) has to be adjusted.
The MCLK reference clock programming (registers GCM(8:1)) has to be changed.
Variable master clock frequency function always enabled (GCM2(4) = 1).
New feature “automatic short haul/long haul adjustment” available by setting
LIM0.EQON = 1.
Additional automatic resynchronization mode for T1 (new bit: FMR2.7 = AFRS).
Additional compare status field (mode 2) in SS7 mode (new bit: CCR5.6 = CSF2).
2048 kHz synchronization interface according o ITU-T G.703 Sec. 13 (E1). For more
information refer to online Application Notes http://www.infineon.com/falc.
1.2
Correction of Errata
All severe errata of QuadFALC® Version 1.3 have been fixed. For more information
please contact your local sales office.
1.3
Modified Pin Functions
QuadFALC® Version 2.1 is pin-compatible with QuadFALC® Version 1.x. However,
some pin functions have been modified as detailed below:
•
•
No 5 V input levels are allowed due to technology restrictions (see Page 24).
The currently unused ("N.C.") pins on V1.3 devices are used as "Core Voltage
Supply" (VDDC) pins and "Voltage Selection" (VSEL) pin on V2.x devices. Due to the
new technology the core voltage is 1.8 V (see Chapter 1.5).
1.4
Package
In addition to the P-TQFP-144-8 package, a P-BGA-160-1 package with a ball pitch of
1.0 mm and a size of 15 mm × 15 mm is supported (see Figure 4).
1.5
Power Supply
The Version 2.1 device requires two supply voltages, 3.3 V and 1.8 V. For compatibility
reasons, it is possible to operate the device off a single 3.3 V supply, with the 1.8 V
Delta Sheet
2/30
2002-09-16
QuadFALC®
PEF 22554
Overview
supply being generated internally using an on-chip voltage regulator. In order to
minimize power consumption, it is also possible to operate the device using separate
external 3.3 V and 1.8 V supplies. Please note that the 1.8 V supply requires de-coupling
whether generated on-chip or externally. Supply voltage selection is done by using pin
VSEL. See Figure 1 and Figure 2.
•
3.3 V
3.3 V
VDD
VDDX
VDDR
VDDP
VDDC
VDDC
VDD, VDDP, VDDX, VDDR > VDDC
(can be
left open)
QuadFALC®
VSS
VSSP
VSSX
VSSR
must always be guaranteed,
also during power on and
power down sequences.
Figure 1
VSEL
F0248
Single Voltage Supply
•
1.8 V
3.3 V
VDD
VDDX
VDDR
VDDP
VDDC
VDDC
VDD, VDDP, VDDX, VDDR > VDDC
QuadFALC®
VSS
VSSP
VSSX
VSSR
must always be guaranteed,
also during power on and
power down sequences.
Figure 2
Delta Sheet
VSEL
F0249
Dual Voltage Supply
3/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Pinout
VSSX
D15
D14
D13
D12
D11
VSS
VDD
D10
D9
D8
D7
D6
D5
D4
D3
VSS
VDD
D2
D1
D0
BHE/BLE
CS
RD/DS
WR/RW
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VSSX
1.6
108
109
104
100
96
92
88
84
80
76
73
72
112
68
116
64
120
60
124
QuadFALC®
PEF 22554 V2.1
128
56
52
132
48
136
44
140
40
144
1
4
8
12
16
20
24
28
32
37
36
VSSX
XDI1
SXLKX1
RPA1
RPB1
RPC1
RPD1
SCLKR1
RDO1
VDD
VSS
RDO2
SCLKR2
RPA2
RPB2
RPC2
RPD2
XDI2
SCLKX2
XDI3
SCLKX3
RPA3
RPB3
RPC3
RPD3
SCLKR3
RDO3
VDD
VSS
RDO4
SCLKR4
RPA4
RPB4
RPC4
RPD4
VSSX
XL1_1/XDOP1/XOID1
VDDX
XL2_1/XDON1/XFM1
TDI
TDO
VDDR
RL1_1/RDIP1/ROID1
RL2_1/RDIN1/RCLKI1
VSSR
VDDC
RCLK1
XPA1
XPB1
XPC1
XPD1
VDDP
VSS
XPA2
XPB2
XPC2
XPD2
RCLK2
TRS
VDDP
MCLK
VSEL
VSSP
VSSR
RL2_2/RDIN2/RCLKI2
RL1_2/RDIP2/ROID2
VDDR
TCK
TMS
XL2_2/XDON2/XFM2
VDDX
XL1_2/XDOP2/XOID2
Figure 3
Delta Sheet
XL1_4/XDOP4/XOID4
VDDX
XL2_4/XDON4/XFM4
SEC/FSC
IM
VDDR
RL1_4/RDIP4/ROID4
RL2_4/RDIN4/RCLKI4
VSSR
VDDC
ALE
RCLK4
XPD4
XPC4
XPB4
XPA4
VSS
VDD
XPD3
XPC3
XPB3
XPA3
SCLKX4
XDI4
SYNC
RCLK3
RES
VSSR
RL2_3/RDIN3/RCLKI3
RL1_3/RDIP3/ROID3
VDDR
INT
DBW
XL2_3/XDON3/XFM3
VDDX
XL1_3/XDOP3/XOID3
F0213
Pin Configuration P-TQFP-144-8, Top View
4/30
2002-09-16
QuadFALC®
PEF 22554
Overview
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XL1_2 XL2_2 VDDR VSSR RL1_2 RL2_2 RL2_1 RL1_1 VSSR VDDR XL2_1 XL1_1
A
B
VSSX
VSSX
XDI1
MCLK
XPC2
TRS
XPD2
VDD
XPA1
VDDP
XPB1
D15
VSSX
C
VDDX VDDX
D
RPC1
SCLKX
1
TCK
VSSP
VDDP
XPA2
XPB2
XPC1
VDDC
TDO
D14
VDDX VDDX
RPA1
RPB1
RPD1
TMS
VSS
XPD1 RCLK1
TDI
D12
D13
D11
E
RDO1
SCLKR
1
VDD
VDD
VSS
VDD
VDD
D10
F
RDO2
VSS
SCLKR
RPA2
2
D9
D7
D8
D6
G
RPC2
RPB2
SCLKX
RPD2
2
H
XDI3
SCLKX
3
XDI2
RPA3
J
RPB3
RPD3
RPC3
K
RDO3
VSS
L
VSEL RCLK2
VSSX
VSS
VSS
D5
VDD
D4
D3
VSS
VSS
D2
VSS
D0
D1
SCLKR
3
BHE/
BLE
CS
W R/
RW
RD/DS
VDD
RDO4
A9
A8
A6
A7
SCLKR
RPB4
4
RPA4
DBW
A2
A4
M
VDDX VDDX
RPC4
INT
RES
N
VSSX
RPD4
XDI4
XPC3
P
VSSX
XPD3
XPB4
ALE
SEC/
FSC
A5
A3
SCLKX
4
VDD
VDD
XPD4
VDDC
IM
A1
VDDX VDDX
SYNC
XPB3
XPA4 RCLK4
VSS
XPC4
A0
VSSX
RCLK3 XPA3
VSSX
XL1_3 XL2_3 VDDR VSSR RL1_3 RL2_3 RL2_4 RL1_4 VSSR VDDR XL2_4 XL1_4
F0213_2
Figure 4
Delta Sheet
Ball Layout P-BGA-160-1, Top View
5/30
2002-09-16
QuadFALC®
PEF 22554
Overview
14
A
13
12
11
10
9
8
7
6
5
4
3
2
1
XL1_1 XL2_1 VDDR VSSR RL1_1 RL2_1 RL2_2 RL1_2 VSSR VDDR XL2_2 XL1_2
B
VSSX
VSSX
D15
XPB1
VDDP
XPA1
VDD
XPD2
TRS
XPC2
MCLK
C
VDDX VDDX
D14
TDO
VDDC
XPC1
XPB2
XPA2
VDDP
VSSP
TCK
RCLK1 XPD1
VSS
TMS
RPD1
RPB1
XDI1
VSSX
SCLKX
VDDX VDDX
1
D
D11
D13
D12
TDI
E
D10
VDD
VDD
VSS
VDD
VDD
F
D6
D8
D7
D9
RPA2
SCLKR
2
G
D3
D4
VDD
D5
VSS
VSS
RPD2
SCLKX
RPB2
2
H
D1
D0
VSS
D2
VSS
VSS
RPA3
J
RD/DS
W R/
RW
CS
BHE/
BLE
K
A7
A6
A8
A9
L
A4
A2
A3
A5
SEC/
FSC
ALE
XPB4
XPD3
XPD4
VDD
VDD
SCLKX
4
RES
RCLK4 XPA4
XPB3
SYNC
XPC3
VDDX VDDX
A1
IM
VDDC
N
VSSX
A0
XPC4
VSS
P
XDI2
SCLKR
RPC3
3
M
VSSX
RCLK2 VSEL
VSSX
RPA1
RPC1
SCLKR
RDO1
1
VSS
RDO2
RPC2
SCLKX
3
XDI3
RPD3
RPB3
RDO4
VDD
VSS
RDO3
XPA3 RCLK3 DBW
RPA4
RPB4
SCLKR
4
INT
RPC4
VDDX VDDX
XDI4
RPD4
VSSX
VSSX
XL1_4 XL2_4 VDDR VSSR RL1_4 RL2_4 RL2_3 RL1_3 VSSR VDDR XL2_3 XL1_3
F0213_3
Figure 5
Delta Sheet
Ball Layout P-BGA-160-1, Bottom View
6/30
2002-09-16
QuadFALC®
PEF 22554
Overview
1.7
Pin Description
Table 1
Additional Pin Functions
VSEL
I + PU
Voltage Select
Enables the internal voltage regulator for 3.3 V-only operation
mode if connected to VDD (recommended) or left open.
Disables the internal voltage regulator for dual power supply mode
if connected to VSS.
VDDC
S
Positive Power Supply
for the digital core (1.8 V)
These pins can either be positive power supply input or output
depending on the VSEL input condition.
If the VSEL pin is connected to VSS, these pins are inputs and
must both be connected to the same 1.8 V power supply and
require decoupling.
If the VSEL pin is connected to VDD (3.3 V), these pins will both be
1.8 V power supply outputs and must be decoupled to VSS.
Attention: These pins must not be used to supply external
devices.
VDDP
S
Positive Power Supply for the analog PLL (3.3 V)
VSSP
S
Power Supply Ground for the analog PLL (0 V)
A short pin list of the BGA package is given in Table 2. For a complete signal description
refer to the QuadFALC® V2.1 Preliminary Data Sheet.
Table 2
BGA Pin Assignment
Ball No.
BGA
Pin No.
TQFP
Symbol
Input(I)
Function
Output(O)
Supply(S)
N12
74
A0
I + PU
Address Bus
M12
75
A1
I + PU
Address Bus
L13
76
A2
I + PU
Address Bus
L12
77
A3
I + PU
Address Bus
L14
78
A4
I + PU
Address Bus
L11
79
A5
I + PU
Address Bus
K13
80
A6
I + PU
Address Bus
K14
81
A7
I + PU
Address Bus
Delta Sheet
7/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Table 2
BGA Pin Assignment (cont’d)
Ball No.
BGA
Pin No.
TQFP
Symbol
Input(I)
Function
Output(O)
Supply(S)
K12
82
A8
I + PU
Address Bus
K11
83
A9
I + PU
Address Bus
B12
107
D15
I/O + PU
Data Bus
C12
106
D14
I/O + PU
Data Bus
D13
105
D13
I/O + PU
Data Bus
D12
104
D12
I/O + PU
Data Bus
D14
103
D11
I/O + PU
Data Bus
E14
100
D10
I/O + PU
Data Bus
F11
99
D9
I/O + PU
Data Bus
F13
98
D8
I/O + PU
Data Bus
F12
97
D7
I/O + PU
Data Bus
F14
96
D6
I/O + PU
Data Bus
G11
95
D5
I/O + PU
Data Bus
G13
94
D4
I/O + PU
Data Bus
G14
93
D3
I/O + PU
Data Bus
H11
90
D2
I/O + PU
Data Bus
H14
89
D1
I/O + PU
Data Bus
H13
88
D0
I/O + PU
Data Bus
L9
62
ALE
I + PU
Address Latch Enable
J14
85
RD/DS
I + PU
Read Enable
Data Strobe
J13
84
WR/RW
I + PU
Write Enable
Read/Write Enable
L4
40
DBW
I + PU
Data Bus Width
M11
68
IM
I + PU
Interface Mode
J12
86
CS
I + PU
Chip Select
J11
87
BHE/BLE
I + PU
Bus High Enable
Bus Low Enable
M4
41
INT
O/oD
Interrupt Request
A9
115
RL1.1
I (analog)
Line Receiver 1, Channel 1
Delta Sheet
8/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Table 2
BGA Pin Assignment (cont’d)
Ball No.
BGA
Pin No.
TQFP
Symbol
Input(I)
Function
Output(O)
Supply(S)
A6
138
RL1.2
I (analog)
Line Receiver 1, Channel 2
P6
43
RL1.3
I (analog)
Line Receiver 1, Channel 3
P9
66
RL1.4
I (analog)
Line Receiver 1, Channel 4
A8
116
RL2.1
I (analog)
Line Receiver 2, Channel 1
A7
137
RL2.2
I (analog)
Line Receiver 2, Channel 2
P7
44
RL2.3
I (analog)
Line Receiver 2, Channel 3
P8
65
RL2.4
I (analog)
Line Receiver 2, Channel 4
A13
109
XL1.1
O (analog) Transmit Line 1, Channel 1
A2
144
XL1.2
O (analog) Transmit Line 1, Channel 2
P2
37
XL1.3
O (analog) Transmit Line 1, Channel 3
P13
72
XL1.4
O (analog) Transmit Line 1, Channel 4
A12
111
XL2.1
O (analog) Transmit Line 2, Channel 1
A3
142
XL2.2
O (analog) Transmit Line 2, Channel 2
P3
39
XL2.3
O (analog) Transmit Line 2, Channel 3
P12
70
XL2.4
O (analog) Transmit Line 2, Channel 4
B4
133
MCLK
I
Master Clock
N6
48
SYNC
I + PU
Clock Synchronization of DCO-R
L10
69
SEC/FSC
I/O + PU
One-Second Timer Input
One-Second Timer Output
8 kHz Frame Synchronization Output
D10
119
RCLK1
O + PU
Receive Clock, Channel 1
D7
130
RCLK2
O + PU
Receive Clock, Channel 2
L5
47
RCLK3
O + PU
Receive Clock, Channel 3
N9
61
RCLK4
O + PU
Receive Clock, Channel 4
E1
9
RDO1
O
Receive Data Out, Channel 1
F1
12
RDO2
O
Receive Data Out, Channel 2
K1
27
RDO3
O
Receive Data Out, Channel 3
K4
30
RDO4
O
Receive Data Out, Channel 4
E2
8
SCLKR1
I/O + PU
System Clock Receive, Ch. 1
Delta Sheet
9/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Table 2
BGA Pin Assignment (cont’d)
Ball No.
BGA
Pin No.
TQFP
Symbol
Input(I)
Function
Output(O)
Supply(S)
F3
13
SCLKR2
I/O + PU
System Clock Receive, Ch. 2
J4
26
SCLKR3
I/O + PU
System Clock Receive, Ch. 3
L1
31
SCLKR4
I/O + PU
System Clock Receive, Ch. 4
D2
4
RPA1
I/O + PU
Receive Multifunction Port A, Ch. 1
F4
14
RPA2
I/O + PU
Receive Multifunction Port A, Ch. 2
H4
22
RPA3
I/O + PU
Receive Multifunction Port A, Ch. 3
L3
32
RPA4
I/O + PU
Receive Multifunction Port A, Ch. 4
D3
5
RPB1
I/O + PU
Receive Multifunction Port B, Ch. 1
G2
15
RPB2
I/O + PU
Receive Multifunction Port B, Ch. 2
J1
23
RPB3
I/O + PU
Receive Multifunction Port B, Ch. 3
L2
33
RPB4
I/O + PU
Receive Multifunction Port B, Ch. 4
D1
6
RPC1
I/O + PU
Receive Multifunction Port C, Ch. 1
G1
16
RPC2
I/O + PU
Receive Multifunction Port C, Ch. 2
J3
24
RPC3
I/O + PU
Receive Multifunction Port C, Ch. 3
M3
34
RPC4
I/O + PU
Receive Multifunction Port C, Ch. 4
D4
7
RPD1
I/O + PU
Receive Multifunction Port D, Ch. 1
G4
17
RPD2
I/O + PU
Receive Multifunction Port D, Ch. 2
J2
25
RPD3
I/O + PU
Receive Multifunction Port D, Ch. 3
N3
35
RPD4
I/O + PU
Receive Multifunction Port D, Ch. 4
B3
2
XDI1
I
Transmit Data In, Channel 1
H3
18
XDI2
I
Transmit Data In, Channel 2
H1
20
XDI3
I
Transmit Data In, Channel 3
N4
49
XDI4
I
Transmit Data In, Channel 4
C3
3
SCLKX1
I/O + PU
System Clock Transmit, Ch. 1
G3
19
SCLKX2
I/O + PU
System Clock Transmit, Ch. 2
H2
21
SCLKX3
I/O + PU
System Clock Transmit, Ch. 3
M6
50
SCLKX4
I/O + PU
System Clock Transmit, Ch. 4
B9
120
XPA1
I/O + PU
Transmit Multifunction Port A, Ch. 1
C7
126
XPA2
I/O + PU
Transmit Multifunction Port A, Ch. 2
Delta Sheet
10/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Table 2
BGA Pin Assignment (cont’d)
Ball No.
BGA
Pin No.
TQFP
Symbol
Input(I)
Function
Output(O)
Supply(S)
L6
51
XPA3
I/O + PU
Transmit Multifunction Port A, Ch. 3
N8
57
XPA4
I/O + PU
Transmit Multifunction Port A, Ch. 4
B11
121
XPB1
I/O + PU
Transmit Multifunction Port B, Ch. 1
C8
127
XPB2
I/O + PU
Transmit Multifunction Port B, Ch. 2
N7
52
XPB3
I/O + PU
Transmit Multifunction Port B, Ch. 3
L8
58
XPB4
I/O + PU
Transmit Multifunction Port B, Ch. 4
C9
122
XPC1
I/O + PU
Transmit Multifunction Port C, Ch. 1
B5
128
XPC2
I/O + PU
Transmit Multifunction Port C, Ch. 2
N5
53
XPC3
I/O + PU
Transmit Multifunction Port C, Ch. 3
N11
59
XPC4
I/O + PU
Transmit Multifunction Port C, Ch. 4
D9
123
XPD1
I/O + PU
Transmit Multifunction Port D, Ch. 1
B7
129
XPD2
I/O + PU
Transmit Multifunction Port D, Ch. 2
L7
54
XPD3
I/O + PU
Transmit Multifunction Port D, Ch. 3
M9
60
XPD4
I/O + PU
Transmit Multifunction Port D, Ch. 4
B6
131
TRS
I + PU
Test Reset for Boundary Scan
D11
112
TDI
I + PU
Test Data Input
D5
141
TMS
I + PU
Test Mode Select
C4
140
TCK
I + PU
Test Clock
C11
113
TDO
O
Test Data Output
M5
46
RES
I
Reset
D6
134
VSEL
I + PU
Voltage Select
A11
114
VDDR
S
Power Supply for analog receiver 1
A4
139
VDDR
S
Power Supply for analog receiver 2
P4
42
VDDR
S
Power Supply for analog receiver 3
P11
67
VDDR
S
Power Supply for analog receiver 4
A10
117
VSSR
S
Ground for analog receiver 1
A5
136
VSSR
S
Ground for analog receiver 2
P5
45
VSSR
S
Ground for analog receiver 3
P10
64
VSSR
S
Ground for analog receiver 4
Delta Sheet
11/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Table 2
Ball No.
BGA
BGA Pin Assignment (cont’d)
Symbol
Input(I)
Function
Output(O)
Supply(S)
C13, C14 110
VDDX
S
Power Supply for analog transmitter 1
C1, C2
143
VDDX
S
Power Supply for analog transmitter 2
M1, M2
38
VDDX
S
Power Supply for analog transmitter 3
M13,
M14
71
VDDX
S
Power Supply for analog transmitter 4
B13, B14 108
VSSX
S
Ground for analog transmitter 1
B1, B2
1
VSSX
S
Ground for analog transmitter 2
N1, N2
36
VSSX
S
Ground for analog transmitter 3
N13, N14 73
VSSX
S
Ground for analog transmitter 4
E3, E4
10
VDD
S
Pad Power Supply 3.3 V
K3
28
VDD
S
Pad Power Supply 3.3 V
M7, M8
55
VDD
S
Pad Power Supply 3.3 V
G12
91
VDD
S
Pad Power Supply 3.3 V
E12, E13 101
VDD
S
Pad Power Supply 3.3 V
B8
---
VDD
S
Pad Power Supply 3.3 V
B10
124
VDDP
S
Analog PLL Power Supply 3.3 V
C6
132
VDDP
S
Analog PLL Power Supply 3.3 V
M10
63
VDDC
S
Core Power Supply 1.8 V
C10
118
VDDC
S
Core Power Supply 1.8 V
C5
135
VSSP
S
Ground for analog PLL
F2
11
VSS
S
Ground
K2
29
VSS
S
Ground
N10
56
VSS
S
Ground
H12
92
VSS
S
Ground
E11
102
VSS
S
Ground
D8
125
VSS
S
Ground
G7, G8,
H7, H8
---
VSS
S
Ground
Delta Sheet
Pin No.
TQFP
12/30
2002-09-16
QuadFALC®
PEF 22554
Overview
1.8
Decoupling Capacitors
To gain best performance, the following values are recommended for the external
decoupling capacitors between VDDC and VSS. There is one decoupling capacitor
required on each VDDC pin.
Table 3
Decoupling Capacitor Parameters
Parameter
Value
Capacitance
470 nF ± 20 %, alternatively: 2 x 220 nF ± 20 %
Capacitor material
ceramic, type X7R or compatible
ESR
< 30 mΩ
Loop inductance (LL)
between VDDC, capacitor
and next VSS pin
< 10 nH
118
VDDC
VDDC 63
LL
LL
125
Figure 6
Delta Sheet
VDD
VSS
VSS
VDD
56
F0252
Decoupling Capacitor Placement
13/30
2002-09-16
QuadFALC®
PEF 22554
Overview
1.9
Operation Description E1/T1/J1
Note: Write access to unused register addresses: should be avoided, or set to “00” hex
in address range. up to xA9; must be avoided in address range above xA9 if not
defined elsewhere (for example in Table 4).
To achieve optimum receiver sensitivity in E1 long haul mode (> 38 dB) the following
sequence must be run:
Table 4
Receive Line Interface Initialization (E1)
Address
Data
BBH
17H
BCH
55H
BBH
97H
BBH
11H
BCH
AAH
BBH
91H
BBH
12H
BCH
55H
BBH
92H
BBH
0CH
BCH
00H
BBH
8CH
Note: Sequence must be repeated whenever receiver reset (CMDR.RRES) of arbitrary
channel was performed (e.g. after setting bit LIM1.EQON).
Delta Sheet
14/30
2002-09-16
QuadFALC®
PEF 22554
Overview
1.10
Device Marking Pattern
The sales code changed from PEB 22554 Version 1.3 to PEF 22554 Version 2.1.
The new marking pattern is:
Engineering
Samples
PTQFP:
Final Devices
PTQFP:
PEF 22554 HT
V2.1
QuadFALC
ES A21
PEF 22554 HT
V2.1
QuadFALC
A21
Engineering
Samples
PBGA:
Final Devices
PBGA:
PEF 22554 E
V2.1
QuadFALC
ES A21
PEF 22554 E
V2.1
QuadFALC
A21
F0200
Figure 7
Delta Sheet
Marking Pattern
15/30
2002-09-16
QuadFALC®
PEF 22554
Overview
1.11
Flexible Clock Mode Settings
The register settings for flexible master clock can be calculated as follows. For some
standard frequencies see Table 5 below. The variables used in these calculations are
located in registers GCM1 to GCM8.
1. PLL_M and PLL_N must fulfill the equations:
a.
for PLL_M = 0 to 31:
f MCLK
f pdref = ---------------------------PLL_M + 1
b.
for PLL_N = 25 to 63:
1.0 MHz ≤ f pdref ≤ 6.0 MHz
for PLL_N = 0 to 24:
5.0 MHz ≤ f pdref ≤ 15.0 MHz
Attention: To decrease sensitivity of PLL to noise on VDDP and/or VSSP adjust
fpdref as high as possible.
c.
4 × ( PLL_N + 1 )
260 MHz ≤ f MCLK × ----------------------------------------- ≤ 395.26 MHz
PLL_M + 1
(as high as possible within this range)
2. Selection of dividing mode to best fulfill:
4 × ( PLL_N + 1 )
f outE1 = f MCLK × ----------------------------------------------------------------------------------------------------- ≅ 2 × 16.384 MHz
æ PHSN_E1 + PHSX_E1
-------------------------ö × ( PLL_M + 1 )
è
ø
6
4 × ( PLL_N + 1 )
f outT1 = f MCLK × ----------------------------------------------------------------------------------------------------- ≅ 2 × 12.352 MHz
æ PHSN_T1 + PHSX_T1
-------------------------ö × ( PLL_M + 1 )
è
ø
6
Though the target frequency might not be met directly, the dividing mode has to be
selected to reach a frequency which is as near as possible to the target frequency.
Delta Sheet
16/30
2002-09-16
QuadFALC®
PEF 22554
Overview
PHSN_E1, PHSN_T1: 1 to 15;
PHSX_E1, PHSX_T1: 0 to 5
3. Calculation of correction value for frequency mismatch correction:
f MCLK
PHSX_E1 4 × ( PLL_N + 1 )
PHD_E1 = 12288 × æ PHSN_E1 + -------------------------ö – ----------------------------------------- × --------------------------------------è
ø
2 × 16.384 MHz
6
PLL_M + 1
f MCLK
PHSX_T1 4 × ( PLL_N + 1 )
PHD_T1 = 12288 × æ PHSN_T1 + -------------------------ö – ----------------------------------------- × --------------------------------------è
ø
6
2 × 12.352 MHz
PLL_M + 1
The result of these equations will be in the range of -2048...+2047. Negative values are
represented in 2s-complement format (e.g., -2000D = 830H ; +2000D = 7D0H).
To achieve optimal QuadFALC® performance values < -1023 and > +1023 must be
applied. Negative values are favored.
Table 5
Clock Mode Register Settings for E1 and T1/J1
fMCLK[MHz]
GCM1
GCM2
GCM3
GCM4
GCM5
GCM6
GCM7
GCM8
1.544
00
15
00
08
00
3F
9C
DF
2.048
00
18
FB
0B
00
2F
DB
DF
8.192
00
18
FB
0B
00
0B
DB
DF
10.000
40
1B
3D
0A
00
07
C9
DC
12.352
00
19
00
08
01
0A
98
DA
16.384
00
18
FB
0B
01
0B
DB
DF
Note: All values are given in hexadecimal notation.
To support the necessary calculations, an easy-to-use PC tool is available for free (see
Page 29 for details).
Delta Sheet
17/30
2002-09-16
QuadFALC®
PEF 22554
Overview
1.12
Register Modifications
Framer Mode Register 2 (Read/Write)
Value after reset: 00H
7
FMR2
AFRS
AFRS
0
MCSP
SSP
DAIS
SAIS
PLB
AXRA
EXZE
(x1E)
Automatic Force Resynchronization
Search for next candidate automatically, if multiple candidates are
present and the current candidate is incorrect.
(This bit is available in T1/J1 F12 mode only).
Line Interface Mode 2 (Read/Write)
Value after reset: 20H
7
LIM2
LBO2
LBO(2:0)
0
LBO1
SLT1
SLT0
SCF
ELT
LOS1
(x3A)
Line Build-Out
To meet the line build-out defined by ANSI T1.403 registers XPM(2:0)
should be programmed as follows:
00
0 dB
01
-7.5 dB
→ XPM(2:0) = 00H, 01H, 8CH
10
-15 dB
→ XPM(2:0) = 01H, 11H, 8CH
11
-22.5 dB → XPM(2:0) = 00H, 01H, 07H
(This bits are available in T1/J1 mode only).
Delta Sheet
18/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Line Interface Mode 0 (Read/Write)
Value after reset: 00H
7
LIM0
XFB
0
XDOS
0
0
EQON
RLM
LL
MAS
(x36)
By setting EQON = 1 the QuadFALC® is able to adjust short haul or
long haul mode automatically. After changing the value of EQON a
receiver reset (CMDR.RRES) is required. For E1 mode please note
sequence as specified in Table 4 on Page 14.
EQON
Note: When using EQON = 1 together with RLM = 1, LIM1.RIL(2:0) must be set to 001B.
Line Interface Mode 1 (Read/Write)
Value after reset: 00H
7
LIM1
CLOS
DRS
0
RIL2
RIL1
RIL0
JATT
RL
DRS
(x37)
Dual Rail Select
Note: LIM0.EQON must be set to 0 when DRS = 1
Version Status Register (Read)
7
VSTR
0
VN(7:0)
0
0
0
0
0
1
0
1
(4A)
Version Number of Chip
05H…Version 2.1
Port Configuration 5 (Read/Write)
Value after reset: 20H
7
0
PC5
PC5.2
CXMFS
0
CSRP
CRP
(x84)
reserved
Must be cleared.
Delta Sheet
19/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Common Configuration Register 5 (Read/Write)
Value after reset: 00H
7
CCR5
1)
0
CSF2
SUET
CSF
AFX
CR1)
EPR1)
(x8D)
T1 mode only
CSF2
Compare Status Field - Mode 2
If the status fields of consecutive LSSUs are equal, only the first is
stored and every following is ignored.
Exception: if identical FISUs are received, two of them are stored,
0
Compare disabled.
1
Compare enabled.
Note: Only valid if SS7 is selected
Global Clock Mode Register 2 (Read/Write)
Value after reset: 00H
7
GCM2
0
0
0
0
1
PHD_E1 PHD_E1 PHD_E1 PHD_E1
11
10
9
8
(93)
GCM2(7:5)
removed bits
GCM2(4)
must be set to 1, details for calculate of the remaining GCM values
can be found in Chapter 1.11.
Global Clock Mode Register 4 (Read/Write)
Value after reset: 00H
7
GCM4
GCM4(7:5)
Delta Sheet
0
0
0
0
0
PHD_T1 PHD_T1 PHD_T1 PHD_T1
11
10
9
8
(95)
removed bits
20/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Global Clock Mode Register 5 (Read/Write)
Value after reset: 00H
7
GCM5
0
GCM5.7
0
0
0
PLLM_4 PLLM_3 PLLM_2 PLL_M1 PLL_M0
(96)
removed bit, to be set to 0
Global Clock Mode Register 6 (Read/Write)
Value after reset: 00H
7
GCM6
0
GCM6.5
0
0
PLLN_5 PLLN_4 PLLN_3 PLLN_2 PLL_N1 PLL_N0
(97)
added bit
Attention: Write operations to GCM5 and/or GCM6 register must be performed
before any port configuration is done. If this is not possible set
LIM0.DRS (if not set) of every channel seperately before writing to these
registers and reset LiM0.DRS (if it was not set before) after these write
operations.
Global Clock Mode Register 7 (Read/Write)
Value after reset: 00H
7
GCM7
1
0
PHSX_
E12
PHSX_
E11
PHSX_
E10
GCM7.7
added bit, to be set to 1
PHSX_E1(2:0)
added bits
PHSN_E1(3:0)
added bits
Delta Sheet
PHSN_
E13
21/30
PHSN_
E12
PHSN_
E11
PHSN_
E10
(98)
2002-09-16
QuadFALC®
PEF 22554
Overview
Global Clock Mode Register 8 (Read/Write)
Value after reset: 00H
7
GCM8
0
1
PHSX_
T12
PHSX_
T11
PHSX_
T10
GCM8.7
added bit, to be set to 1
PHSX_T1(2:0)
added bits
PHSN_T1(3:0)
added bits
PHSN_
T13
PHSN_
T12
PHSN_
T11
PHSN_
T10
(99)
Channel Interrupt Status Register (Read)
7
CIS
0
PLLL
CIS.7
0
0
0
GIS4
GIS3
GIS2
GIS1
(6F)
PLL Locked Status
1 if PLL is locked, 0 if PLL is unlocked
Note:This bit is only updated when a clock is available on pin MCLK
Transmit Pulse Mask 2…0 (Read/Write)
Value after RESET: 7BH, 03H, 40H
7
0
XPM0
XP12
XP11
XP10
XP04
XP03
XP02
XP01
XP00
(x26)
XPM1
XP30
XP24
XP23
XP22
XP21
XP20
XP14
XP13
(x27)
XPM2
XLLP
XLT
DAXLT
XP34
XP33
XP32
XP31
(x28)
XP24XP20
XP34XP30
C
Table 6
Range in
m
Pulse Shaper Programming (T1/J1)1)
Range in
ft.
XPM0
XPM1
XPM2
XP04- XP14XP00 XP10
hexadecimal
decimal
0 to 40
0 to 133
95
16
01
21
20
5
2
40 to 81
133 to 266 B6
9E
01
22
21
7
3
Delta Sheet
22/30
2002-09-16
QuadFALC®
PEF 22554
Overview
Table 6
Pulse Shaper Programming (T1/J1)1)
Range in
m
Range in
ft.
81 to 122
XPM1
XPM2
XP04- XP14XP00 XP10
XP24XP20
XP34XP30
266 to 399 D9
26
01
25
22
9
2
122 to 162 399 to 533 FC
36
01
28
23
13
2
162 to 200 533 to 655 3F
CB
01
31
28
18
3
1)
XPM0
Register values of V1.3 may also be used. For optimum results V2.1 values must be applied
Example for E1 120 Ω interface:
Programming values for XPM(2:0): 00H, 03H, 9CH.
XPM0(4:0): 1CH or 28 decimal
XPM1(4:0): 1CH or 28 decimal
XPM2(4:0): 00H
XPM3(4:0): 00H
Delta Sheet
23/30
2002-09-16
QuadFALC®
PEF 22554
Electrical Characteristics
2
Electrical Characteristics
Due to the change of silicon technology some of the electrical characteristics have
changed.
2.1
Absolute Maximum Ratings
Parameter
Ambient temperature under bias
Storage temperature
IC supply voltage (pads, digital)
IC supply voltage (core, digital)
IC supply voltage PLL (analog)
IC supply voltage receive (analog)
IC supply voltage transmit (analog)
Voltage on any pin with respect to
ground1)
Symbol
TA
Tstg
VDD
VDDC
VDDP
VDDR
VDDX
VS
Limit Values
Unit
min.
max.
– 40
85
°C
– 65
125
°C
– 0.3
3.60
V
– 0.3
1.98
V
– 0.3
3.60
V
– 0.3
3.60
V
– 0.3
3.60
V
– 0.3
3.60
V
ESD robustness
HBM: 1.5 kΩ, 100 pF2)
CDM 3)
VESD,HBM -
2000
V
VESD,CDM -
500
V
Moisture level 3
---
2254)
°C
2455)
°C
1)
Except VDDC
2)
According to JEDEC standard EIA/JESD22-A114-B-1997.
3)
According to EOS/ESD Assn.Standard DS5.3-1993
4)
According to IPS J-STD 020
5)
According to IFX internal standard
Attention: If the 1.8 V power supply is externally driven on VDDC, the voltage on
this pin must never exceed the 3.3 V supply voltages on pins VDD, VDDP,
VDDX and VDDR, even during power up and power down of the circuit.
Attention: Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Delta Sheet
24/30
2002-09-16
QuadFALC®
PEF 22554
Electrical Characteristics
2.2
Operating Range
Parameter
Ambient temperature
Supply voltages
Analog input voltages
Digital input voltages
Ground
Symbol
TA
VDD
VDDP1)
VDDR1)
VDDC
VDDX1)
VIA
VID
VSS
VSSP
VSSR
VSSX
Limit Values
Unit Notes
min.
max.
-40
85
°C
3.13
3.46
V
3.3 V ± 5%
3.13
3.46
V
3.3 V ± 5%
3.13
3.46
V
3.3 V ± 5%
1.62
1.98
V
1.8 V ± 10%
3.13
3.46
V
3.3 V ± 5%
0
3.602)
V
3.3 V ± 5%
0
3.46
V
3.3 V ± 5%
0
0
V
1)
Voltage ripple less than 50 mV on these 3.3V supplies
2)
Depending on the applied power supply level, signal clipping may occur due to activation of the ESD protection
diodes if the signal level exceeds VDDR + 0.3 V
Note: In the operating range, the functions given in the circuit description are fulfilled.
VDD, VDDP, VDDR and VDDX have to be connected to the same voltage level,
VSS, VSSP, VSSR, and VSSX have to be connected to ground level.
VDD and VDDC refer to the same ground level VSS.
Delta Sheet
25/30
2002-09-16
QuadFALC®
PEF 22554
Electrical Characteristics
2.3
Changed DC Characteristics
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
2.0
3.46
V
290
mA
E1 application
LIM1.DRS = 0
IDDT1
285
mA
T1 application
LIM1.DRS = 0
Average power
supply current
(digital line interface
mode)
IDD3.3V
IDDC
201)
mA
LIM1.DRS = 12)
90
mA
Transmitter leakage
current
ITL
15.0
µA
XL1/2 = VDDX;
XPM2.XLT = 1
15.0
µA
XL1/2 = VSSX;
XPM2.XLT = 1
433)
dB
RL1, RL2
LIM0.EQON = 1
1.25
2.25
V
RIL(2:0) = 0006)
0.84
1.07
RIL(2:0) = 0016)
0.45
0.58
RIL(2:0) = 0107)
0.26
0.33
RIL(2:0) = 0116)
0.15
0.21
RIL(2:0) = 1006)
0.10
0.14
RIL(2:0) = 1016)
0.07
0.09
RIL(2:0) = 1106)
0.04
0.06
RIL(2:0) = 1116)
Input high voltage
Average power
supply current
(analog line interface
mode)
VIH
IDDE1
Receiver sensitivity
E1 long haul
SRLH
Loss of signal (LOS)
detection limit4)5)
VLOS
1)
In single voltage supply mode (see Figure 1) maximum IDD3.3V = 110 mA
2)
System interface at 16 MHz; all-ones data; TA = 85 °C
3)
To achieve maximum receiver sensitivity of -43 dB (E1) take special care on sufficient attenuation of crosstalk
between Rx and Tx on board (e.g. in transformer) and run sequence as specified in Table 4 on Page 14
4)
Differential input voltage between pins RL1 and RL2
5)
Values only valid for LIM0.EQON = 1, LOS detection limits set to PCR = 15H, PCD = AH, applied signal
sequence +1,0,-1,0,...
6)
Parameter not tested in production
7)
Value measured in production to fulfil ITU-T G.775
Delta Sheet
26/30
2002-09-16
QuadFALC®
PEF 22554
Electrical Characteristics
2.4
Changed Supply Power Test Conditions T1/J1
Parameter
Symbol
Pulse Mask Programming
XPM2
01H
XPM1
16H
XPM0
95H
Delta Sheet
27/30
Test
Values
Unit Notes
2002-09-16
QuadFALC®
PEF 22554
Electrical Characteristics
2.5
Package Outlines
P-BGA-160-1
(Plastic Ball Grid Array Package)
GPA09369
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Delta Sheet
28/30
2002-09-16
QuadFALC®
PEF 22554
Appendix
3
Appendix
The calculation of the GCM register values is supported by a PC-based tool which is
available for free. A screenshot is shown in Figure 8 below.
F0260
Figure 8
Delta Sheet
Flexible Master Clock Calculator
29/30
2002-09-16
QuadFALC®
PEF 22554
Appendix
F0234
Figure 9
Delta Sheet
Application Wizard
30/30
2002-09-16