YGV619 AVDP6 Advanced Video Display Processor 6 ■ Outline YGV619 is a VDP (Video Display Processor) adopting OSD display control system which is best suited to the data broadcasting. The digital image interface of this device for connection with MPEG decoder has been improved. The use of this device allows screen composition that is suited to mobile information terminals, car navigation system, etc. Scan timing conforming to the display standard of digital TVs can be made. Two built-in PLL circuits allows to realize superimposition of external image signal on original image signal, and to produce clock best suited to SDRAM that is adopted as external video memory. ■ Features ● Display planes: External digital image is overlaid with OSD images composed of regions. Up to four planes, which are individually composed of back drop plane (plane on which external images are inputted) + region, are available. ● OSD image format: 8bit/dot palette mode, and 16 bit RGB or YCbCr format can be selected. YCbCr conforms to the conversion method of ITU601. Color palette (256 colors in 16777 k colors) can be specified by region. ● Digital image input format: · 18bitR6G6B6 · 16bitYCbCr422 · 8bitITU656 (Max. dot clock frequency: 80 MHz) (Max. dot clock frequency: 80 MHz) (Dot clock frequency 27 MHz) ● Digital image output format: · R6G6B6 + 2 bit AT · 18bitYCbCr444 + 2 bit AT · 16bitYCbCr422 + 2 bit AT · 8bitITU656 + 2 bit AT + 6 bit α blending coefficient ● Max. OSD resolution: 960 dots × 1080 lines (However, max. resolution of overlaid external image is 1920 ×1080 lines) ● Applicable digital TV image format: · 525i · 525p · 1125i ● Video capture function: · Draws external image input on the frame memory in real time. · Can convert resolution. · Provided with progressive scanning conversion YGV619 CATALOG CATALOG No.: LSI-4GV619A1 2001.01 YGV619 ● Priority of display planes Regular priority: Plane D > Plane C > Plane B > Plane A > Back drop plane The priority can be changed by region. ● α blending function (64 intensity level) Blending weight can be set by dot. ● Flicker cancel filter is built in. Enabling / disabling flicker cancel function can be set by region. ● 8 bit DACs are built in for R, G and B individually. (Max. operating frequency: 80 MHz) ● Two PLLs are built in. (1: Generates SDRAM clock and system clock 2: Generates dot clock) ● Display monitor control · Display resolution and scanning frequency can be set optionally. This function is compatible with progressive scanning and interlaced scanning modes. NTSC subcarrier output ● SDRAM can be added externally as VRAM (SDRAM generation clock frequency: Max. 80 MHz.) ·16 bit bus 512k words × 16 bits × 2 banks × 1 pc. 1M words × 16 bits × 4 banks × 1 pc. 2M words × 16 bits × 2 banks × 1 pc. ·32 bit bus 512k words × 16 bits × 2 banks × 2 pcs. 512k words × 32 bits × 4 banks × 1 pc. 1M words × 16 bits × 4 banks × 2 pcs. 2M words × 16 bits × 2 banks × 2 pcs. (capacity: 2M bytes) (capacity: 8M bytes) (capacity: 8M bytes) (capacity: (capacity: (capacity: (capacity: 4M bytes) 8M bytes) 16M bytes) 16M bytes) ● CPU interface Compatible with 16/32 bit CPU. Various built-in tables can be mapped on CPU space. Compatible with little endian and big endian ● Package: 240SQFP (YGV619-S) ● Operating temperature range: -45 to +85°C ● Power supply: 3.3V, single power supply Supplementary information: For YGV619, Application Manual that details the specifications of the device and the evaluation board (MSY619DB01) are available in addition to this brochure. The evaluation board is equipped with an SDRAM of 16 MB as a video memory. A high performance system can be realized when it is used with Hitachi’s CPU board, Super H Solution Engine. The device driver provided by Yamaha and attached to the evaluation board consists of the main body of the driver and API related layers, allowing the user to build it into the system easily according to the environment. For the details of these products, inquire of the sales agents or our business offices. For CPU board, inquire of: Hitachi ULSI Systems Co., Ltd. Tel:+81-42-351-6600 2 YGV619 ■ Block Diagram D31-0 A23-2 CSREG CSMEM DREQ RD A1/WR3 CPU INTERFACE WR2-0 DRAWING PROCESSOR UNIT WAIT SDQ31-0 SA12-0 SDRAM INTERFACE READY SBA1-0 SCS INT RAS RESET CAS WE DQM3-0 SYCKIN SYCKOUT SDCLK VIDEO CAPTURE CONTROLLER FSC CSYNC HSYNC HSIN VSIN CRT CONTROLLER AT1-0 DCKIN DCKOUT GCKIN GCKOUT PIXEL DATA CONTROLLER DRO[5:0] DGO[5:0] DRI[5:0] DBO[5:0] DGI[5:0] DBI[5:0] DAC R, G, B AVDP6 performs parallel processing including operation of writing display data into video memory (SDRAM) connected on the local bus (drawing function) and operation of sequentially reading bit map image stored in the video memory in accordance with monitor scanning (display function). Drawing function: This function transfers bit map image data configured on the external memory of CPU to video memory. For the transfer of the data, a method that maps the video memory as external memory managed by CPU and performs the transfer as the transfer between external memories of CPU, or a method that uses internal drawing processor of AVDP6 to configure the display image on the video memory can be used. Display function: This function displays the bit map image stored in the video memory in accordance with the display parameters that are stored in the internal registers of AVDP6 and the video memory. Basically, AVDP6 automatically sends out display data and refreshes SDRAM once initial setting for internal registers are completed. When performing dynamic processing such as scroll, the processing that synchronizes with the scanning of AVDP6 can be performed easily by using internal flag polling of AVDP6 or interrupt function. 3 D20 D19 D18 D17 D16 VSS D15 D14 D13 D12 D11 VDD D10 D9 D8 VSS D7 D6 D5 D4 D3 D2 D1 D0 VSS SYCKOUT SYCKIN VDD TEST2 TEST1 TEST0 SDQ0 SDQ15 SDQ1 VSS SDQ14 SDQ2 SDQ13 SDQ3 VDD SDQ12 VSS SDQ4 SDQ11 SDQ5 SDQ10 SDQ6 VSS SDQ9 SDQ7 SDQ8 DQM0 VDD WE VSS DQM1 CAS SDCLK AVSS2 AVDD2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 VDD DCKIN DCKOUT VSS TCK80 TCKS VSIN HSIN GCKS GCKIN DBI0 VDD DBI1 DBI2 DBI3 VSS DBI4 DBI5 DGI0 DGI1 DGI2 DGI3 DGI4 DGI5 DRI0 VDD DRI1 VSS DRI2 DRI3 DRI4 DRI5 AVSS3 AVDD3 AVDD4 REXT AVSS4 R AVSS4 G AVSS4 B AVSS4 VSS DBO0 DBO1 DBO2 VDD DBO3 DBO4 VSS DBO5 DGO0 DGO1 DGO2 DGO3 VSS DGO4 DGO5 DRO0 YGV619 ■ Pin Assignment AVSS1 AVDD1 A23 A22 A21 A20 A19 VSS A18 VDD A17 A16 A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 VDD A4 A3 A2 A 1 /W R 3 WR2 WR1 VSS WR0 RD RESET VDD CSREG CSMEM LWD LEND SYCKS DREQ VSS READY WAIT INT D31 VDD D30 D29 D28 D27 D26 D25 D24 VSS D23 D22 D21 VDD 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 Top view VDD DRO1 DRO2 VSS DRO3 DRO4 DRO5 GCKOUT AT0 VSS AT1 FSC BLANK HSYNC CSYNC VDD SDQ24 VSS SDQ23 SDQ25 SDQ22 SDQ26 SDQ21 VSS SDQ27 SDQ20 SDQ28 SDQ19 VDD SDQ29 VSS SDQ18 SDQ30 SDQ17 SDQ31 SDQ16 VSS DQM3 DQM2 SA4 SA3 VDD SA5 SA2 SA7 VSS SA6 SA1 SA0 SA8 SA10 SA9 SA12 VDD SBA0 VSS SA11 SBA1 SCS RAS YGV619 ■ Pin Functions < CPU INTERFACE > l D31-0 (I/O: Pull Up) ) CPU data bus. D31-16 pins are not used for 16 bit CPU (LWD=0). These pins are provided with a pull-up resistor. Unused pins are to be open. l A23-8 (I: Pull Up) ), A7-2 (I) ) CPU address bus. When accessing CSREG space, signals inputted to A23-8 pins are ignored without regarding to the bus width of CPU. Internal registers are selected depending on the state of signals inputted to A7-2 for 32 bit CPU or A72 and A1 / WR3 pin for 16 bit CPU. Systems that control AVDP6 only with CSREG do not use this address bus. However, A23-8 pins must be open because they are provided with pull-up resistor. All the addresses are valid when accessing CSMEM space. l CSREG (I) ) Chip select signal input to REG space. Internal registers of AVDP6 are accessed by a using write / read pulse that is inputted when the chip select signal is active. When this signal is low, inputs to A23-8 pins are ignored. ) l CSMEM (I) CSMEM is made active when directly mapping the video memory connected to local bus of AVDP6 on the memory space of CPU. The video memory managed by AVDP6 is directly accessed using write / read pulse that is inputted with this chip select signal is active. The video memory can be accessed from REG space without using this pin, however, high level signal must be inputted to CSMEM in this case. l LWD (I: Pull Up) Selects a CPU data bus width. When high level signal is inputted to this pin, AVDP6 operates as CPU 32 bit device, or when low level signal is inputted to this pin, AVDP6 operates as CPU 16 bit device. l A1 / WR3 , WR2-0 (I) ) Controls write access to AVDP6 when chip select input signal is active. A1 / WR3 control D31-24, WR2 controls D23-16, WR1 controls D15-8, and WR0 controls D7-0. For 16 bit CPU, A1 / WR3 function as A1 of CPU address. WR2 is not used, and thus must be open because the pin is provided with a pull-up resistor. ) l RD (I) Controls read access to AVDP6 when chip select input signal is active. D31-0 pins are in output state while this signal and chip select signals are active. For 16 bit CPU, only D15-0 pins are in output state and D31-16 pins are in input states at all times. ) l WAIT (O: Pull Up, 3-state output) Data wait signal output to CPU. When CSREG pin or CSMEM pin (hereafter called “CS pin”) is active, the WAIT signal is asserted once for RD or A1 / WR3 and WR2-0 signals, and then negated when AVDP6 becomes accessible. This pin becomes high impedance state when CS pin is not active, and outputs high level signal when CS pin is active and RD or A1 / WR3 and WR2-0 pins are not active. Use this pin or READY depending on the type of CPU. l READY (O: Pull Up, 3-state output) ) Data ready signal output to CPU. When AVDP6 becomes accessible, this signal is asserted. This pin becomes high impedance state when CS pin is not active, outputs high level signal when CS pin is active and RD or A1 / WR3, WR2-0 pins are not active. Use this pin or WAIT depending on the type of CPU. l INT (O) ) Interrupt request signal output to CPU. This pin becomes active when internal state of AVDP6 coincides with the setting conditions of the registers, and is reset when internal registers of AVDP6 are accessed. 5 YGV619 l DREQ (O) ) DMA request. This pin is asserted when AVDP6 becomes a state where it can accept the DMA transfer. The DMA transfer should be performed using regular WRn and RD pins. (Use Dual Address Mode of DMAC) l RESET (I: Schmidt input) ) Initial reset signal input. Inputting this signal clears the internal registers of AVDP6 to initialize the internal state of the device. (Some registers are loaded with initial value.) ) l LEND (I: Pull Up) Selects an endian of CPU. Big endian is selected when this pin is at high level, or little endian when the level is low. ) l SYCKS (I: Pull Up) Input high level to this pin or leave it open (because it is provided with pull-up resister) when clock inputted through DCKIN and DCKOUT pins are used as a system clock. VRAM clock and dot clock are generated from DCKIN. At this time, supply of clock to SYCKIN pin is not needed. Input low level signal to this pin when input clock from SYCKIN and SYCKOUT pins are used. < SDRAM interface > l SDQ31-0 (I/O) ) Data bus for SDRAM. AVDP6 uses these pins for data input/out access to SDRAM. The data bus width for SDRAM can be set to 32 bits or 16 bits by using the register setting. SDQ31-16 pins are not used when SDRAM bus width of 16 bits is used. At this time, SDQ31-16 pins are in output state at all times. l SA12-0 (O) ) Address bus for SDRAM. This bus uses time-sharing method to output row address and column address of SDRAM used by AVDP6. l SBA1-0 (O) ) Outputs access bank of SDRAM and ACTIVE command at the same time. SA12-0 and SBA1-0 pins output the signals as shown below depending on the type of SDRAM. VRM SBA1 SBA0 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 BA RA10 RA9 RA8 RA7 RA6 RA5 0 BA CA7 CA6 CA5 BA1 BA0 RA11 RA10 RA9 RA8 RA7 RA6 RA5 1 BA1 BA0 CA7 CA6 CA5 BA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 2 BA CA7 CA6 CA5 BA RA10 RA9 RA8 RA7 RA6 RA5 3 BA CA7 CA6 CA5 BA1 BA0 RA10 RA9 RA8 RA7 RA6 RA5 4 BA1 BA0 CA7 CA6 CA5 BA1 BA0 RA11 RA10 RA9 RA8 RA7 RA6 RA5 5 BA1 BA0 CA7 CA6 CA5 BA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 6 BA CA7 CA6 CA5 VRM shows the setting value of R#03:VRM[2:0]. Upper row shows the states issued, and lower column shows the state when Read/Write command is issued. SA4 RA4 CA4 RA4 CA4 RA4 CA4 RA4 CA4 RA4 CA4 RA4 CA4 RA4 CA4 of the SA3 SA2 SA1 SA0 RA3 RA2 RA1 RA0 CA3 CA2 CA1 CA0 RA3 RA2 RA1 RA0 CA3 CA2 CA1 CA0 RA3 RA2 RA1 RA0 CA3 CA2 CA1 CA0 RA3 RA2 RA1 RA0 CA3 CA2 CA1 CA0 RA3 RA2 RA1 RA0 CA3 CA2 CA1 CA0 RA3 RA2 RA1 RA0 CA3 CA2 CA1 CA0 RA3 RA2 RA1 RA0 CA3 CA2 CA1 CA0 pins when Active command is l SCS (O) ) Outputs chip select signal for SDRAM. A command is issued to SDRAM when this signal is active. When two 16 bit SDRAMs are used, connect this pin to both SDRAMs. 6 YGV619 l RAS (O) ) Outputs row address strobe signal for SDRAM. When two 16 bit SDRAMs are used, connect this pin to both SDRAMs. ) l CAS (O) Outputs column address strobe signal for SDRAM. When two 16 bit SDRAMs are used, connect this pin to both SDRAMs. ) l WE (O) Outputs write strobe signal for SDRAM. When two SDRAMs are used, connect this pin to both SDRAMs. l DQM3-0 (O) ) Outputs data mask signal for SDRAM. DQM3, DQM2, DQM1 and DQM0 are mask control signals for SDQ31-24, SDQ23-16, SDQ15-8 and SDQ7-0 respectively. When masking the data, corresponding DQM pin outputs high level signal. When one 16 bit SDRAM is used, DQM3-2 pins are not used, thus they are to be kept open. l SDCLK (I/O) ) Outputs CLK for SDRAM. SDCLK inputs the clock once outputted from this pin to use it as fetch clock to obtain setup time at SDQ input. < Display monitor interface > l R, G, B (O: analog output) ) Outputs linear RGB signal. Termination resistor of 37.5Ω is connected to this pin to make the resolution of output voltage amplitude 8 bits. Monitor with impedance of 75Ω can be driven directly through this interface as shown below. R(G,B) RL=75Ω RL=75Ω l REXT (I: analog input) ) A resistor is connected between this pin and GND(AVSS4) for adjusting the amplitude of signal outputted from DAC for RGB. The standard amplitude of signal outputted from DAC is 0.7 V (rREXT=470 Ω). The amplitude of the output can be adjusted finely within around ±100Ω by using the following formula. Vp_p = 470 × 0.7 / rREXT l CSYNC (O) ) Outputs composite sync signal for external monitor. In interlaced scanning mode, equalizing pulses are added to this signal. This pin can output VSYNC by using internal register setting. l HSYNC (O) ) Outputs horizontal sync signal for external monitor. l BLANK (O) ) Outputs a signal that indicates effective display period when LCD panel is connected to the device. l AT1-0 (O) ) AT1-0 bits of display data are outputted from these pins. l FSC (O) ) Outputs subcarrier clock for video encoder. The subcarrier clock is created by dividing the clock inputted to DCKIN pin by 1, 2, 4, or 8, which is determined by register setting. For example, inputting 14.318 MHz to DCKIN pin and dividing it by “4” give subcarrier clock of 3.58 MHz. 7 YGV619 l DRO5-0, DGO5-0, DBO5-0 (O) ) Outputs digital image signal. The output data format can be set to 18 bit RGB, 16 bit YCbCr(ITU601) or ITU656(8bit) by using R_YRT[1:0] and R_DOF[1:0]. 16 bit YCbCr and image data for ITU656 are outputted as described below. 18bit RGB DRO[5] DRO[4] DRO[3] DRO[2] DRO[1] DRO[0] DGO[5] DGO[4] DGO[3] DGO[2] DGO[1] DGO[0] DBO[5] DBO[4] DBO[3] DBO[2] DBO[1] DBO[0] 16 bit YCbCr n.c. n.c. CO[7] CO[6] CO[5] CO[4] CO[3] CO[2] CO[1] CO[0] YO[7] YO[6] YO[5] YO[4] YO[3] YO[2] YO[1] YO[0] ITU656(8bit) α [6] α [5] α [4] α [3] α [2] α [1] α [0] n.c. n.c. n.c. DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] n.c.: Stands for “no connection”. l GCKOUT (O) ) Outputs clock for digital image signal output. The state of the digital image signal changes synchronizing with this clock. Maximum frequency of the clock is 80 MHz 8 YGV619 < External video input > l VSIN (I: Pull Up) ) Resets vertical timing function of AVDP6. When this input signal is sampled at intervals equivalent to the width of horizontal sync pulse signal and low level is detected three times consecutively, this pin resets the internal V counters at HTL (time where horizontal sync signal starts). This function makes it possible to reset internal V counter synchronizing with vertical sync signal when composite sync signal is inputted to this pin. At the same time, this function automatically identifies fields in interlaced scanning mode. l HSIN (I: Pull Up) ) Resets horizontal timing function of AVDP6. AVDP6 samples the input signal synchronizing with the main clock and sets horizontal scanning time to the horizontal sync start position at the moment the signal falls from high level to low level, and at the same time, adjust the phase of division clock to HSIN. l DRI5-0, DGI5-0, DBI5-0 (I: Pull Up) ) Digital image signal input pin. This pin becomes valid when internal register R_EIE is “1”. The input data format can be set to 18 bit RGB, 16 bit YCbCr(ITU601) or ITU656(8bit) depending on the value of internal register R_EIF[1:0]. Input a signal to individual pins as shown below in accordance with the input data format. 18 bit RGB DRI[5] DRI[4] DRI[3] DRI[2] DRI[1] DRI[0] DGI[5] DGI[4] DGI[3] DGI[2] DGI[1] DGI[0] DBI[5] DBI[4] DBI[3] DBI[2] DBI[1] DBI[0] HSIN VSIN 16 bit YCbCr not use not use CI[7] CI[6] CI[5] CI[4] CI[3] CI[2] CI[1] CI[0] YI[7] YI[6] YI[5] YI[4] YI[3] YI[2] YI[1] YI[0] HSIN VSIN ITU656(8bit) SDI[7] SDI[6] SDI[5] SDI[4] SDI[3] SDI[2] SDI[1] SDI[0] SHSIN SVSIN BDI[7] BDI[6] BDI[5] BDI[4] BDI[3] BDI[2] BDI[1] BDI[0] HSIN VSIN Data for capture HSIN for capture VSIN for capture Data for BG HSIN for BG VSIN for BG l GCKIN (I) ) Clock for external video input is inputted to this pin. This pin is valid only when GCKS pin is low. Maximum frequency of this signal is 80 MHz. l GCKS (I: Pull Up) ) When external image input signal is present, low level signal is inputted to GCKS pin so that the GCKIN pin input is used as the video capture clock. When data are displayed on the back drop plane, this signal can be used as dot clock by using register setting. When no external image signal is not present, the clock inputted through DCKIN and DCKOUT pins can be used as GCK by making GCKS open state or high level. In this case, be sure to input a fixed signal to GCKIN pin. 9 YGV619 < PLL > l DCKIN (I) ), DCKOUT (O) ) XTAL connection pins for generating dot clock. The dot clock is used by sync control, display control and screen composition blocks. By using the built-in PLL, dot clock with various frequencies that synchronizes with the clock of DCKIN pin can be generated. When SYCKS pin is brought to high level, system clock is generated together with dot clock from input clock of DCKIN pin. Dot clock can be generated from input clock of DCKIN pin in accordance with the setting of the built-in registers, however, it is necessary to input some clock to DCKIN pin. (DCKIN pin is used to input initialization clock.) l SYCKIN (I) ), SYCKOUT (O) ) XTAL connection pins for generating system clock. This clock is supplied to SDRAM interface, CPU interface, drawing processor, and video capture blocks individually. When making SYCKS pin open or high level, input a fixed signal to SYCKIN pin. SYCKOUT pin can be left open. Externally oscillated clock, if used, should be inputted to SYCKIN. < Power supply > l AVDD1 (I) ), AVSS1 (I) ) Supplies power to PLL (PLLDCK) for dot clock. Connect 3.3 V to AVDD1 and GND level to AVSS1. When designing the circuit board, take care so that the noise from the lines that supply power to other power supply pins of AVDP6 does not enter these pins. l AVDD2 (I) ), AVSS2 (I) ) These pins supply power to PLL (PLLVCK) for system clock. Connect 3.3 V to AVDD2 and GND level to AVSS2. When designing the circuit board, take care so that the noise from the lines that supply power to other power supply pins of AVDP6 does not enter these pins. l AVDD3 (I) ), AVSS3 (I) ) Use these pins to supply power to the digital circuit of the build-in 8 bit DAC. Connect 3.3 V to AVDD3 and GND level to AVSS3. When designing the circuit board, take care so that the noise from the lines that supply power to other power supply pins of AVDP6 does not enter these pins. l AVDD4 (I) ), AVSS4 (I) ) Use these pins to supply power to the analog circuit of the build-in 8 bit DAC. Connect 3.3 V to AVDD4 and GND level to AVSS4. When designing the circuit board, take care so that the noise from the lines that supply power to other power supply pins of AVDP6 does not enter these pins. l VDD (I) ), VSS (I) ) These pins supply power to digital circuits and I/O section. Connect 3.3 V to VDD and GND level to VSS. When designing the circuit board, take care so that the noise from the lines that supply power to other power supply pins of AVDP6 does not enter these pins. < Others > l TEST2-0, TCKS, TCK80 (I) ) Input pins for testing. Input high level signal for regular operations of the device. 10 YGV619 ■ Electrical Characteristics Note! The values of electrical characteristics shown in this section are target data, and do not guarantee the specifications at the shipment of this product. The specification data may be changed without prior notice. Therefore, please confirm the newest data when using this product. ● Absolute maximum ratings Items Supply Voltage *2 Input Voltage *3 Input Voltage *2 Output Voltage Output Current Storage temperature Symbol VDD*1 VI*1 VI*1 VO*1 IO Tstg Ratings −0.5 to +4.6 −0.5 to VDD+ 0.5 −0.5 to 5.5 −0.5 to VDD+ 0.5 −20 to +20 −50 to +125 Unit V V V V mA °C *1 : Value with respect to VSS (GND) = 0V : for no-tolerant pins *3 : for tolerant pins *2 ● Recommended operating conditions Items Supply Voltage *2 Low Level Input Voltage *2 High Level Input Voltage *3 Low Level Input Voltage *3 High Level Input Voltage *4 Low Level Input Voltage *4 High Level Input Voltage Ambient operating temperature *1 Symbol VDD*1 VIL*1 VIH*1 VIL*1 VIH*1 VIL*1 VIH*1 TOP Min. 3.0 −0.3 2.0 −0.3 0.7VDD −0.3 2.0 −45 Typ. 3.3 Max. 3.6 0.8 VDD+ 0.3 0.3VDD VDD+ 0.3 0.8 5.5 +85 Unit V V V V V V V °C Typ. Max. 0.4 Unit V V µA µA mA : Value with respect to VSS (GND) = 0V *2 : when signal is inputted to I/O pins except DCIKN, SYCKIN and tolerant : DCIKN, SYCKIN pins *4 : for tolerant pins *3 ● Electrical characteristics under recommended operating conditions l DC characteristics Items Low level output voltage (CMOS) High level output voltage (CMOS) Input leakage current Output leakage current Current consumption Symbol VOL*1 VOH*2 ILI ILO IDD Min. Symbol CI CO CIO Min. 2.4 10 25 *1 *2 : Measurement condition IOL=100µA : Measurement condition IOH=-100µA l Pin Capacitance Items Input Pin Capacitance Output Pin Capacitance I/O Pin Capacitance Typ. Max. 8 10 12 Unit pF pF pF 11 YGV619 ■ Example of System Configuration AVDP6 is a display control device that operates as 16 bit or 32 bit I/O device on the external general purpose bus of CPU on the system in which the device is built-in. Because CPU I/F of AVDP6 uses asynchronous I/F, it can be controlled with general purpose SRAM I/F. SDRAM is connected on the local bus of AVDP6 to be used as video memory. The timing for this SDRAM is made by AVDP6 independently. In the SDRAM, bit map image and palette data that are displayed by AVDP6 are stored, and in addition, memory domain of SDRAM can be mapped directly on the bus of CPU so that the vacant space is utilized as the work domain of CPU. The memory space of SDRAM is controlled with general purpose SDRAM I/F. Examples of system configuration are shown below by application. Independent (free running) system RAM ROM SDRAM CPU AVDP6 ITU601 8bit YCbCr 16bit RGB 18bit dot clock RGB analog When displaying bit map image stored in the video memory independently, it is possible to output sync signal and display data that are compatible with various scan timing functions by supplying dot clock that is suited to the display device and by writing timing parameter into the registers for internal scan timing. Since the display data are outputted as analog and digital data, an LCD panel can be connected directly to the device and video signal can be created by Video Encoder device. OSD of NTSC digital images RAM ROM SDRAM CPU 27MHz MPEG2 decoder ITU656 AVDP6 ITU656 NTSC encoder Video This is an example of system configuration that uses AVDP6 to display OSD images of digital video equipment conforming to NTSC (SDTV) such as DVD. Since AVDP6 is equipped with input / output pins for digital images, the digital video signal can be inputted without converting it to analog signal, processed with OSD and α blending without deteriorating the quality of images, and then outputted. When displaying bitmap image of AVDP6 for external video with OSD, it is necessary to synchronize the external video signal with scanning of AVDP6. At this time, OSD image can be synchronized with external video by inputting sync signal of the external video into scan control circuit of AVDP6. (As the dot clock, use the clock that is synchronized with external video signal.) The digital image I/F of AVDP6 is compatible with digital I/F that conforms to CCIR-Rec601/656 (ITU656). 12 YGV619 OSD of HDTV digital image RAM ROM SDRAM CPU 74MHz MPEG2 decoder AVDP6 YCbCr 16bit YCbCr 16bit This is an example of the system configuration that uses AVDP6 as OSD image display device in HDTV. Since the device is able to input / output YCbCr422 data at the frequency up to 80 MHz, it is possible to control OSD for video signal of HDTV (1125i). In this case, The frequency of dot clock of OSD image becomes up to 40 MHz (the resolution equivalent to color difference data). (As the 74 MHz dot clock, it is necessary to input clock that synchronizes with external video signal.) OSD of NTSC analog image RAM ROM SDRAM CPU 14MHz HSYNC,VSYNC analog input analog RGB AVDP6 YS (AT0) analog RGB analog switch analog RGB When the external video is analog signal, switching signal for analog switch can be outputted together with OSD display data. Since the dot clock that synchronizes with sync signal of external video can be regenerated by using the built-in PLL, the superimposing function can be realized easily also for analog image signal. 13 YGV619 ■ External Dimensions of Package 14 YGV619 IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer’s sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL, OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANY THIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRANGIMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS’ INFRINGEMENT OF ANY THIRD PARTY’S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE. Notice The specification given here are provisional and subject to change without prior notice. Please confirm the latest documentation before using this product. AGENCY Address inquiries to: Semiconductor Sales & Marketing Department Head Office Tokyo Office Osaka Office All rights reserved 2001 203, Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 Namba Tsujimoto Nissei Bldg., 4F 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691 Printed in Japan