INFINEON PEB20571

ICs for Communications
DSP Embedded Line and Port Interface Controller
DELIC-LC
PEB 20570 Version 2.1
DELIC-PB
PEB 20571 Version 2.1
Preliminary Data Sheet 2003-08
DS 1.1
PEB 20570
PEB 20571
Revision History:
Current Version: 2003-08
Previous Version:
07.99
Page
Page
(in previous (in current
Version)
Version)
Subjects (major changes since last revision)
Trademarks changed
For questions on technology, delivery and prices please contact the Infineon Technologies Offices
in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at http://www.infineon.com
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56,
FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE,
ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC,
SLICOFI® are registered trademarks of Infineon Technologies AG.
ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG.
Note: OCEM® and OakDSPCore® (OAK®) are registered trademarks of ParthusCeva,
Inc..
Edition 2003-08
Published by Infineon Technologies AG,
TR,
Balanstraße 73,
81541 München
© Infineon Technologies AG 5/8/03.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with
the express written approval of the Infineon Technologies AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
DELIC
Preface
This document provides reference information on the DELIC-PB and -LC version 2.1.
Organization of this Document
This Preliminary Data Sheet is divided into 11 chapters and appendices. It is organized
as follows:
• Chapter 1, Introduction
Gives a general description of the product and its family, lists the key features, and
presents some typical applications.
• Chapter 2, Pin Description
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
• Chapter 3, Interface Description
Describes the DELIC external interfaces.
• Chapter 4, Functional IC Description
Describes the features of the main functional blocks.
• Chapter 5, Memory Structure
• Chapter 6, Register Descriptions
Containes the detailed register description.
• Chapter 7, Package Outlines
• Chapter 8, Electrical Characteristics
Containes the DC specification.
• Chapter 9, Timing Diagrams
Contains the AC specification (as far as available).
• Chapter 10, Application Hints
• Chapter 11, Mailbox Protocol Description
Describes the communication protocol to an external µP.
Preliminary Data Sheet
III
2003-08
DELIC
Your Comments
We welcome your comments on this document as we are continuously aiming at
improving our documentation. Please send your remarks and suggestions by e-mail to
[email protected]
Please provide in the subject of your e-mail:
device name (DELIC-LC/ -PB), device number (PEB 20570/ PEB 20571), device version
(Version 2.1), or and in the body of your e-mail:
document type (Preliminary Data Sheet), issue date (2003-08) and document revision
number (DS 1.1).
Preliminary Data Sheet
IV
2003-08
DELIC
PEB 20571
Table of Contents
Page
1
1.1
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2
2.1
2.2
2.3
2.4
2.5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Pin Diagram DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Pin Diagram DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Pin Definitions and Functions for DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . 2-3
Pin Definitions and Functions for DELIC-PB . . . . . . . . . . . . . . . . . . . . . . 2-15
Strap Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
3
3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.4
3.2.4.1
3.2.4.2
3.3
3.3.1
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.5.1
3.5.2
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Overview of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
IOM-2000 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
IOM-2000 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Command and Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
UPN State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
INFO Structure on the UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
UPN Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
S/T State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Signals / Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Intel/Siemens or Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
De-multiplexed or Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
DMA or Non-DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
DELIC External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
JTAG Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Boundary Scan Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.4.1
4.2.4.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Functional Overview and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
IOM-2000 Transceiver Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
TRANSIU Overview of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
TRANSIU Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Initialization of VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
S/T Mode Control and Framing Bits on IOM-2000 . . . . . . . . . . . . . . . . 4-4
Framing Bit (F-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Multiframing Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Preliminary Data Sheet
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2003-08
DELIC
PEB 20571
Table of Contents
4.2.4.3
4.2.4.4
4.2.5
4.2.5.1
4.2.5.2
4.2.5.3
4.2.6
4.2.7
4.2.7.1
4.2.7.2
4.2.7.3
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.3.2.6
4.3.2.7
4.3.2.8
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4
4.4.1.5
4.4.1.6
4.4.1.7
4.5
4.6
4.6.1
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.2.5
4.7
4.7.1
Page
Fa/N Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
DC-Balancing Bit (L-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
UPN Mode Control and Framing Bits on IOM-2000 . . . . . . . . . . . . . . . 4-6
Framing Bit (LF-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Multiframing Bit (M-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
DC-Balancing Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
IOM-2000 Command and Status Interface . . . . . . . . . . . . . . . . . . . . . . 4-7
IOM-2000 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
UPN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
UPN Scrambler/Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
S/T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
IOM-2 Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
IOMU Overview of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
IOMU Functional and Operational Description . . . . . . . . . . . . . . . . . . 4-15
Frame-Wise Buffer Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
I-buffer Logical Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
DSP Access to the D-Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
IOM-2 Interface Data Rate Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
IOMU Serial Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
IOMU Parallel Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
IOM-2 Push-Pull and Open-Drain Modes . . . . . . . . . . . . . . . . . . . . 4-19
Support of DRDY Signal from QUAT-S . . . . . . . . . . . . . . . . . . . . . . 4-20
PCM Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
PCMU Functional and Operational Description . . . . . . . . . . . . . . . . . . 4-22
Frame-Wise Buffer Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
DSP Inaccessible Buffer (I-buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
DSP Accessible Buffer (D-Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
PCMU Interface Data Rate Modes . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
PCMU Serial Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
PCMU Parallel Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
PCMU Tri-state Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
A-law/µ-law Conversion Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
HDLC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
HDLCU Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
DSP Operation of the HDLCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Initialization of the HDLCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Transmitting a Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Ending a Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Aborting a Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
DSP Access to the HDLCU Buffers . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
GHDLC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
GHDLC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
Preliminary Data Sheet
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PEB 20571
Table of Contents
Page
4.7.2
4.7.3
4.7.4
4.7.5
4.7.5.1
4.7.5.2
4.7.6
4.7.7
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
4.9
4.9.1
4.9.2
4.9.3
4.10
4.10.1
4.10.2
4.10.3
4.10.4
4.10.5
4.10.6
4.10.7
4.11
4.12
4.12.1
4.12.2
4.12.3
4.12.4
4.12.5
4.12.6
4.12.7
4.12.8
GHDLC Channel External Configurations . . . . . . . . . . . . . . . . . . . . . . 4-34
GHDLC General Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
GHDLC Protocol Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
External Configuration and Handshaking in Bus Mode . . . . . . . . . . . . 4-35
External Tri-State in Point-to-Multi-Point Mode . . . . . . . . . . . . . . . . 4-35
Arbitration of GHDLCs on a Collision Bus . . . . . . . . . . . . . . . . . . . . 4-36
GHDLC Memory Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
GHDLC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
DSP Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
DSP Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
DSP Run Time Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
Data Bus and Program Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Boot Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Reset Execution and Boot Strap Pin Setting . . . . . . . . . . . . . . . . . . . . 4-41
General Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
µP Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
OAK Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
DMA Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
Intel/Siemens Mode and Motorola Mode (Memory-to-Memory) . . . . . 4-45
Fly-By Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
PEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
Transmit Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
Receive Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47
Access to the DMA FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
DSP Core OAK+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
DSP Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
PCM Master/Slave Mode Clocks Selection . . . . . . . . . . . . . . . . . . . . . 4-52
DELIC Clock System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
IOM-2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
IOM-2000 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
REFCLK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
GHDLC Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
5
5.1
5.1.1
5.1.2
DELIC Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
DSP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
DSP Register Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
DSP Program Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Preliminary Data Sheet
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Table of Contents
Page
5.1.3
5.2
DSP Data Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
µP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
6
6.1
6.2
6.2.1
6.2.1.1
6.2.1.2
6.2.1.3
6.2.1.4
6.2.1.5
6.2.1.6
6.2.1.7
6.2.1.8
6.2.2
6.2.2.1
6.2.2.2
6.2.2.3
6.2.2.4
6.2.2.5
6.2.3
6.2.3.1
6.2.3.2
6.2.3.3
6.2.3.4
6.2.4
6.2.4.1
6.2.4.2
6.2.4.3
6.2.5
6.2.5.1
6.2.5.2
6.2.5.3
6.2.5.4
6.2.6
6.2.6.1
6.2.6.2
6.2.6.3
6.2.6.4
6.2.6.5
6.2.6.6
6.2.6.7
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
TRANSIU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
TRANSIU IOM-2000 Configuration Register . . . . . . . . . . . . . . . . . . 6-10
TRANSIU Channel Configuration Registers . . . . . . . . . . . . . . . . . . 6-11
VIP Command Registers (VIPCMR0, VIPCMR1, VIPCMR2) . . . . . 6-12
VIP Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
TRANSIU Initialization Channel Command Register . . . . . . . . . . . . 6-15
TRANSIU Initialization Channel Status Register (TICSTR) . . . . . . . 6-20
Scrambler Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Scrambler Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
IOMU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
IOMU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
IOMU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
IOMU Tri-State Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
IOMU DRDY Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
IOMU Data Prefix Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
PCMU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
PCMU Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
PCMU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
PCMU Tri-state Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
PCMU Data Prefix Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
A-/µ-law Unit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
A/µ-law Unit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
A/µ-law Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
A/µ-law Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
HDLCU Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
HDLCU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
HDLCU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
Channel Command Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Channel Status Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
GHDLC Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
GHDLC Test/ Normal Mode Register . . . . . . . . . . . . . . . . . . . . . . . 6-38
GHDLC Channel Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
GHDLC Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
GHDLC FSC Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . 6-39
GHDLC Receive Channel Status Registers 0..3 . . . . . . . . . . . . . . . 6-40
GHDLC Receive Data and Status . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
GHDLC Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42
Preliminary Data Sheet
VIII
2003-08
DELIC
PEB 20571
Table of Contents
6.2.6.8
6.2.6.9
6.2.6.10
6.2.6.11
6.2.6.12
6.2.6.13
6.2.6.14
6.2.7
6.2.7.1
6.2.7.2
6.2.7.3
6.2.7.4
6.2.8
6.2.8.1
6.2.8.2
6.2.8.3
6.2.9
6.2.9.1
6.2.9.2
6.2.9.3
6.2.9.4
6.2.9.5
6.2.9.6
6.2.9.7
6.2.9.8
6.2.10
6.2.10.1
6.2.10.2
6.2.10.3
6.2.11
6.2.11.1
6.2.11.2
6.2.11.3
6.2.11.4
6.2.11.5
6.2.11.6
6.2.11.7
6.2.11.8
6.2.11.9
6.2.11.10
6.2.11.11
6.2.11.12
Page
GHDLC Channel Transmit Command Registers . . . . . . . . . . . . . . . 6-43
ASYNC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
LCLK0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
LCLK1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
LCLK2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
LCLK3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
Muxes Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
DCU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
Status Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
Statistics Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51
Statistics Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
µP Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
µP Interface Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
Device Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
µP Mailbox Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
µP Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
µP Mailbox Busy Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
µP Mailbox Generic Data Register . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
µP Mailbox (General and DMA Mailbox) Data Registers . . . . . . . . . 6-57
DSP Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
DSP Mailbox Busy Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58
DSP Mailbox Generic Data Register . . . . . . . . . . . . . . . . . . . . . . . . 6-59
DSP Mailbox (General and DMA Mailbox) Data Registers . . . . . . . 6-59
DMA Mailbox Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60
DMA Mailbox Transmit Counter Register . . . . . . . . . . . . . . . . . . . . 6-60
DMA Mailbox Receive Counter Register . . . . . . . . . . . . . . . . . . . . . 6-60
DMA Mailbox Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . 6-61
Clock Generator Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
PDC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
PFS Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
CLKOUT Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63
DCXO Reference Clock Select Register . . . . . . . . . . . . . . . . . . . . . 6-64
REFCLK Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65
DCL_2000 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66
DCL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66
FSC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67
L1_CLK Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68
PFS Sync Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69
Realtime Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69
Strap Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70
Preliminary Data Sheet
IX
2003-08
DELIC
PEB 20571
Table of Contents
Page
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
8
8.1
8.2
8.3
8.4
8.5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Recommended 16.384 MHz Crystal Parameters . . . . . . . . . . . . . . . . . . . 8-3
9
9.1
9.2
9.2.1
9.2.2
9.3
9.4
9.4.1
9.4.2
9.5
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
µP Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
µP Access Timing in Motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
µP Access Timing in Intel/Infineon Mode . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
DMA Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
DMA Access Timing In Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
DMA Access Timing in Intel/Infineon Mode . . . . . . . . . . . . . . . . . . . . . 9-12
IOM®-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
10
10.1
10.2
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
DELIC Connection to External Microprocessors . . . . . . . . . . . . . . . . . . . 10-1
DELIC Worksheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
11
11.1
11.1.1
11.1.2
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
11.3.9
11.4
11.4.1
11.4.1.1
Mailbox Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Mailbox Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Mailbox Access Transmit Direction (µP->DELIC) . . . . . . . . . . . . . . . . 11-1
Mailbox Access Receive Direction (DELIC->µP) . . . . . . . . . . . . . . . . . 11-1
Subscriber Address (SAD) Interpretation . . . . . . . . . . . . . . . . . . . . . . . . 11-4
SAD as IOM-2 Port and Channel Number . . . . . . . . . . . . . . . . . . . . . . 11-4
SAD as IOM-2000 VIP and Channel Number . . . . . . . . . . . . . . . . . . . 11-5
Overview of Commands and Indications . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Commands and Indications for Boot Sequence . . . . . . . . . . . . . . . . . 11-5
General Commands and Indications . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Commands and Indications for Configuration . . . . . . . . . . . . . . . . . . . 11-7
Commands and Indications for IOM-2 C/I Channels . . . . . . . . . . . . . . 11-8
Commands and Indications for IOM-2 Monitor Channel . . . . . . . . . . . 11-8
Commands and Indications for IOM-2000 C/I Channels . . . . . . . . . . . 11-9
Commands and Indications for HDLC Channel . . . . . . . . . . . . . . . . . 11-10
Commands and Indications for GHDLC Channel . . . . . . . . . . . . . . . 11-10
Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Boot Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Boot Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Start Boot Command (0x55) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Preliminary Data Sheet
X
2003-08
DELIC
PEB 20571
Table of Contents
11.4.1.2
11.4.1.3
11.4.1.4
11.4.2
11.4.2.1
11.4.2.2
11.4.2.3
11.4.2.4
11.5
11.5.1
11.5.1.1
11.5.1.2
11.5.2
11.5.2.1
11.6
11.6.1
11.6.1.1
11.6.1.2
11.6.1.3
11.6.1.4
11.6.1.5
11.6.2
11.6.2.1
11.6.2.2
11.6.2.3
11.7
11.7.1
11.7.1.1
11.7.2
11.7.2.1
11.7.3
11.7.4
11.8
11.8.1
11.8.1.1
11.8.1.2
11.8.1.3
11.8.1.4
11.8.1.5
11.8.1.6
11.8.2
11.8.2.1
Page
Finish Boot Command (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Write Program Memory Command (0xAn) . . . . . . . . . . . . . . . . . . 11-13
Write Data Memory Command (0xEn) . . . . . . . . . . . . . . . . . . . . . . 11-14
Boot Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Error Indication (0b011100XX) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Start Loading Program RAM Indication (0x1F) . . . . . . . . . . . . . . . 11-15
Start Loading Data RAM Indication (0xEF) . . . . . . . . . . . . . . . . . . 11-15
Firmware Version Indication (0x00) . . . . . . . . . . . . . . . . . . . . . . . . 11-15
General Commands and Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
General Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
Write Register Command (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
Read Register Command (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
General Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Read Register Indication (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Initialization/Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
IOM-2000 Reference Channel Select Command (0x05) . . . . . . . . 11-20
IOM-2000 Delay Measurement Command (0x04) . . . . . . . . . . . . . 11-21
IOM-2000 VIP Channel Configuration Command (0x03) . . . . . . . 11-22
GHDLC Configuration Command (0x14) . . . . . . . . . . . . . . . . . . . . 11-22
Finish Initialization Command (0x06) . . . . . . . . . . . . . . . . . . . . . . . 11-24
Configuration Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
IOM-2000 Far-end Code Violation Indication (0x07) . . . . . . . . . . . 11-24
IOM-2000 Delay Indication (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
Finish VIP Channel Configuration Indication (0x02) . . . . . . . . . . . 11-26
IOM-2 C/I Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
IOM-2 C/I Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
Write C/I Value Command (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
IOM-2 C/I Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
Change Detected Indication (0x41) . . . . . . . . . . . . . . . . . . . . . . . . 11-27
Common Mailbox Parameter Structure . . . . . . . . . . . . . . . . . . . . . . . 11-27
Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28
IOM-2 Monitor Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
IOM-2 Monitor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
Search On Command (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
Search Reset Command (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
Monitor Reset Command (0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
Transmit Continuous Command (0x29) . . . . . . . . . . . . . . . . . . . . . 11-30
Transmit Command (0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
Transmit&Receive/Receive Only Command (0x2A) . . . . . . . . . . . 11-30
IOM-2 Monitor Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
Transfer Ready Indication (0x53) . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
Preliminary Data Sheet
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Table of Contents
Page
11.8.2.2
Receive Continuous Indication (0x52) . . . . . . . . . . . . . . . . . . . . . . 11-31
11.8.2.3
Receive Indication (0x51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
11.8.2.4
Transmit Abort Indication (0x55) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32
11.8.2.5
Monitor Active Indication (0x54) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32
11.8.3
Common Mailbox Parameter Structure . . . . . . . . . . . . . . . . . . . . . . . 11-32
11.8.4
Flow Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
11.9
IOM-2000 C/I Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
11.9.1
IOM-2000 C/I Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
11.9.1.1
Write C/I Value Command (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . 11-38
11.9.2
IOM-2000 C/I Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38
11.9.2.1
Change Detected Indication (0x11) . . . . . . . . . . . . . . . . . . . . . . . . 11-38
11.9.3
Common Mailbox Parameter Structure . . . . . . . . . . . . . . . . . . . . . . . 11-38
11.10
HDLC Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
11.10.1
HDLC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
11.10.1.1
Reset Command (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40
11.10.1.2
Transmit Command (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41
11.10.1.3
Transmit Continuous Command (0x1E) . . . . . . . . . . . . . . . . . . . . 11-41
11.10.1.4
Activation/Deactivation Command (0x20) . . . . . . . . . . . . . . . . . . . 11-41
11.10.2
HDLC Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42
11.10.2.1
Error Indication (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42
11.10.2.2
Transmit Ready Indication (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . 11-43
11.10.2.3
Receive Indication (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44
11.10.2.4
Receive Continuous Indication (0x32) . . . . . . . . . . . . . . . . . . . . . . 11-44
11.10.3
Common Mailbox Parameter Structure . . . . . . . . . . . . . . . . . . . . . . . 11-44
11.10.4
Flow Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45
11.11
GHDLC Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46
11.11.1
GHDLC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46
11.11.1.1
Reset Command (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46
11.11.1.2
Transmit Command (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47
11.11.1.3
Transmit Continuous Command (0x12) . . . . . . . . . . . . . . . . . . . . . 11-48
11.11.2
GHDLC Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
11.11.2.1
Error Indication (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
11.11.2.2
Fatal Error Indication (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
11.11.2.3
Transmit Ready Indication (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 11-49
11.11.2.4
Receive Indication (0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49
11.11.2.5
Receive Continuous Indication (0x22) . . . . . . . . . . . . . . . . . . . . . . 11-49
11.12
B-Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50
11.12.1
Switching Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50
11.12.1.1
8-bit Connect Command (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50
11.12.1.2
8-bit Disconnect Command (0x18) . . . . . . . . . . . . . . . . . . . . . . . . 11-52
12
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1
Preliminary Data Sheet
XII
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13
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Preliminary Data Sheet
-XIII
2003-08
DELIC
PEB 20571
List of Figures
Figure 1-1
Figure 1-2
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 2-1
Figure 2-2
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
Figure 4-10
Figure 4-11
Figure 4-12
Figure 4-13
Figure 4-14
Figure 4-15
Figure 4-16
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Figure 9-7
Page
Block Diagram of the DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Block Diagram of the DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
DELIC-LC in S/T and Upn Line Cards (up to 8 S/T and 16 Upn). . . . . 1-7
DELIC-LC in Uk0 Line Card for 16 Subscribers. . . . . . . . . . . . . . . . . . 1-8
DELIC-PB in Analog Line Card for 16 Subscribers . . . . . . . . . . . . . . . 1-8
DELIC-PB in Small PBX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Pin Configuration DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Pin Configuration DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Overview of IOM-2000 Interface Structure (Example with One VIP) . . 3-2
IOM-2000 Data Sequence (1 VIP with 8 Channels) . . . . . . . . . . . . . . 3-4
IOM-2000 Data Order (3 VIPs with 24 Channels) . . . . . . . . . . . . . . . . 3-5
IOM-2000 CMD/STAT Handling (1 VIP with 8 Channels) . . . . . . . . . . 3-6
IOM-2000 Command/Status Sequence (3 VIPs with 24 Channels) . . 3-6
UPN State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
State Diagram of LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
LT-T Mode State Diagram (Conditional and Unconditional States) . . 3-20
IOM®-2 Interface in Digital Linecard Mode . . . . . . . . . . . . . . . . . . . . 3-23
DELIC in Multiplexed and in De-multiplexed Bus Mode . . . . . . . . . . 3-25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
S/Q Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
IOMU Integration in DELIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
IOM-2 Interface Timing in Single/Double Clock Mode . . . . . . . . . . . . 4-18
IOM-2 Interface Open-Drain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
IOM-2 Interface Push-Pull Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
DRDY Signal Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
DRDY Sampling Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
PCMU Integration in DELIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
IOM-2 Interface Timing in Single/Double Clock Mode . . . . . . . . . . . . 4-25
HDLCU General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Data Processing in the GHDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
GHDLC Interface Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
GHDLC Receive and Transmit Buffer Structure . . . . . . . . . . . . . . . . 4-37
Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
DELIC Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
Write Cycle in Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Read Cycle in Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Write Cycle in Intel/Infineon De-multiplexed Mode . . . . . . . . . . . . . . . 9-4
Read Cycle in Intel/Infineon De-multiplexed Mode . . . . . . . . . . . . . . . 9-5
Write Cycle in Intel/Infineon Multiplexed Mode . . . . . . . . . . . . . . . . . . 9-6
Read Cycle in Intel/Infineon Multiplexed Mode . . . . . . . . . . . . . . . . . . 9-7
Interrupt Acknowledge Cycle Timing in Motorola Mode. . . . . . . . . . . . 9-8
Preliminary Data Sheet
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2003-08
DELIC
PEB 20571
List of Figures
Figure 9-8
Figure 9-9
Figure 9-10
Figure 9-11
Figure 9-12
Figure 9-13
Figure 9-14
Figure 9-15
Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Figure 11-5
Figure 11-6
Figure 11-7
Figure 11-8
Figure 11-9
Figure 11-10
Figure 11-11
Figure 11-12
Figure 11-13
Figure 11-14
Page
Interrupt Acknowledge Cycle Timing in Intel/Infineon Mode . . . . . . . . 9-8
IREQ Deactivation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
DMA Write Transaction Timing in Motorola Mode . . . . . . . . . . . . . . . 9-11
DMA Read-Transaction Timing in Motorola Mode . . . . . . . . . . . . . . . 9-12
DMA Write Transaction Timing in Intel/Infineon Mode. . . . . . . . . . . . 9-14
DMA Read Transaction Timing in Intel/Infineon Mode . . . . . . . . . . . 9-14
IOM®-2 Interface Timing with Single Data Rate DCL . . . . . . . . . . . . 9-15
Timing of the IOM®-2 Interface with Double Data Rate DCL . . . . . . 9-16
DELIC Connection to Intel 80386EX (Demuxed Configuration) . . . . 10-1
DELIC Connection to Siemens C165 (Demuxed Configuration) . . . . 10-2
DELIC-LC PCM unit mode 0 ( 4 ports with 2 MBit/s) . . . . . . . . . . . . . 10-3
Command/ Indication handshake of general mailbox . . . . . . . . . . . . 10-4
Transmit Mailbox Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Receive Mailbox Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Flow Diagram: Mailbox Write Access . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Initialization Flow Diagram: Configuration Example. . . . . . . . . . . . . 11-20
C/I Flow Diagram: Receiving C/I Value Changes . . . . . . . . . . . . . . 11-29
Monitor Flow Diagram: Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
Monitor Flow Diagram: Transmit Continuous. . . . . . . . . . . . . . . . . . 11-34
Monitor Flow Diagram: Search Mode . . . . . . . . . . . . . . . . . . . . . . . 11-35
Monitor Flow Diagram: Receive Only with Receive Continuous . . . 11-36
Monitor Flow Diagram: Transmit & Receive. . . . . . . . . . . . . . . . . . . 11-37
HDLC Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
HDLC Flow Diagram: Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45
HDLC Flow Diagram: Transmit Continuous . . . . . . . . . . . . . . . . . . . 11-45
Preliminary Data Sheet
XV
2003-08
DELIC
PEB 20571
List of Tables
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 2-19
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 4-5
Table 4-6
Table 4-7
Table 4-8
Table 4-9
Table 4-10
Table 4-11
Table 4-12
Table 4-13
Table 4-14
Table 4-15
Table 5-1
Page
IOM®-2 Interface Pins (DELIC-LC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
IOM-2000 Interface / LNC Port 1 (DELIC-LC) . . . . . . . . . . . . . . . . . . 2-4
LNC Port 0 (DELIC-LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Microprocessor Bus Interface Pins (DELIC-LC). . . . . . . . . . . . . . . . . 2-6
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC) . . . . . . . . 2-8
Clock Generator Pins (DELIC-LC) (additionally to IOM/PCM clocks) 2-11
Power Supply Pins (DELIC-LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
JTAG and Emulation Interface Pins (DELIC-LC) . . . . . . . . . . . . . . . 2-13
Test Interface Pins (DELIC-LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
IOM®-2 Interface Pins (DELIC-PB) . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
IOM-2000 Interface / LNC Port 1 (DELIC-PB) . . . . . . . . . . . . . . . . . 2-16
LNC Port 0 (DELIC-PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Microprocessor Bus Interface Pins (DELIC-PB) . . . . . . . . . . . . . . . 2-18
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) . . . . . . . 2-20
Clock Generator Pins (DELIC-PB) (additionally to IOM/PCM clocks) 2-24
Power Supply Pins (DELIC-PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
JTAG and Emulation Interface Pins (DELIC-PB) . . . . . . . . . . . . . . . 2-26
Test Interface Pins (DELIC-PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Strap Pins (Evaluated During Reset) . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Control Bits in S/T Mode on DR Line . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Control Bits in S/T Mode on DX Line . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
INFO Structure on UPN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
UPN State Machine Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
LT-S State Machine Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
LT-T Mode State Machine Codes (Conditional States) . . . . . . . . . . 3-18
TAP Controller Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Differences between DELIC-LC - DELIC-PB . . . . . . . . . . . . . . . . . . . 4-1
S/T Mode Multiframe Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
I-Buffer Logical Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
D-Buffer Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
DCL Frequency in Different IOM-2 Modes. . . . . . . . . . . . . . . . . . . . 4-17
I-Buffer Logical Memory Mapping of Input Buffers. . . . . . . . . . . . . . 4-23
I-Buffer Logical Memory Mapping of Output Buffers . . . . . . . . . . . . 4-23
DSP Access to D-Buffer Input Blocks . . . . . . . . . . . . . . . . . . . . . . . 4-23
DSP Access to D-Buffer Output Blocks . . . . . . . . . . . . . . . . . . . . . . 4-24
PCM TSC in 4 x 32 TS Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
PCM TSC in 2 x 64 TS Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
PCM TSC in 1 x 128 TS and 1 x 256 TS (1st Half) Mode . . . . . . . . 4-27
PCM TSC in 1 x 256 TS (2nd Half) Mode . . . . . . . . . . . . . . . . . . . . 4-27
Interrupt Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Overview of Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
DSP Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Preliminary Data Sheet
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2003-08
DELIC
PEB 20571
List of Tables
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 6-5
Table 6-6
Table 6-7
Table 6-8
Table 6-9
Table 6-10
Table 6-11
Table 6-12
Table 6-13
Table 6-14
Table 9-1
Table 9-2
Table 9-3
Table 9-4
Table 9-5
Table 9-6
Table 9-7
Table 9-8
Table 9-9
Table 9-10
Page
DSP Program address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Occupied DSP Data Address space . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
OAK memory mapped registers address space . . . . . . . . . . . . . . . . 5-3
µP Address Space Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
TRANSIU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Scrambler Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
IOMU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
PCMU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
A-/µ-law Unit Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
HDLCU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
GHDLC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
DCU Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
µP Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
General Mailbox Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DMA Mailbox Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Clock Generator Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Available ISDN Modes for each VIP Channel . . . . . . . . . . . . . . . . . 6-11
Tristate Control Assignment for IOM-2 Time Slots. . . . . . . . . . . . . . 6-24
Timing For Write Cycle In Motorola Mode . . . . . . . . . . . . . . . . . . . . . 9-2
Timing For Read Cycle In Motorola Mode . . . . . . . . . . . . . . . . . . . . . 9-3
Timing For Write Cycle In Intel/Infineon Demultiplexed Mode . . . . . . 9-4
Timing For Read Cycle In Intel/Infineon De-multiplexed Mode . . . . . 9-5
Timing For Write Cycle In Intel/Infineon Multiplexed Mode . . . . . . . . 9-6
Timing For Read Cycle In Intel/Infineon Multiplexed Mode . . . . . . . . 9-7
Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
R/W Behavior During DMA Transactions in Normal and Fly-By Mode 9-9
DMA Transaction timing in Mototrola Mode . . . . . . . . . . . . . . . . . . . 9-10
R/W Behavior During DMA Transactions in Normal and Fly-By Mode 913
Table 9-11
Table 9-12
Table 9-13
Table 11-1
Table 11-2
Table 11-3
Table 11-4
Table 11-5
Table 11-6
Table 11-7
Table 11-8
Table 11-9
Table 11-10
DMA Transaction Timing in Intel/Infineon Mode . . . . . . . . . . . . . . .
Timing Characteristics of the IOM®-2 . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics of the IOM®-2 . . . . . . . . . . . . . . . . . . . . .
Boot Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 C/I Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 C/I Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 Monitor Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 Monitor Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Data Sheet
XVII
9-13
9-15
9-16
11-5
11-6
11-6
11-6
11-7
11-7
11-8
11-8
11-8
11-9
2003-08
DELIC
Table 11-11
Table 11-12
Table 11-13
Table 11-14
Table 11-15
Table 11-16
Table 11-17
Table 11-18
IOM-2000 C/I Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
IOM-2000 C/I Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
HDLC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
HDLC Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
GHDLC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
GHDLC Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Switching Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Time Slot Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50
Preliminary Data Sheet
-XVIII
2003-08
DELIC
Introduction
1
Introduction
The DELIC and VIP chipset realizes multiple ISDN S/T and Up interfaces together with
controller functionality typically needed in PBX or Central Office systems. This
functionality comprises voice channel handling, signaling control, layer-1 control, and
even signal processing tasks.
Moreover it provides a programmable master/slave clock generator with 2 PLLs, an
universal µP interface and a DMA interface.
The controller part, DELIC, is planned in three different versions:
• DELIC-LC (PEB 20570) is a line card controller providing voice channel switching,
multiple HDLC and layer-1 control for up to three VIPs (24 ISDN channels). Other
transceiver ICs (32 analog or 16 digital channels) may additionally be connected via
IOM-2/GCI interface.
• DELIC-PB (PEB 20571) additionally provides a programmable telecom DSP
including program and data RAM. This DSP can be used for layer-1 control, protocol
support and signal processing. The flexibility gained by the programmability allows
Infineon to offer different application specific solutions with the same silicon just by
software configuration.
A configuration tool assists the user in finding a valid system configuration. Even more
customer specific DSP-routines can be integrated with the assistance of Infineon.
• DELIC-HD (PEB 20572) (in definition) includes up to 64 time-slot oriented HDLC
controllers, and 2 independent serial communication controllers. Additional transfer
and signalling protocols such as ASYNC and SS7 (PEB 3040 replacement) will be
provided in DSP software.
VIP PEB 20590 is the first (8 channel) ISDN transceiver that implements multiple UPN
and S/T interfaces within one device. The user can decide by programming in which
mode a desired channel shall work.
A total of 8 channels are provided for layer-1 subscriber or trunk line characteristic. The
VIP is programmed by the DELIC via the IOM-2000 interface.
VIP’s eight channels are programmable in the following maximum partitioning between
UPN and S/T channels:
Max. number of UPN and S/T Channels
UPN
8
7
6
5
4
S/T
0
1
2
3
4
Preliminary Data Sheet
1-1
2003-08
DELIC
Introduction
VIP-8 PEB 20591
Additionally to the features of the VIP, the VIP-8 allows any combination of UPN S/T
interface (i.e. each of the 8 channels may be programmed to S/T or UPN mode)
DELIC-LC
IOM-2 /
PCM
IOM - 2000
IOM-2000
Interface
24 HDLC
Controllers
Signaling
Controller
Clocks
µP Mailbox
DMA Mailbox
JTAG
PCM
PCM
Interface
Serial Port
Switch
224 x 256 TS
IOM-2 /
PCM
Interface
µP Interface
DELIC-LC-PO.vsd
Figure 1-1
Block Diagram of the DELIC-LC
Preliminary Data Sheet
1-2
2003-08
DELIC
Introduction
Switch
Program
RAM
DSP
Voice handling
Data RAM
IOM-2000
Interface
HDLC Controllers
Async/Sync
Controller
Clocks
µP Mailbox
DMA Mailbox
JTAG
DSP Emulation
Interface
µP Interface
Figure 1-2
PCM
Interface
PCM
IOM-2 /
PCM
Interface
Serial Port
IOM - 2000
IOM-2 /
PCM
DELIC-PB
Block Diagram of the DELIC-PB
Preliminary Data Sheet
1-3
2003-08
DSP Embedded Line and Port Interface Controller
DELIC-LC/ DELIC-PB
Version 2.1
1.1
PEB 20570
PEB 20571
CMOS
DELIC-LC Key Features
DELIC-LC is optimized for line card applications:
• One IOM-2000 interface supporting three VIPs i.e.
up to 24 ISDN channels
• Two IOM-2 (GCI) ports (configurable as PCM ports)
supporting up to 16ISDN channels or 32 analog
subscribers
• Four PCM ports with up to 4 x 2.048 Mbit/s
(4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s
P-TQFP-100-1
•
•
•
•
•
Switching matrix 224 x 256 TS (8-bit switching)
24 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
Serial communication controller: high-speed signaling channel for 2.048 Mbit/s
Standard multiplexed and de-multiplexed µP interface: Siemens, Intel, Motorola
Programmable PLL based Master/Slave clock generator, providing all system clocks
from a single 16.384 MHz crystal source
• JTAG compliant test interface
• single 3.3 V power supply, 5 V tolerant inputs
1.2
DELIC-PB Key Features
Compared to the DELIC-LC, having a fixed functionality, the DELIC-PB provides a high
degree of flexibility (in terms of selected number of ports or channels).
Additionally it features computing power for typical DSP-oriented PBX tasks like
conferencing, DTMF..
A Microsoft Windows based configuration tool, the Configurator, enables to generate an
application specific functionality. Its features are mainly determined by the firmware of
the integrated telecom DSP.
Type
Package
PEB 20570/ PEB 20571
P-TQFP-100-1
Preliminary Data Sheet
1-4
2003-08
DELIC
Introduction
List of maximum available features:
• One IOM-2000 interface supporting up to three VIPs i.e. up to 24 ISDN channels
• Up to two IOM-2 (GCI) ports (also configurable as PCM ports) supporting up to 16
ISDN channels or 32 analog subscribers
• Up to four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or
1 x 8.192 Mbit/s
• Switching matrix 224 x 256 TS (switching of 4-/8- bit time slots)
• Up to 32 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
• Serial communication controller: high-speed signaling channel of up to 16.384 Mbit/s
• DECT synchronization support
• Standard multiplexed and de-multiplexed µP interface: Siemens, Intel, Motorola
• Dedicated DMA support mailbox
• Integrated DSP core OAK®+ (up to 60 MIPS for layer 1 control, signalling and DSPalgorithms)
• 4 KW on-chip program memory
• 2 KW on-chip data memory
• 2 KW ROM
• DSP work load measurement for run-time statistics, DSP alive indication
• On chip debugging unit
• Serial DSP program debugging interface connected via JTAG port
• A-/µ-law conversion unit
• Programmable PLL based Master/Slave clock generator, providing all system clocks
from a single 16.384 MHz crystal source
• JTAG compliant test interface
• single 3.3 V power supply, 5 V compatible inputs
Note: As each feature consumes system resources (DSP-performance, memory, port
pins), the maximum available number of supported interfaces or HDLC channels
is limited by the totally available resources. A System Configurator tool helps to
determine a valid configuration.
Preliminary Data Sheet
1-5
2003-08
DELIC
Introduction
1.3
Logic Symbol
P-TQFP-100-1
Power Supply
27
IOM-2
Interfaces
7
14
IOM-2000/ LNC
Interface
DELPHI-LC
PEB20570
5
DELPHI-PB
5
PEB 20571
Clock
Signals
9
LNC or Signaling
Interface
P-TQFP-100
26
µP Interface
Figure 1-1
PCM/ LNC
Interfaces
5
2
JTAG
Interface
Test
Interface
DELIC-logic-DS.vsd
Logic Symbol
Preliminary Data Sheet
1-6
2003-08
DELIC
Introduction
1.4
Typical Applications
The following two figures show example configurations of DELIC-PB Line card
applications for different ISDN interface standards.
In Figure 1-2, three VIP transceiver ICs are connected to the DELIC-PB via the new
IOM-2000 interface, whereas in Figure 1-3 and Figure 1-4 IOM-2 (GCI) interfaces are
used.
up to
4x
S/T
4x
Upn
VIP
PEB 20590
IOM-2000
PCM
4 x 32 TS
DELIC
up to
4x
S/T
4x
Upn
8x
Upn
PEB 20570
(PEB 20571)
VIP
PEB 20590
Signaling
up to 2.048 Mbit/s
VIP
PEB 20590
Memory
Figure 1-2
µP
Infineon
C166
DELIC-LC in S/T and Upn Line Cards (up to 8 S/T and 16 Upn)
Preliminary Data Sheet
1-7
2003-08
DELIC
Introduction
HYBRID
QUAD-U
HYBRID
HYBRID
IOM-2
..
.
QUAD-U
DELIC
HYBRID
16 x Uk0
PEB 20570
(PEB 20571)
HYBRID
QUAD-U
HYBRID
HYBRID
PCM
4 x 32 TS
..
.
Signaling
QUAD-U
HYBRID
Memory
Figure 1-3
µP
Infineon
C166
DELIC-LC in Uk0 Line Card for 16 Subscribers
HV-SLIC
SLICOFI - 2
IOM-2
HV-SLIC
HV-SLIC
16 x
t/r
PCM
4 x 32 TS
SLICOFI - 2
DELPHI-PB
HV-SLIC
IOM-2
HV-SLIC
PEB 20571
SLICOFI - 2
HV-SLIC
HV-SLIC
Signaling
SLICOFI - 2
HV-SLIC
Memory
Figure 1-4
µP
Siemens
C166
DELIC-PB in Analog Line Card for 16 Subscribers
Preliminary Data Sheet
1-8
2003-08
DELIC
Introduction
HV-SLIC
SLICOFI-2
IOM-2
PCM
HV-SLIC
up to 32 TS
32 x t/r
HV-SLIC
SLICOFI-2
HV-SLIC
Central
Office
DELIC-PB
PEB 20571
4x
UPN
VIP
2xS
PEB 20590
IOM-2000
LNC
2 Mbit/s
for service
2xT
Power
Supply
Figure 1-5
Memory
µP
Infineon
C166
DELIC-PB in Small PBX
Preliminary Data Sheet
1-9
2003-08
DELIC
PEB 20571
Pin Descriptions
2
Pin Descriptions
2.1
Pin Diagram DELIC-LC
(top view)
TDO
TMS
TDI/ SCANEN
JTCK
LCLK0
TRST
VDD
VSS
LTSC0/ LRTS0
LCxD0/LCTS0
LTxD0
LRxD0
DSP_STOP
STAT/ LCTS1
VSS
VDD
DR/ LRxD1
CMD/ LCLK1
DCL_2000/ LRTS1
DX/ LTxD1
RxD3/ LCTS3
VSS
VDD
RxD1/LRxD3
RxD2/ LCTS2
P-TQFP-100-1
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RxD0/LRxD2
TSC0/ LRTS2
TXD0/LTxD2
TSC1/ LRTS3
TxD1/LTxD3
TSC2
TxD2/LCLK2
TSC3
VDD
VSS
TxD3/LCLK3
PFS
PDC
RESIND
REFCLK
VDD
VSS
VSSA
CLK16-XI
CLK16-XO
VDDA
VSSA
VSSA
VDDA
VDDA
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DELIC-LC
PEB 20570
SCANMO
VSS
L1_CLK
VSS
VDD
DRDY
DD1
DD0
DU1
DU0
DCL
FSC
A6
VSS
VDD
A5
A4
A3
A2
A1
A0
RESET
CLKOUT
VSS
VDD
Figure 2-1
D5
D6
D7
D4
VSS
D3
VDD
D2
D1
D0
ALE
RD / DS
WR / R/W
DREQR
CS
DREQT
VSS
VDD
MODE
IREQ
IACK
XCLK
CLK_DSP
DSP_FRQ
DCXOPD
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 20 2122 23 2425
Pin Configuration DELIC-LC
Preliminary Data Sheet
2-1
2003-08
DELIC
PEB 20571
Pin Descriptions
2.2
Pin Diagram DELIC-PB
(top view)
TDO
TMS
TDI/ SCANEN
JTCK
LCLK0
TRST
VDD
VSS
LTSC0/ LRTS0
LCxD0/LCTS0
LTxD0
LRxD0
DSP_STOP
STAT/ LCxD1/LCTS1
VSS
VDD
CMD/ LCLK1
DR/ LRxD1
DCL_2000/ LTSC1/LRTS1
DX/ LTxD1
RxD3/ LCxD3/LCTS3
VSS
VDD
RxD1/LRxD3
RxD2/ LCxD2/LCTS2
P-TQFP-100-1
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RxD0/LRxD2
TSC0/ LTSC2/LRTS2
TXD0/LTxD2
TSC1/ LTSC3/LRTS3
TxD1/LTxD3
TSC2
TxD2/LCLK2
TSC3
VDD
VSS
TxD3/LCLK3
PFS
PDC
RESIND
REFCLK
VDD
VSS
VSSA
CLK16-XI
CLK16-XO
VDDA
VSSA
VSSA
VDDA
VDDA
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DELIC-PB
PEB 20571
SCANMO
VDD
L1_CLK
VSS
VDD
DRDY
DD1
DD0
DU1
DU0
DCL
FSC
A6
VSS
VDD
A5
A4/DACK
A3
A2
A1
A0
RESET
CLKOUT
VSS
VDD
Figure 2-2
D5
D6
D7
D4
VSS
D3
VDD
D2
D1
D0
ALE
RD / DS
WR / R/W
CS
DREQR
DREQT
VSS
VDD
IREQ
MODE
IACK
XCLK
CLK_DSP
DSP_FRQ
DCXOPD
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 20 2122 23 2425
Pin Configuration DELIC-PB
Preliminary Data Sheet
2-2
2003-08
DELIC
PEB 20571
Pin Descriptions
2.3
Pin Definitions and Functions for DELIC-LC
Note: The column “During Reset” refers to the time period that starts with activation of
RESET input and ends with the deactivation of the RESIND output. During this
period, the DELIC’s strap pins (refer to Table 2-19) may be driven by external pulldown or pull-up resistors to define DELIC’s configuration. If external pull-down or
pull-up resistors are not connected to the strap pins, the value of each strap pin
during reset will be determined by an internal pull-up or pull-down resistor,
according to the default strap value of each pin.
The user must ensure that connected circuits do not influence the sampling of the
strap pins during reset.
The column “After Reset” describes the behavior of every pin, from the
deactivation of the RESIND output until the DELIC’s registers are programmed.
Table 2-1
IOM®-2 Interface Pins (DELIC-LC)
Pin
No.
Symbol
In (I)
During
Out(O) Reset
After
Reset
Function
39
FSC
O
O
O
Frame Synchronization Clock (8 kHz)
Used for both the IOM-2 and the IOM2000 interface
40
DCL
O
O
TESTStrap (3),
(internal
pull-up),
refer to
Table 2-19
IOM-2 Data Clock 2.048 MHz or 4.096
MHz
43
DD0
O(OD)
High Z
High Z Data Downstream IOM-2 Interface
Channel0
44
DD1
O(OD)
High Z
High Z Data Downstream IOM-2 Interface
Channel1
41
DU0
I
I
I
Data Upstream IOM-2 Interface
Channel 0
42
DU1
I
I
I
Data Upstream IOM-2 Interface
Channel 1
45
DRDY
I
I
I
D- Channel Ready
Stop/Go information for D-channel
control on S/T interface in LT-T.
Affects only IOM-2 port 0.
DRDY = 1 means GO
DRDY = 0 means STOP
Preliminary Data Sheet
2-3
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-2
IOM-2000 Interface / LNC Port 1 (DELIC-LC)
Pin
No.
Symbol
70
DCL_2000 / O
69
68
67
64
In (I)
During After
Out (O) Reset Reset
LRTS1
O
DX /
O
LTxD1
O (OD)
DR /
I
LRxD1
I
CMD /
O
LCLK1
I/O
STAT /
I
LCTS1
I
Preliminary Data Sheet
O
O
Function
IOM-2000 Data Clock
3.072, 6.144 or 12.288 MHz
’request-to-send’ functionality (Async
mode)
High Z
High Z
Data Transmit
Transmits IOM-2000 data to VIP
LNC Transmit Serial Data Port 1
(Async mode).
I
I
Data Receive
Receives IOM-2000 data from VIP
LNC Receive Serial Data Port 1
(Async mode).
High Z
High Z
IOM-2000 Command
Transmits DELIC commands to VIP.
LNC Clock Port 1.
When configured as output may be
driven at the following frequencies:
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
I
I
IOM-2000 Status
Receives status information from VIP.
LNC1 Clear to Send
’clear-to-send’ functionality (Async
mode)
2-4
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-3
LNC Port 0 (DELIC-LC)
Pin
No.
Symbol In (I)
During
Out (O) Reset
After
Reset
Function
62
LRxD0
I
I
I
LNC Receive Serial Data Port 0
(HDLC and Async mode).
61
LTxD0
O (OD)
High Z
High Z LNC Transmit Serial Data Port 0
(HDLC and Async mode).
60
LTSC0 / O
LRTS0
PLLBypass”
strap.
Internal
pull-up
refer to
page 228
H
I
I
59
LCxD0 / I
LCTS0
LNC0 Tristate Control / Request to Send
2 modes per S/W selectable:
1) TxD output is valid (HDLC mode).
Supplies a control signal for an external
driver. (’low’ when the corresponding
TxD-output is valid).
2) ’request-to-send’ functionality
(Async mode)
LNC0 Collision Data / Clear to Send
2 modes per S/W selectable:
1) Collision Data (HDLC Mode).
2) ’clear-to-send’ functionality
(Async mode)
56
LCLK0
I/O
Preliminary Data Sheet
I
I
LNC Clock Port 0
When configured as output may be
driven at the following frequencies:
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
2-5
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-4
Microprocessor Bus Interface Pins (DELIC-LC)
Pin
No.
Symbol In (I)
During
Out (O) Reset
After
Reset
Function
25
24
23
22
21
18
17
16
D7
D6
D5
D4
D3
D2
D1
D0
I/O
The direction of these pins
depends on the value of the
following pins:
CS, RD/DS, WR / R/W and
MODE
Data Bus
38
35
34
33
32
31
30
A6
A5
A4
A3
A2
A1
A0
I
Address Bus (bits 6 ... 0)
11
DREQR O
L
CLOCK
MASTER
Strap
(internal
pull-down),
refer to
Table 2-19
Strap pin
10
DREQT O
L
EMULATION
BOOT
Strap
(internal
pull-down),
refer to
Table 2-19
Strap pin
12
CS
I
Chip Select
A "low" on this line selects all registers
for read/write operations.
I
I
Note: When operated in address/data
multiplex mode, this bus is used
as a multiplexed AD bus. The
Address pins are externally
connected to the AD bus.
Note: When operated in address/data
multiplex mode, this bus is used
as a multiplexed AD bus. The
Data
pins
are
externally
connected to the AD bus.
I
Preliminary Data Sheet
I
2-6
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-4
Microprocessor Bus Interface Pins (DELIC-LC) (Continued)
Pin
No.
Symbol In (I)
During
Out (O) Reset
After
Reset
Function
13
WR/
I
Write (Intel/Siemens Mode)
Indicates a write access.
I
I
R/W
14
RD/
Read/Write (Motorola Mode)
Indicates the direction of the data
transfer
I
I
I
Read (Intel/Siemens Mode)
Indicates a read access.
Data Strobe (Motorola Mode)
During a read cycle, DS indicates that
the DELIC should place valid data on
the bus. During a write access, DS
indicates that valid data is on the bus.
DS
15
ALE
I
I
I
Address Latch Enable
Controls the on-chip address latch in
multiplexed bus mode. While ALE is
’high’, the latch is transparent. The
falling edge latches the current
address. ALE is also evaluated to
determine
the
bus
mode
(’low’=multiplexed,
’high’=demultiplexed)
7
MODE
I
I
I
Bus Mode Selection
Selects the µP bus mode
(’low’=Intel/Infineon, ’high’=Motorola)
6
IREQ
O
(OD)
High Z
(OD)
High Z Interrupt Request is programmable to
(OD)
push/pull (active high or low) or opendrain. This signal is activated when the
DELIC requests a µP interrupt. When
operated in open drain mode, multiple
interrupt sources may be connected.
5
IACK
I
I
I
Preliminary Data Sheet
Interrupt Acknowledge
2-7
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-4
Microprocessor Bus Interface Pins (DELIC-LC) (Continued)
Pin
No.
Symbol In (I)
During
Out (O) Reset
After
Reset
Function
29
RESET
I
I
System Reset
DELIC is forced to go into reset state.
89
RESIND O
O
O
Reset Indication
Indicates that the DELIC is executing a
reset. The DELIC remains in reset
state for at least 500 µs after the
termination of the RESET pulse.
Table 2-5
I
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC)
Pin Symbol In (I)
During
No.
Out (O) Reset
After
Reset
Function
87
PFS
I/O
I
I
PCM Frame Synchronization Clock.
8 kHz/4 kHz when input or 8 kHz when
output.
Note: When PFS is configured as 4 kHz
input,
PDC
configuration
is
restricted to 2.048 MHz input.
88
PDC
I/O
I
I
PCM Data Clock (input or output)
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
76
RxD0 /
I
I
I
PCM Receive Data Port 0
LRxD2
I
TxD0 /
O
LTxD2
O(OD)
78
Preliminary Data Sheet
LNC Receive Serial Data Port 2
(Async mode)
High
Z
High
Z
PCM Transmit Data Port 0
LNC Transmit Serial Data Port 2
Async mode)
2-8
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-5
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC) (Continued)
Pin Symbol In (I)
During
No.
Out (O) Reset
77
74
TSC0 /
O
LRTS2
O
After
Reset
Function
H
Reset
Counter
Bypass”
strap
Internal
pull-up
refer to
page 228
PCM Tristate Control Port 0
Supplies a control signal for an external
driver (’low’ when the corresponding TxDoutput is valid).
I
PCM Receive Data Port 2
LNC2 Tristate Control / Request To Send
’request-to-send’ functionality
(Async mode)
RxD2 /
I
LCTS2
I
TxD2 /
O
LCLK2
I/O
81
TSC2
O
TEST(1) H
strap
refer to
page 228
PCM Tristate Control Port 2
Supplies a control signal for an external
driver (’low’ when the corresponding TxDoutput is valid).
75
RxD1 /
I
I
PCM Receive Data Port 1
LRxD3
I
TxD1 /
O
LTxD3
O(OD)
82
80
Preliminary Data Sheet
I
LNC2 ’clear-to-send’ functionality
(Async mode)
weak
low
weak
low
PCM Transmit Data Port 2
LNC External Clock Port 2
When configured as output may be driven
at the following frequencies:
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
I
LNC Receive Serial Data Port 3
(Async mode)
High
Z
High
Z
PCM Transmit Data Port 1
LNC Transmit Serial Data Port 3
(Async mode)
2-9
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-5
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC) (Continued)
Pin Symbol In (I)
During
No.
Out (O) Reset
79
TSC1 /
O
LRTS3
71
86
83
RxD3 /
I
LCTS3
I
TxD3 /
O
LCLK3
I/O
TSC3
O
Preliminary Data Sheet
After
Reset
Function
H
PLL
PowerDown
strap
Internal
pull-up
refer to
page 228
PCM Tristate Control Port 1
Supplies a control signal for an external
driver (’low’ when the corresponding TxDoutput is valid).
I
PCM Receive Data Port 3
I
LNC3 Request to Send
’request-to-send’ functionality
(Async mode)
LNC3 ’clear-to-send’ functionality
(Async mode)
weak
low
weak
low
PCM Transmit Data Port 3
LNC External Clock Port 3
When configured as output may be driven
at the following frequencies: 2.048 MHz,
4.096 MHz, 8.192 MHz, 16.384 MHz
TEST(1) H
strap
refer to
page 228
PCM Tristate Control Port 3
Supplies a control signal for an external
driver (’low’ when the corresponding TxD
output is valid).
2-10
2003-08
DELIC
PEB 20571
Pin Descriptions
.
Table 2-6
Clock Generator Pins (DELIC-LC) (additionally to IOM/PCM clocks)
Pin
No.
Symbol
In (I)
During After
Out (O) Reset Reset
Function
94
CLK16-XI
I
I
I
16.384 MHz External Crystal Input
95
CLK16-XO
O
O
O
16.384 MHz External Crystal Output
1
DCXOPD
I
I
I
DCXO Power Down and Bypass
Activating this input powers down the
on-chip DCXO PLL.
The input CLK16-XI is used directly as
the internal 16.384 MHz clock, and the
oscillator and the shaper are bypassed.
Required for testing; during normal
operation this input should be
permanently low (‘0’).
2
CLK_DSP
I
I
I
External DSP Clock
Provides a DSP clock other than
61.44 MHz from an external oscillator.
3
DSP_FRQ
I
I
I
DSP Operational Frequency Selection
(e.g. for test purpose)
0: The DSP is clocked internally at
61.44 MHz
1: The DSP clock is driven by the
CLK_DSP input pin
48
L1_CLK
O
O
O
Layer-1 Clock
15.36 MHz or 7.68 MHz
28
CLKOUT
O
O
O
General Purpose Clock Output
2.048 MHz, 4.096 MHz, 8.192 MHz,
15.36 MHz or 16.384 MHz
4
XCLK
I
I
I
External Reference Clock
Synchronization input from Layer-1 ICs
(8 kHz, 512 kHz or 1.536 MHz)
This pin is connected to the VIP’s
REFCLK output at 1.536 MHz.
90
REFCLK
I/O
I
I
Reference Clock
Input: Synchronization of DELIC clock
system
Output: Used to drive a fraction of
XCLK to the system clock master
(8 kHz or 512 kHz programmable)
Preliminary Data Sheet
2-11
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-7
Power Supply Pins (DELIC-LC)
Pin
No.
Symbol
In (I)
During After
Out (O) Reset Reset
Function
8
19
26
36
46
57
65
72
84
91
VDD
I
I
I
Power Supply 3.3 V
Used for core logic and interfaces in pure
3.3 V environment
9
20
27
37
47
49
58
66
73
85
92
VSS
I
I
I
Digital Ground (0 V)
96
99
100
VDDA
I
I
I
Power Supply 3.3 V Analog Logic
Used for DCXO and PLL
93
97
98
VSSA
I
I
I
Analog Ground
Used for DCXO and PLL
Preliminary Data Sheet
2-12
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-8
JTAG and Emulation Interface Pins (DELIC-LC)
Pin Symbol
No.
In (I)
During After
Out (O) Reset Reset
Function
Used for boundary scan according to IEEE 1149.1
54
JTCK
I
I
I
JTAG Test Clock
Provides the clock for JTAG test logic.
Used also for serial emulation interface.
53
TMS
I
I
I
Test Mode Select
A ’0’ to ’1’ transition on this pin is
required to step through the TAP
controller state machine.
52
TDI /
I
I
I
Test Data Input
In the appropriate TAP controller state
test data or a instruction is shifted in via
this line.
Used also for serial emulation interface.
Note: This pin must not be driven to low
on the board during reset and
operation to ensure functioning of
DELIC
SCANEN
51
TDO
SCAN Enable
When both SCANMO and SCANEN are
asserted, the full-scan tests of DELIC
are activated.
Not used during normal operation.
O
Preliminary Data Sheet
O
O
Test Data Output
In the appropriate TAP controller state
test data or an instruction is shifted out
via this line.
Used also for serial emulation interface.
2-13
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-8
JTAG and Emulation Interface Pins (DELIC-LC) (Continued)
Pin Symbol
No.
In (I)
During After
Out (O) Reset Reset
Function
55
TRST
I
I
Test Reset
Provides an asynchronous reset to the
TAP controller state machine.
63
DSP_STO
P
O
BOOT O
Strap
(intern
al pulldown)
refer to
Table
2-19
Table 2-9
I
DSP Stop Pin
Stops external logic during breakpoints.
Activated when a stop to the DSP is
issued.
Test Interface Pins (DELIC-LC)
Pin
No.
Symbol
In (I)
During
Out (O) Reset
After
Reset
Function
50
SCANMO
I
I
Scan Mode
If driven to ’1’ during device tests,
TDI input is used as enable for full
scan tests of the DELIC.
SCANMO should be tied to GND
during normal operation.
Preliminary Data Sheet
I
2-14
2003-08
DELIC
PEB 20571
Pin Descriptions
2.4
Pin Definitions and Functions for DELIC-PB
Note: The column “During Reset” refers to the time period that starts with activation of
RESET input and ends with the deactivation of the RESIND output. During this
period, the DELIC’s strap pins (refer to Table 2-19) may be driven by external pulldown or pull-up resistors to define DELIC’s configuration. If external pull-down or
pull-up resistors are not connected to the strap pins, the value of each strap pin
during reset will be determined by an internal pull-up or pull-down resistor,
according to the default strap value of each pin.
The user must ensure that connected circuits do not influence the sampling of the
strap pins during reset.
The column “After Reset” describes the behavior of every pin, from the
deactivation of the RESIND output until the DELIC’s registers are programmed.
Table 2-10
IOM®-2 Interface Pins (DELIC-PB)
Pin
No.
Symbol
In (I)
During
Out(O) Reset
After
Reset
Function
39
FSC
O
O
O
Frame Synchronization Clock (8 kHz)
Used for both the IOM-2 and the IOM2000 interface
40
DCL
O
O
TESTStrap (3),
(internal
pull-up),
refer to
Table 2-19
IOM-2 Data Clock 2.048 MHz or 4.096
MHz
43
DD0
O(OD)
High Z
High Z Data Downstream IOM-2 Interface
Channel0
44
DD1
O(OD)
High Z
High Z Data Downstream IOM-2 Interface
Channel1
41
DU0
I
I
I
Data Upstream IOM-2 Interface
Channel 0
42
DU1
I
I
I
Data Upstream IOM-2 Interface
Channel 1
45
DRDY
I
I
I
D- Channel Ready
Stop/Go information for D-channel
control on S/T interface in LT-T.
Affects only IOM-2 port 0.
DRDY = 1 means GO
DRDY = 0 means STOP
Preliminary Data Sheet
2-15
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-11
IOM-2000 Interface / LNC Port 1 (DELIC-PB)
Pin
No.
Symbol
70
DCL_2000 / O
69
68
67
64
In (I)
During After
Out (O) Reset Reset
LTSC1/
LRTS1
O
DX /
O
LTxD1
O (OD)
DR /
I
LRxD1
I
CMD /
O
LCLK1
I/O
STAT /
I
LCxD1/
LCTS1
I
Preliminary Data Sheet
O
O
Function
IOM-2000 Data Clock
3.072, 6.144 or 12.288 MHz
LNC1 Tristate Control /Request to
Send
2 modes per S/W selectable:
1) TxD output is valid (HDLC mode).
Supplies a control signal for an
external driver. (’low’ when the
corresponding TxD-output is valid).
2) ’request-to-send’ functionality
(Async mode)
High Z
High Z
Data Transmit
Transmits IOM-2000 data to VIP
LNC Transmit Serial Data Port 1
(HDLC and Async mode).
I
I
Data Receive
Receives IOM-2000 data from VIP
LNC Receive Serial Data Port 1
(HDLC and Async mode).
High Z
High Z
IOM-2000 Command
Transmits DELIC commands to VIP.
LNC Clock Port 1.
When configured as output may be
driven at the following frequencies:
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
I
I
IOM-2000 Status
Receives status information from VIP.
LNC1 Collision Data / Clear to Send
1) Collision Data (HDLC Mode).
2) ’clear-to-send’ functionality (Async
mode)
2-16
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-12
LNC Port 0 (DELIC-PB)
Pin
No.
Symbol In (I)
During
Out (O) Reset
After
Reset
Function
62
LRxD0
I
I
I
LNC Receive Serial Data Port 0
(HDLC and Async mode).
61
LTxD0
O (OD)
High Z
High Z LNC Transmit Serial Data Port 0
(HDLC and Async mode).
60
LTSC0 / O
LRTS0
PLLBypass”
strap.
Internal
pull-up
refer to
page 228
H
I
I
59
LCxD0 / I
LCTS0
LNC0 Tristate Control / Request to Send
2 modes per S/W selectable:
1) TxD output is valid (HDLC mode).
Supplies a control signal for an external
driver. (’low’ when the corresponding
TxD-output is valid).
2) ’request-to-send’ functionality
(Async mode)
LNC0 Collision Data / Clear to Send
2 modes per S/W selectable:
1) Collision Data (HDLC Mode).
2) ’clear-to-send’ functionality
(Async mode)
56
LCLK0
I/O
Preliminary Data Sheet
I
I
LNC Clock Port 0
When configured as output may be
driven at the following frequencies:
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
2-17
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-13
Microprocessor Bus Interface Pins (DELIC-PB)
Pin
No.
Symbol In (I)
During
Out (O) Reset
After
Reset
Function
25
24
23
22
21
18
17
16
D7
D6
D5
D4
D3
D2
D1
D0
I/O
The direction of these pins
depends on the value of the
following pins:
CS, RD/DS, WR / R/W and
MODE
Data Bus
38
35
A6
A5
I
Address Bus (bits 6 ... 0 except bit 4)
33
32
31
30
A3
A2
A1
A0
34
A4
DACK/
I
I
Note: When operated in address/data
multiplex mode, this bus is used
as a multiplexed AD bus. The
Address pins are externally
connected to the AD bus.
Note: When operated in address/data
multiplex mode, this bus is used
as a multiplexed AD bus. The
Data
pins
are
externally
connected to the AD bus.
Note: In non-DMA mode DACK/A4
input pin should be connected to
A4 of the µP address-bus. In
DMA mode A4 is internally
connected to ‘0’.
I
I
I
DMA Acknowledge
Bit 4 of the address bus, when the
DELIC is configured to non-DMA mode.
Note: In DMA mode A4 is internally
connected to ‘0’.
11
DREQR O
Preliminary Data Sheet
L
CLOCK
MASTER
Strap
(internal
pull-down),
refer to
Table 2-19
DMA Request for Receive Direction
Note: May be configured to active high
or active low (the default is active
high)
2-18
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-13
Microprocessor Bus Interface Pins (DELIC-PB) (Continued)
Pin
No.
Symbol In (I)
During
Out (O) Reset
10
DREQT O
After
Reset
Function
EMULL
ATION
BOOT
Strap
(internal
pull-down),
refer to
Table 2-19
DMA Request for Transmit Direction
Note: May be configured to active high
or active low (the default is active
high)
12
CS
I
I
I
Chip Select
A "low" on this line selects all registers
for read/write operations.
13
WR/
I
I
I
Write (Intel/Siemens Mode)
Indicates a write access.
Read/Write (Motorola Mode)
Indicates the direction of the data
transfer
R/W
14
RD/
I
I
I
Read (Intel/Siemens Mode)
Indicates a read access.
DS
Data Strobe (Motorola Mode)
During a read cycle, DS indicates that
the DELIC should place valid data on
the bus. During a write access, DS
indicates that valid data is on the bus.
15
ALE
I
I
I
Address Latch Enable
Controls the on-chip address latch in
multiplexed bus mode. While ALE is
’high’, the latch is transparent. The
falling edge latches the current
address. ALE is also evaluated to
determine
the
bus
mode
(’low’=multiplexed,
’high’=demultiplexed)
7
MODE
I
I
I
Bus Mode Selection
Selects the µP bus mode
(’low’=Intel/Infineon, ’high’=Motorola)
Preliminary Data Sheet
2-19
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-13
Microprocessor Bus Interface Pins (DELIC-PB) (Continued)
Pin
No.
Symbol In (I)
During
Out (O) Reset
After
Reset
6
IREQ
O
(OD)
High Z
(OD)
High Z Interrupt Request is programmable to
(OD)
push/pull (active high or low) or opendrain. This signal is activated when the
DELIC requests a µP interrupt. When
operated in open drain mode, multiple
interrupt sources may be connected.
5
IACK
I
I
I
Interrupt Acknowledge
29
RESET
I
I
I
System Reset
DELIC is forced to go into reset state.
89
RESIND O
O
O
Reset Indication
Indicates that the DELIC is executing a
reset. The DELIC remains in reset
state for at least 500 µs after the
termination of the RESET pulse.
Table 2-14
Function
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB)
Pin Symbol In (I)
During
No.
Out (O) Reset
After
Reset
Function
87
PFS
I/O
I
I
PCM Frame Synchronization Clock.
8 kHz/4 kHz when input or 8 kHz when
output.
Note: When PFS is configured as 4 kHz
input,
PDC
configuration
is
restricted to 2.048 MHz input.
88
PDC
I/O
I
I
PCM Data Clock (input or output)
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
76
RxD0 /
I
I
I
PCM Receive Data Port 0
LRxD2
I
TxD0 /
O
LTxD2
O(OD)
78
Preliminary Data Sheet
LNC Receive Serial Data Port 2
(HDLC and Async mode)
High
Z
High
Z
PCM Transmit Data Port 0
LNC Transmit Serial Data Port 2
(HDLC and Async mode)
2-20
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-14
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) (Continued)
Pin Symbol In (I)
During
No.
Out (O) Reset
77
74
82
81
TSC0 /
O
LTSC2/
LRTS2
O
RxD2 /
I
LCxD2/
LCTS2
I
TxD2 /
O
LCLK2
I/O
TSC2
O
Preliminary Data Sheet
After
Reset
Function
H
Reset
Counter
Bypass”
strap
Internal
pull-up
refer to
page 228
PCM Tristate Control Port 0
Supplies a control signal for an external
driver (’low’ when the corresponding TxDoutput is valid).
I
PCM Receive Data Port 2
I
LNC2 Tristate Control / Request To Send
2 modes per S/W selectable:
1) TxD output is valid (HDLC mode).
Supplies a control signal for an external
driver. (’low’ when the corresponding TxDoutput is valid).
2) ’request-to-send’ functionality
(Async mode)
LNC2 Collision Data
2 modes per S/W selectable:
1) Collision Data (In HDLC Mode).
2) ’clear-to-send’ functionality
(Async mode)
weak
low
weak
low
PCM Transmit Data Port 2
LNC External Clock Port 2
When configured as output may be driven
at the following frequencies:
2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz
TEST(1) H
strap
refer to
page 228
PCM Tristate Control Port 2
Supplies a control signal for an external
driver (’low’ when the corresponding TxDoutput is valid).
2-21
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-14
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) (Continued)
Pin Symbol In (I)
During
No.
Out (O) Reset
After
Reset
Function
75
I
PCM Receive Data Port 1
80
79
RxD1 /
I
LRxD3
I
TxD1 /
O
LTxD3
O(OD)
TSC1 /
O
LTSC3/
LRTS3
71
RxD3 /
I
LCxD3/
LCTS3
I
Preliminary Data Sheet
I
LNC Receive Serial Data Port 3
(HDLC and Async mode)
High
Z
High
Z
PCM Transmit Data Port 1
LNC Transmit Serial Data Port 3
(HDLC and Async mode)
H
PLL
PowerDown
strap
Internal
pull-up
refer to
page 228
PCM Tristate Control Port 1
Supplies a control signal for an external
driver (’low’ when the corresponding TxDoutput is valid).
I
PCM Receive Data Port 3
I
LNC3 Tristate Control / Request to Send
2 modes per S/W selectable:
1) TxD output is valid (HDLC mode).
Supplies a control signal for an external
driver. (’low’ when the corresponding TxDoutput is valid).
2) ’request-to-send’ functionality
(Async mode)
LNC3 Collision Data
2 modes per S/W selectable:
1) Collision Data (HDLC Mode).
2) ’clear-to-send’ functionality
(Async mode)
2-22
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-14
PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) (Continued)
Pin Symbol In (I)
During
No.
Out (O) Reset
After
Reset
Function
86
weak
low
PCM Transmit Data Port 3
83
TxD3 /
O
LCLK3
I/O
TSC3
O
Preliminary Data Sheet
weak
low
LNC External Clock Port 3
When configured as output may be driven
at the following frequencies: 2.048 MHz,
4.096 MHz, 8.192 MHz, 16.384 MHz
TEST(1) H
strap
refer to
page 228
PCM Tristate Control Port 3
Supplies a control signal for an external
driver (’low’ when the corresponding TxD
output is valid).
2-23
2003-08
DELIC
PEB 20571
Pin Descriptions
.
Table 2-15
Clock Generator Pins (DELIC-PB) (additionally to IOM/PCM clocks)
Pin
No.
Symbol
In (I)
During After
Out (O) Reset Reset
Function
94
CLK16-XI
I
I
I
16.384 MHz External Crystal Input
95
CLK16-XO
O
O
O
16.384 MHz External Crystal Output
1
DCXOPD
I
I
I
DCXO Power Down and Bypass
Activating this input powers down the
on-chip DCXO PLL.
The input CLK16-XI is used directly as
the internal 16.384 MHz clock, and the
oscillator and the shaper are bypassed.
Required for testing; during normal
operation this input should be
permanently low (‘0’).
2
CLK_DSP
I
I
I
External DSP Clock
Provides a DSP clock other than
61.44 MHz from an external oscillator.
3
DSP_FRQ
I
I
I
DSP Operational Frequency Selection
(e.g. for test purpose)
0: The DSP is clocked internally at
61.44 MHz
1: The DSP clock is driven by the
CLK_DSP input pin
48
L1_CLK
O
O
O
Layer-1 Clock
15.36 MHz or 7.68 MHz
28
CLKOUT
O
O
O
General Purpose Clock Output
2.048 MHz, 4.096 MHz, 8.192 MHz,
15.36 MHz or 16.384 MHz
4
XCLK
I
I
I
External Reference Clock
Synchronization input from Layer-1 ICs
(8 kHz, 512 kHz or 1.536 MHz)
This pin is connected to the VIP’s
REFCLK output at 1.536 MHz.
90
REFCLK
I/O
I
I
Reference Clock
Input: Synchronization of DELIC clock
system
Output: Used to drive a fraction of
XCLK to the system clock master
(8 kHz or 512 kHz programmable)
Preliminary Data Sheet
2-24
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-16
Power Supply Pins (DELIC-PB)
Pin
No.
Symbol
In (I)
During After
Out (O) Reset Reset
Function
8
19
26
36
46
49
57
65
72
84
91
VDD
I
I
I
Power Supply 3.3 V
Used for core logic and interfaces in pure
3.3 V environment
9
20
27
37
47
58
66
73
85
92
VSS
I
I
I
Digital Ground (0 V)
96
99
100
VDDA
I
I
I
Power Supply 3.3 V Analog Logic
Used for DCXO and PLL
93
97
98
VSSA
I
I
I
Analog Ground
Used for DCXO and PLL
Preliminary Data Sheet
2-25
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-17
JTAG and Emulation Interface Pins (DELIC-PB)
Pin Symbol
No.
In (I)
During After
Out (O) Reset Reset
Function
Used for boundary scan according to IEEE 1149.1
54
JTCK
I
I
I
JTAG Test Clock
Provides the clock for JTAG test logic.
Used also for serial emulation interface.
53
TMS
I
I
I
Test Mode Select
A ’0’ to ’1’ transition on this pin is
required to step through the TAP
controller state machine.
52
TDI /
I
I
I
Test Data Input
In the appropriate TAP controller state
test data or a instruction is shifted in via
this line.
Used also for serial emulation interface.
Note: This pin must not be driven to low
on the board during reset and
operation to ensure functioning of
DELIC
SCANEN
51
TDO
SCAN Enable
When both SCANMO and SCANEN are
asserted, the full-scan tests of DELIC
are activated.
Not used during normal operation.
O
Preliminary Data Sheet
O
O
Test Data Output
In the appropriate TAP controller state
test data or an instruction is shifted out
via this line.
Used also for serial emulation interface.
2-26
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-17
JTAG and Emulation Interface Pins (DELIC-PB) (Continued)
Pin Symbol
No.
In (I)
During After
Out (O) Reset Reset
Function
55
TRST
I
I
Test Reset
Provides an asynchronous reset to the
TAP controller state machine.
63
DSP_STO
P
O
BOOT O
Strap
(intern
al pulldown)
refer to
Table
2-19
Table 2-18
I
DSP Stop Pin
Stops external logic during breakpoints.
Activated when a stop to the DSP is
issued.
Test Interface Pins (DELIC-PB)
Pin
No.
Symbol
In (I)
During
Out (O) Reset
After
Reset
Function
50
SCANMO
I
I
Scan Mode
If driven to ’1’ during device tests,
TDI input is used as enable for full
scan tests of the DELIC.
SCANMO should be tied to GND
during normal operation.
Preliminary Data Sheet
I
2-27
2003-08
DELIC
PEB 20571
Pin Descriptions
2.5
Strap Pin Definitions
Table 2-19
Strap Pins (Evaluated During Reset)
Pin No.
Strap Name Strap Function
DREQR
(11)
CLOCK
MASTER
Clock Slave
0:
(default) PDC and PFS are used as inputs.
PDC = 2.048 MHz
PFS = 4 kHz
1:
DSP_STOP BOOT
(63)
0:
The DSP starts running from address FFFEH,
(default) and executes the µP boot routine.
1:
DCL (40):
TSC3 (83):
TSC2 (81)
DREQT
(10)
TEST
(3:1)
The DSP starts running directly from address
0000H. The boot routine is not executed.
111 or
Regular Work Mode
110:
(default)
101
Test mode 1
100
Test mode 2
011
Test mode 3
010
Test mode 4
001
Test mode 5
After reset the boot-routine loads the program
EMULATION 0:
BOOT
(default) RAM via the µP-interface (via the general mailbox).
1:
LTSC
(60)
Clock Master
PDC and PFS are used as outputs.
PDC = 2.048 MHz
PFS = 8 kHz
PLL
BYPASS
0:
After reset the boot-routine loads
the program RAM via the CDI mail-box (via the
JTAG interface).
DSP_CLK input pin (the DSP fall-back clock) is
used as source for the 61 MHz clock division
chain. (Only for testing).
1:
The PLL output is used as the source for the
(default) 61 MHz clock division chain.
Preliminary Data Sheet
2-28
2003-08
DELIC
PEB 20571
Pin Descriptions
Table 2-19
Strap Pins (Evaluated During Reset) (Continued)
TSC1
(79)
The PLL is powered-down. (for IDDQ tests)
PLL POWER 0:
DOWN
1:
The PLL is on.
(default)
TSC0
(77)
RESET
COUNTER
BYPASS
0:
The reset-counter is bypassed, thus the internal
reset is the filtered reset. The internal reset lasts
1-2 16 MHz cycles after a deactivation of
RESET.
The internal reset lasts 4-5 8 kHz cycles (>
1:
(default) 500 µs) after a deactivation of RESET
Note: When the strap pins are not driven externally during reset, they are driven by
internal pull-ups/pull-downs. To reduce power consumption, the internal pull-up/
pull-down resistors are connected only during activated RESET input.
To ensure the default value of the straps, the pins must not be driven during reset.
In case of fixed external pull-up/pull-down, a pull-up/pull-down resistance of
10 KΩ +/-10% is recommended.
Preliminary Data Sheet
2-29
2003-08
DELIC
Interface Description
3
Interface Description
3.1
Overview of Interfaces
The DELIC provides the following system interfaces:
IOM-2000 Interface
• A new serial layer 1 interface driving up to three VIP/ VIP8 (Versatile ISDN Port, PEB
20590/ PEB 20591). Each VIP provides eight 2B+D ISDN channels, which can be
programmed via IOM-2000 to S/T mode or UPN mode.
IOM-2 (GCI) Interface
• Two standard IOM-2 (GCI) ports with eight 2B+D ISDN channels each, at a data rate
of up to 2 x 2.048 Mbit/s. They can be combined to a 4.096 Mbit/s highway.
PCM Interface
• Four standard Master/Slave PCM interfaces with up to 32 time slots each, at a data
rate of up to 4 x 2.048 Mbit/s. They can be combined to two 4.096 Mbit/s highways or
one 8.192 Mbit/s highway. Additionally, 128 time slots of 256 time slots per 8 kHz
frame can be transmitted at a rate of 16.384 Mbit/s.
Serial Communication Interface (GHDLC)
• An asynchronous serial port supporting HDLC formatted data frames at a data rate of
up to 16.384 Mbit/s.
Microprocessor Interface
• A standard 8-bit multiplexed/de-multiplexed µP interface, compatible to Intel/Siemens
(e.g. 80386EX, C166) and Motorola (e.g. 68340, 801) bus systems. It includes two
separate mailboxes, one for normal data transfer, and one for fast DMA transfers.
JTAG Boundary Scan Test Interface
• DELIC provides a standard test interface according to IEEE 1149.1. The 4-bit TAP
controller has an own reset input.
• The JTAG pins TDI, TDO and JTCK may also be used as interface for DSP emulation.
Preliminary Data Sheet
3-1
2003-08
DELIC
Interface Description
3.2
IOM-2000 Interface
3.2.1
Overview
The IOM-2000 interface represents a new concept for connecting ISDN layer-1 devices
to the DELIC. The transceiver unit (TRANSIU) and the DSP perform the layer-1 protocol,
which enables flexible and efficient operation of the transceiver IC (VIP/ VIP8).
VIP/ VIP8 supports two types of ISDN interfaces: 2-wire (ping-pong) UPN interfaces and
4-wire S/T interfaces. For detailed description please refer to VIP/ VIP8 Data Sheet.
The IOM-2000 interface consists of the following signals:
• Frame Synchronization: IOM-2000 uses the same 8 kHz FSC as the IOM-2 ports.
• Data Interface: Data is transmitted via DX line from DELIC to VIP with DCL_2000
rising edge. Data is received via DR line from VIP to DELIC, sampled with DCL_2000
falling edge.
• Command/Status Interface: Configuration and control information of VIP’s layer-1
transceivers is exchanged via CMD and STAT lines.
• Data/Command Clock: Data and commands for one VIP are transmitted at
3.072 MHz. When DELIC drives 2 or 3 VIPs, the transmission rate is increased.
• Reference Clock: In LT-T mode, the VIP provides a reference clock synchronized to
the exchange. In LT-S or UPN mode, DELIC is always the clock master to VIP.
S/T:
bit 1 bit 0
data ctrl
Data Transmit / Receive in S/T mode
f=3.072 MHz (2 x 8 x 192 kbit/s)
UPN:
bit 0
data
Data Transmit / Receive for UPN mode
f=3.072 MHz (8 x 384 kbit/s)
DX / DR:
FSC
Channel_0
.
.
.
DCL_2000
DX
VIP
DR
PEB 20590
DELIC
PEB 20570
STAT
Channel_7
Figure 3-1
CMD
Overview of IOM-2000 Interface Structure (Example with One VIP)
Preliminary Data Sheet
3-2
2003-08
DELIC
Interface Description
3.2.2
IOM-2000 Frame Structure
3.2.2.1
Data Interface
On the ISDN line side of the VIP, data is ternary coded. Since the VIP contains logic to
detect the level of the signal, only the data value is transferred via IOM-2000 to DELIC.
UPN Mode
• In UPN mode, only data is sent via the IOM-2000 data interface.
S/T Mode
• In S/T mode, data and control information is sent via IOM-2000 data interface. Every
data bit has a control bit associated with it. Thus, for each S/T line signal, 2 bits are
transferred via DX and DR. Bit0 is assigned to the user data, and bit1 carries control
information.
Table 3-1
Control Bits in S/T Mode on DR Line
ctrl (bit1) data (bit0) Function
0
0
Logical ’0’ received on line interface
0
1
Logical ’1’ received on line interface
1
0
Received E-bit = inverted transmitted D-bit (E=D) (LT-T only)
1
1
F-bit (Framing) received; indicates the start of the S frame
Table 3-2
Control Bits in S/T Mode on DX Line
ctrl (bit1) data (bit0) Function
0
0
Logical ’0’ transmitted on line interface
0
1
Logical ’1’ transmitted on line interface
1
0
not used
1
1
F-bit (Framing) transmitted; indicates the start of the S frame
Note: ’data’ is always transmitted prior to ’ctrl’ via DX/DR lines (refer to Figure 3-2).
Preliminary Data Sheet
3-3
2003-08
DELIC
Interface Description
FSC
125 µs
DCL
3.072 MHz
F-bit
data ctrl
LT-S mode:
Ch0 bit0
Ch1 bit0 (data)
Ch2 bit0
UPN mode:
data
Ch7 bit0 (data)
DX/DR
Ch0 bit1
Ch1 bit0 (ctrl)
Ch2 bit1
Ch7 bit0 (ctrl)
Ch1,3,5,7 in S mode (LT-S)
Ch0,2,4,6 in UPN mode
Ch0 bit2
Ch1 bit1 (data)
Ch2 bit2
Ch7 bit1 (data)
last bit of UPN frame
Ch6 bit37
last bit of LT-S frame
Figure 3-2
Ch7 bit 23 (ctrl)
IOM-2000 Data Sequence (1 VIP with 8 Channels)
Note: 1. Data transfer on IOM-2000 interface always starts with the MSB (related to B
channels), whereas CMD and STAT bits transfer always starts with LSB (bit 0)
of any register
2. All registers follow the Intel structure (LSB=20, MSB=231)
3. Unused bits are don’t care (’x’)
4. The order of reception or transmission of each VIP channel is always
channel 0 to channel 7. A freely programmable channel assignment of multiple
VIPs on IOM-2000 (e.g., ch0 of VIP_0, ch1 of VIP_0, ch0 of VIP_1, ch2 of
VIP_0, ...) is not possible.
Preliminary Data Sheet
3-4
2003-08
DELIC
Interface Description
125 µs
FSC
DCL
12.288 MHz
F-bit
Ch0 bit0
Ch23 bit0
Ch24 bit0
not used (don’t care)
DX/DR
Ch31 bit0
Ch0 bit1
Ch23 bit1
Ch24 bit1
not used (don’t care)
Ch31 bit1
Ch0 bit37
(example for 24 channels in UPN mode)
Ch23 bit37
Ch24 bit37
not used
Ch31 bit37
Figure 3-3
IOM-2000 Data Order (3 VIPs with 24 Channels)
Receive Data Channel Shift
In receive direction (DR), data of all IOM-2000 channels (ch0...7 if one VIP is used,
ch0 ... ch23 if three VIPs are used) is shifted by 2 channels with respect to the
transmitted data channels (DX), assuming a start of transmission of ch0 bit0 with the
FSC signal. DELIC is transmitting ch0, while receiving ch2 via DR the same time, etc.
DX
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
ch0
DR
ch2
ch3
ch4
ch5
ch6
ch7
ch0
ch1
ch2
Preliminary Data Sheet
3-5
2003-08
DELIC
Interface Description
3.2.2.2
Command and Status Interface
The CMD and STAT lines are the configuration and control interface between DELIC and
VIP. The bit streams are partitioned into 32-bit words carrying information dedicated to
the VIPs (CMD_0 / STAT_0) followed by information dedicated to the individual
channels of the same VIP (CMD_0_0 ... CMD_2_7 or STAT_0_0 ... STAT_2_7).
Note: As opposed to data, command and status bits are sent channel-wise, starting with
channel_0. The transmission clock is the same as the DR/DX data clock.
FSC
125 µs
DCL
3.072 MHz
3x32-bit empty
C_0C0 C_0C1 C_0C2 C_0C3 C_0C4 C_0C5 C_0C6 C_0C7
C_0
CMD
0 1 2
Command bits to VIP_0
C_0
...
31
0
1
2
31
Commands bits to VIP_0 channel_7
3x32-bit empty
S_0 ...
S_0 S_0C0 S_0C1 S_0C2 S_0C3 S_0C4 S_0C5 S_0C6 S_0C7
STAT
1
0
2
31
Status bits of VIP_0
0
1
2
31
Status bits of VIP_0 channel_7
Note: C_0 refers to CMD_0, S_0 to STAT_0 C_0C0 refers to CMD_0_0, S_0C0 to STAT_0_0
Figure 3-4
IOM-2000 CMD/STAT Handling (1 VIP with 8 Channels)
Note: The position of each VIP within the IOM-2000 frame is programmable by two VIP
pins (VIP_ADR0, VIP_ADR1) to IOM-2000 channels 0..7, 8..15 or 16..23.
FSC
CMD /
STAT
125 µs
3 empty
32-bit words
3 empty
32-bit words
VIP_0
VIP_1
3 empty
32-bit words
VIP_2
VIP_0
...
VIP_0 ch0
Figure 3-5
ch7
VIP_1 ch0
VIP_2 ch0
ch7
ch7
reserved
IOM-2000 Command/Status Sequence (3 VIPs with 24 Channels)
Preliminary Data Sheet
3-6
2003-08
DELIC
Interface Description
Commands to VIP_n (CMD_n, n = 0 ... 2)
Initialization and control information for each VIP is sent by DELIC in the following
sequence every 125 µs via the IOM-2000 CMD line (32 CMD_n bits per VIP_n):
Note: All bits are programmed in VIP Command register (VIPCMR0..2).
31
24
x
x
x
x
x
x
x
23
x
16
x
x
x
x
x
x
x
15
x
8
x
x
x
x
RD_n
PLLPPS
SH_FSC
7
0
DELCH(2:0)
CMD_n
DELRE
EXREF
REFSEL(2:0)
WR_n
Commands to VIP_n, Channel_m (CMD_n_m, m = 0 ... 7)
Initialization and control information for each VIP channel is sent by DELIC in the
following sequence every 125 µs via the IOM-2000 CMD line (32 CMD_n_m bits per
VIP_n Channel_m):
Note: All bits except WR_ST, SMINI(2:0) and MSYNC are programmed in TRANSIU
Initialization Channel Command register (TICCR);
bits WR_ST, SMINI(2:0) and MSYNC reside in the TRANSIU Tx data RAM.
31
24
FIL
CMD_n_m
SMINI(2:0)
MSYNC
EXLP
PLLS
23
PD
16
x
DHEN
x
x
PDOWN LOOP TX_EN PLLINT
15
8
AAC(1:0)
BBC(1:0)
OWIN(2:0)
MF_EN
7
0
MODE(2:0)
Preliminary Data Sheet
MOSEL(1:0)
3-7
WR_ST
RD
WR
2003-08
DELIC
Interface Description
Status from VIP_n (n = 0 ... 2)
Status information is sent by each VIP in the following sequence via the STAT line
(32 STAT_n bits per VIP_n):
31
24
x
STAT_n
x
x
x
x
x
x
23
x
16
x
x
x
x
x
x
x
15
x
8
x
x
x
x
x
x
x
7
x
0
DELAY(7:0)
Note: Bits DELAY are read from VIP Status register (VIPSTR) in TRANSIU. x = unused
Status from VIP_n, Channel_m (m = 0 ... 7)
Status information is sent by each VIP channel in the following sequence via the STAT
line (32 STAT_n_m bits per VIP_n Channel_m):
31
24
x
STAT_n_m
x
x
x
x
x
x
23
x
16
x
x
x
x
x
x
x
15
x
8
x
x
x
x
x
x
7
x
x
0
x
MSYNC* FCV*
FSYNC*
SLIP
FECV
RxSTA(1:0)
Note: Marked bits (*) are not evaluated by the DELIC, only for VIP testing.
Bits SLIP, FECV and are directly accessible in the TRANSIU receive data RAM.
x = unused
Preliminary Data Sheet
3-8
2003-08
DELIC
Interface Description
3.2.3
UPN State Machine
3.2.3.1
INFO Structure on the UPN Interface
Signals controlling and indicating the internal state of all UPN transceiver state machines
are called INFOs. Four different INFOs (INFO 0, 1W, 1, 2, 3, 4) may be sent over the UPN
interface, depending on the actual state (Synchronized, Activated, Pending Activation,
...). When the line is deactivated, INFO 0 (=no signal on the line) is exchanged by the
UPN transceivers at either end of the line.
When the line is activated, INFO 3 (in upstream direction) and INFO 4 (in downstream
direction) are continuously sent. INFO 3 and 4 contain the transmitted data (B1, B2, D,
M). INFO 1/2 are used for activation and synchronization.
Table 3-3
INFO Structure on UPN Interface
Name
Direction
INFO 0
Upstream
No signal on the line
Downstream
INFO 1W
Upstream
Asynchronous Wake Signal
4 kHz burst rate
F0001000100010001000101010100010111111
Code violation in the framing bit
INFO 1
Upstream
4 kHz burst rate
F000100010001000100010101010001011111M1)DC
Code violation in the framing bit
INFO 2
Downstream 4 kHz burst rate
F000100010001000100010101010001011111M1)
Code violation in the frame bit
INFO 3
Upstream
INFO 4
Downstream 4 kHz burst rate
No code violation in the framing bit
User data in B, D and M channels
B channels scrambled, DC bit2) optional
Note:
1)
2)
Description
4 kHz burst rate
No code violation in the framing bit
User data in B, D and M channels
B channels scrambled, DC bit2) optional
The M channel superframe contains:
CV code violation
[1 kbit/s (once in every fourth frame)]
S bits transparent
[1 kbit/s channel]
T bits transparent
[2 kbit/s channel]
DC balancing bit;
F = Framing bit
Preliminary Data Sheet
3-9
2003-08
DELIC
Interface Description
3.2.3.2
UPN Mode State Diagram
TIM
TM1
TM2
TIM
Reset
Test Mode
it1
it2
TIM
i0
*
DR
TM1
TM2
Pend. Deact.
i0
i0
*
DR
DR
RESET
RES
RES
DC
i0
DI
DR
ARx
G4 Wait for DR
i0
i0
DC
DI
DC
Deactivated
DR
i0
i0
i1w
AR
DC
ARx
DR
Pend. Act.
i2
i1w
Note:
TM2 = Send Continuous Pulses
TM1 = Send Single Pulses
it1 = test signal invoked by TM1
it2 = test signal invoked by TM2
ARx = AR, AR2
Uncond. Transitions by: RES, TM1, TM2, DR
i1
UAI
DC
ARx, AI
DR
Synchronized
i1
RSY
DC
ARx
Resynchron.
i2
i1, i3
i4
i1
i3
DR
µP interface
i1
OUT
IN
Ind.
Cmd.
State
AI
i3
DC
ARx, AI
Activated
ix
DR
iy
Upn interface
DELPHI UP SM.vsd
i4
Figure 3-6
i3
UPN State Diagram
Preliminary Data Sheet
3-10
2003-08
DELIC
Interface Description
The UPN state machine has unconditional and conditional states (refer to Figure 3-6):
Unconditional States
Reset
This state is entered unconditionally after a low appears on the RESET pin or after the
receipt of command RES (software reset). The analog transceiver part is disabled
(transmission of INFO 0) and the UPN interface awake detector is inactive. Hence,
activation from terminal (TE) is not possible.
Test Mode
The test signal (iti) sent to the UPN interface in this state is dependant on the command
which originally invoked the state. TM1 causes single alternating pulses to be
transmitted (it1); TM2 causes continuous alternating pulses to be transmitted (it2). The
burst mode technique normally employed on the UPN interface is suspended in this state
and the test signals are transmitted continuously.
Pending Deactivation
To access any of the conditional states from any of the above unconditional states, the
pending deactivation state must be entered. This occurs after the receipt of a DR
command. In this state the awake detector is activated and the state is left only when the
line has settled (i.e., INFO 0 has been detected for 2 ms) or by the command DC.
Note: Although DR is shown as a normal command, it may be seen as an unconditional
command. No matter which state the LT is in, the reception of a DR command will
always result in the pending deactivation state being entered.
Conditional States
Wait for DR
This state is entered from the pending deactivation state once INFO 0 or DC has been
identified. From here the line may be either activated, deactivated or a test loop may be
entered.
Deactivated
This is the power down state of the physical protocol. The awake detection is active and
the device will respond to an INFO 1w (wake signal) by initiating activation.
Preliminary Data Sheet
3-11
2003-08
DELIC
Interface Description
Pending Activation
This state results from a request for activation of the line, either from the terminal
(INFO 1w) or from the layer-2 device (AR, AR2). INFO 2 is then transmitted and the DSP
waits for the responding INFO 1 from the remote device.
Synchronized
This state is reached after synchronization upon the receipt of INFO 1, i.e. after a
maximum of 10 ms. In this state, INFO 2 is supplied to the remote terminal for
synchronization.
Activated
Info 1 has a code violation in the framing bit (F-bit), whereas INFO 3 has none. Upon the
reception of two frames without a code violation in the F bit, the activated state is entered
and INFO 4 is transmitted. The line is now activated; INFO 4 is sent to the remote and
INFO 3 is received from the remote.
Re synchronization
If the recognition of INFO 3 fails, the receiver will attempt to resynchronize. Upon
entering this state, INFO 2 is transmitted. This is similar to the original synchronization
procedure in the pending activation state (the indication given to layer 2 is different).
However, as before, recognition of INFO 1 leads to the synchronized state.
Table 3-4
UPN State Machine Codes
Command
Abbr.
Code
Remark
Deactivate request
DR
0000
Initiates a complete deactivation from the
exchange side by transmitting INFO 0 (x)
Reset
RES
0001
(x)
Test mode 1
TM1
0010
Transmission of pseudo-ternary pulses at
2 kHz frequency (x)
Test mode 2
TM2
0011
Transmission of pseudo-ternary pulses at
192 kHz frequency (x)
Activate request
AR
1000
Used to start an exchange initiated
activation
1010
Transmission of INFO 2, switching of loop
2 (at TE), T bit set to one
Activate request test AR2
loop 2
Preliminary Data Sheet
3-12
2003-08
DELIC
Interface Description
Table 3-4
UPN State Machine Codes (Continued)
Command
Abbr.
Code
Remark
Activate indication = AI
"blocked"
1100
Transmission of INFO 4, T bit set to zero
Deactivate
confirmation
1111
Deactivation acknowledgement, quiescent
state
DC
(x) unconditional commands
Note: The UPN state machine does not support loops. So neither C/I commands nor
Indications are provided by the mailbox protocol.
An loop can be programmed by setting bits TICCMR:LOOP and TICCMR:EXLP
for the respective channel.
Indication
Abbr.
Code
Remark
Timing
TIM
0000
Deactivate state, activation from the line
not possible
Resynchronizing
RSY
0100
Receiver is not synchronous
Activate request
AR
1000
INFO 1w received
U only activation
indication
UAI
0111
INFO 1 received, synchronous receiver
Activate indication
AI
1100
Receiver synchronous, i.e., activation
completed
Deactivate indication DI
1111
INFO 0 or DC received after deactivation
request
Preliminary Data Sheet
3-13
2003-08
DELIC
Interface Description
3.2.4
S/T State Machine
A finite state machine in the DELIC controls the VIP S/T line activation/deactivation
procedures and transmission of special pulse patterns. Such actions can be initiated by
primitives (INFOs) on the S/T interface or by C/I codes sent via the mailbox.
Depending on the application mode and the transfer direction, the S/T state machines
support different codes in conditional and unconditional states:
LT-S mode
Codes:
data downstream = Commands: reset, test mode, activate req, ..
data upstream = Indications: not sync, code violation, timer out, ..
deactivated, activated, pending, lost framing, test mode
States:
The state diagram is shown in Figure 3-7.
LT-T mode
Codes
data upstream
= Commands: reset, test, activate request,..
data downstream = Indications: command x acknowledged,..
Conditional states: power up, pending deactivation, synchronized, slip detected,..
The state diagram is shown in Figure 3-8.
Unconditional states may be entered from any conditional state and should be left with
the command TIM: test mode, reset state,..
The S/T layer-1 activation and deactivation procedures implemented in the DELIC are
similar to the ones implemented in the PEB 2084, QUAT-S.
3.2.4.1
LT-S Mode
Table 3-5
LT-S State Machine Codes
Command
Abbr.
Code
Remark
Deactivate request
DR
0000
Initiates a complete deactivation from the
exchange side by transmitting INFO 0 (x)
Reset
RES
0001
(x)
Test mode 1
TM1
0010
Transmission of pseudo-ternary pulses at
2 kHz frequency (x)
Test mode 2
TM2
0011
Transmission of pseudo-ternary pulses at
96 kHz frequency (x)
Preliminary Data Sheet
3-14
2003-08
DELIC
Interface Description
Table 3-5
LT-S State Machine Codes (Continued)
Command
Abbr.
Code
Remark
Activate request
AR
1000
Used to start an exchange initiated
activation
Deactivate confirmation
DC
1111
Deactivation acknowledgement,
quiescent state
(x) unconditional commands
Note: The LT-S state machine does not support loops. So neither C/I commands nor
Indications are provided by the mailbox protocol.
A loop can be programmed by setting bits TICCMR:LOOP and TICCMR:EXLP for
the respective channel.
Indication
Abbr.
Code
Timing
TIM
0000
Resynchronizing
RSY
0100
Receiver is not synchronous
Activate request
AR
1000
INFO 0 received
Code violation received
CVR
1011
After each multi-frame the reception of at
least one illegal code violation is
indicated four times
Activate indication
AI
1100
Receiver synchronous, i.e., activation
completed
Deactivate indication
DI
1111
Timer (32 ms) expired or INFO 0
received after deactivation request
Preliminary Data Sheet
Remark
3-15
2003-08
DELIC
Interface Description
RESET
TIM
TIM
RES
TIM
DR
DR
Reset
i0
RES
DR
G4 Pend. Deact.
i0
*
ARD1)
DC
Any State
DI
Test Mode
it1
it2
i0
DC
i0 or 32ms
SCP
SSP
*
SCP
SSP
Any State
DR
G4 Wait for DR
ARD1)
i0
*
DC
DI
DC
DR
G1 Deactivated
ARD1)
i0
i0
i0
AR
DC
AR
DR
G2 Pend. Act.
i2
i3
Note:
i3
AR
TM2 = Send Continuous Pulses
TM1 = Send Single Pulses
it1 = test signal invoked by TM1
it2 = test signal invoked by TM2
DC
AR
G3 Activated
E=D
i4
i3
i3
RSY
i3
i3
DELPHI LT-S SM.vsd
Figure 3-7
µP
interface
DC
AR
G2 Lost Framing
i2
DR
DR
OUT
IN
Ind.
Cmd.
State
S interface
ix
iy
State Diagram of LT-S Mode
Preliminary Data Sheet
3-16
2003-08
DELIC
Interface Description
LT-S Mode States
• G1 deactivated
The line interface is not transmitting. There is no signal detected on the S interface,
and no activation command is received.
• G2 pending activation
As a result of an INFO 1 detected on the S line or an AR command, the line interface
begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise
reception of INFO 3 is to be implemented in software. In case of an ARL command,
loop 2 is closed.
• G3 activated
Normal state where INFO 4 is transmitted to the S interface. The line interface
remains in this state as long as neither a deactivation nor a test mode is requested,
and the receiver does not loose synchronism. When receiver synchronism is lost,
INFO 2 is sent automatically. After reception of INFO 3, the transmitter continues
sending INFO 4.
• G2 lost framing
This state is reached when the line interface has lost synchronism in the state G3
activated.
• G4 pending deactivation
This state is triggered by a deactivation request DR. It is an unstable state: status DI
(state “G4 wait for DR”) is issued by the DELIC when either INFO 0 is received, or an
internal timer of 32 ms expires.
• G4 wait for DR
Final state after a deactivation request. The line interface remains in this state until a
response to DI (in other words DC) is issued.
• Test mode 1
Single alternating pulses are sent on the S interface (2 kHz repetition rate).
• Test mode 2
Continuous alternating pulses are sent on the S interface (96 kHz).
Preliminary Data Sheet
3-17
2003-08
DELIC
Interface Description
3.2.4.2
LT-T Mode
Table 3-6
LT-T Mode State Machine Codes (Conditional States)
Command
Abbr. Code
Remark
Timing Request
TIM
0000
Requests the line interface to change into
power-up state
Reset
RES
0001
Reset of state machine. Transmission of
Info 0. No reaction to incoming infos (x)
Test mode 1
TM1
0010
Transmission of single pulses on the S/Tinterface. The pulses are transmitted with
alternating polarity at a frequency of
2 kHz. (x)
Test mode 2
TM2
0011
Transmission of continuous pulses on the
S/T-interface. The pulses are sent with
alternating polarity at a rate of 96 kHz.
TM2 is an unconditional command (x).
Activate request, priority 8 AR8
1000
Activation Request with priority 8 for Dchannel transmission. This command is
used to start a LT-T initiated activation.
D-channel priority 8 is the highest priority.
It should be used to request signaling
information transfer.
Activate request, priority
10
AR10 1001
Activation request with priority 10 for Dchannel transmission. This command is
used to start a LT-T initiated activation.
D-channel priority 10 is a lower priority. It
should be used to request packet data
transfer.
Deactivate indication
DI
This command forces the line interface
into “F3 power down” mode.
1111
(x) unconditional commands
Note: The LT-T state machine does not support loops. So neither C/I commands nor
Indications are provided by the mailbox protocol.
A loop can be programmed by setting bits TICCMR:LOOP and TICCMR:EXLP for
the respective channel.
Preliminary Data Sheet
3-18
2003-08
DELIC
Interface Description
Indication
Abbr. Code
Remark
Deactivate request
DR
0000
Deactivation request if left from F7/F8
Reset
RES
0001
Reset acknowledge
Test mode 1
TM1
0010
TM1 acknowledge
Test mode 2
TM2
0011
TM2 acknowledge
Slip detected
SLIP
0011
Frame wander larger than +/- 25 µs
Resynchronization during
level detect
RSY
0100
Signal received, receiver not synchronous
Power up
PU
0111
Line interface is powered up
Activate request
AR
1000
INFO 2 received
Code violation received
CVR
1011
After each multiframe the reception of at
least one illegal code violation is indicated
four times.
Activate indication with
priority class 8
AI8
1100
INFO 4 received,
D-channel priority is 8 or 9
Activate indication with
priority class 10
AI10
1101
INFO 4 received,
D-channel priority is 10 or 11
Deactivate confirmation
DC
1111
Line interface is powered down
Preliminary Data Sheet
3-19
2003-08
DELIC
Interface Description
DI
DC
i4
F3
Power Down
i0
TIM
i0
AR i2
DI
PU AR2)
AR
F4
Pending Act.
TIM
i0
i1
DI
i2
i4
X
i0
i4
TMI4) TMI4)
TIM
DI
F5
Unsynchronized DI
i0
TIM
F3
Power Up
i0
i0
RSY
PU
RES
Test Mode i
it5)
ix
TIM
*
TMI4)
Any State
i2
RES RES
AR
DI
X
RES
F6
Synchronized
i3
i2
RESET
i0
TIM
*
ix
i4
i2
i4
i2
RSY
X
F8
Lost Framing
i0
i0
DI
DELPHI RESET pin
TIM
i0*TO1
i2
DI*TO2 (from F6)
DI (from F7, F8)
ix
AI3) AR2)
F7
Activated
i3
i4
i0*TO1
i4
DR1)
X
F3
Pending Deact.
i0
TIM*TO2 (from F6)
TIM (from F7, F8)
i0
1)
DR for transition from F7 or F8
AR stands for AR8 or AR10
3) AI stands for AI8 or AI10
4) TMI stands for TM1 or TM2
5) it1 = test signal invoked by it1
it2 = test signal invoked by it2
2)
Figure 3-8
TO1:
TO2:
16 ms
0.5 ms
LT-T Mode State Diagram (Conditional and Unconditional States)
Preliminary Data Sheet
3-20
2003-08
DELIC
Interface Description
LT-T Mode (Conditional States)
• F3 power down
This is the deactivated state of the physical protocol. The receive line awake unit is
active.
• F3 power up
This state is similar to “F3 power down”. The state is invoked by a Command
TIM = “0000” (or DI static low).
• F3 pending deactivation
The line interface reaches this state after receiving INFO 0 (from states F5 to F8).
From this state an activation is only possible from the line (transition “F3 pending
deactivation” to “F5 unsynchronized”). The power down state may be reached only
after receiving DI.
• F4 pending activation
Activation has been requested from the terminal; INFO 1 is transmitted; INFO 0 is still
received; “Power Up” is transmitted in the C/I channel. This state is stable: timer T3
(ITU I.430) is to be implemented in software.
• F5/8 unsynchronized
At the reception of any signal the VIP ceases to transmit INFO 1, adapts its receiver
circuit, and awaits identification of INFO 2 or INFO 4. This state is also reached after
the line interface has lost synchronism in the states F6 or F7 respectively.
• F6 synchronized
When the VIP receives an activation signal (INFO 2), it responds with INFO 3 and
waits for normal frames (INFO 4).
• F7 activated
This is the normal active state with the layer 1 protocol activated in both directions.
From state “F6 synchronized”, state F7 is reached almost 0.5 ms after reception of
INFO 4.
• F7 slip detected
When a slip is detected between the T interface clocking system and the IOM-2
interface clocks (phase wander of more than 25 µs, data may be disturbed) the line
interface enters this state, synchronizing again the internal buffer. After 0.5 ms this
state is relinguished.
Preliminary Data Sheet
3-21
2003-08
DELIC
Interface Description
LT-T Mode (Unconditional States)
The unconditional states should be left with the command TIM.
• Test mode 1
Single alternating pulses are sent on the T interface (2 kHz repetition rate).
• Test mode 2
Continuous alternating pulses are sent on the T interface (120 kHz).
• Reset state
A hardware or software reset (RES) forces the line interface to an idle state where the
analog components are disabled (transmission of INFO 0) and the T line awake
detector is inactive.
Preliminary Data Sheet
3-22
2003-08
DELIC
Interface Description
3.3
IOM®-2 Interface
IOM-2 is a standardized interface for interchip communication in ISDN line cards for
digital exchange systems developed by ALCATEL, Siemens, Plessey and ITALTEL.
The IOM-2 interface is a four-wire interface with a bit clock, a frame clock and one data
line per direction. It has a flexible data clock. This way, data transmission requirements
are optimized for different applications.
Figure 3-9
IOM®-2 Interface in Digital Linecard Mode
Note: In Linecard mode, 8 identical IOM-2 subchannels are provided. In analog
Linecards, a 6-bit C/I Channel is available for signaling information. In digital
Linecards, a dedicated 2-bit D-channel carries the signaling information.
3.3.1
FSC
DCL
DD
DU
B1, B2
MONITOR
D
C/I
MR
MX
Signals / Channels
Frame Synchronization Clock, 8 kHz
Data Clock, up to 4.096 MHz *)
Data Downstream, up to 4.096 Mbit/s *)
Data Upstream, up to 4.096 Mbit/s *)
User data channels, 64 kbit/s each
Monitor Channel
Signaling Channel, 16 kbit/s
Command/Indication Channel
Monitor Receive handshake signal
Monitor Transmit handshake signal
*) For detailed clock and data rates, refer to IOMU feature description in Chapter 4.3.2
Preliminary Data Sheet
3-23
2003-08
DELIC
Interface Description
3.4
µP Interface
The µP interface may be operated in different modes. This chapter describes how to
configure the DELIC to each mode.
3.4.1
Intel/Siemens or Motorola Mode
The processor mode is selected by the MODE input pin of the DELIC. "Low" level selects
Siemens/ INTEL mode, "HIGH" level selects Motorola mode.
3.4.2
De-multiplexed or Multiplexed Mode
In both modes, the A-bus and the D-bus are used in parallel. The A-bus should be
connected to the 8 LSBs of AD-bus, coming from the µP, also in multiplexed mode. The
mode is determined according to the ALE input pin. When ALE is permanently driven to
‘1’, the DELIC works in de-multiplexed mode. Otherwise the DELIC works in multiplexed
mode.
The next figure describes the connection of the DELIC to the address and data buses in
the different modes.
Note: Motorola mode is used only with de-multiplexed AD bus. Intel/Infineon mode may
be used with both, multiplexed or de-multiplexed AD bus.
Preliminary Data Sheet
3-24
2003-08
DELIC
Interface Description
Multiplexed Mode
AD
D
7
DELIC
LATCH
8
µP
A
ALE
ALE
De-multiplexed Mode
8
D
D
DELIC
A
7
A
LATCH
µP
ALE
‘1’
Figure 3-10 DELIC in Multiplexed and in De-multiplexed Bus Mode
Note: In both modes only the 7 LSBs of A-bus or AD/bus are connected to the
Address inputs of the DELIC. In DMA mode DACK/A4 input pin is used as DACK,
and A4 is internally driven to ‘0’. In this case A4 of the µP A/AD-bus is also not
connected to the DELIC.
3.4.3
DMA or Non-DMA Mode
The internal interface between the on-chip DSP and µP is established by two Mailboxes:
a ’general’ Mailbox and a dedicated DMA Mailbox. The non-DMA mode provides the
option to combine them together building a double-sized ’general’ Mailbox. The DELIC
is configured to DMA or non-DMA mode by a dedicated bit in the µP interface
configuration register (MCFG:DMA).
DMA Mode
The DMA Mailbox can be accessed only by a DMA controller. The DACK input pin
(together with the RD and WR signals) is used to access the DMA Mailbox. Only the
general Mailbox can be accessed directly by the µP. In DMA mode, the pin DACK/A4 is
Preliminary Data Sheet
3-25
2003-08
DELIC
Interface Description
used as DACK, and A4 of the A-bus or AD-bus coming from the µP must not be used as
an address line for the DELIC. In this case A4 is driven internally to ‘0’.
Note: In de-multiplexed mode AD4 should be connected to DELIC’s D4input pin.
Non-DMA mode
This is the default mode (after reset).The general Mailbox and the DMA Mailbox data
registers are concatenated into one double-sized general Mailbox, accessible by the µP.
This broad Mailbox consists of a dedicated µP Mailbox and a DSP Mailbox. Each of them
contains 32 data bytes and 1 command byte. In non-DMA mode, DACK/A4 is used as
A4, in order to include the DMA Mailbox data registers in the µP interface address space.
3.4.4
DELIC External Interrupts
The DELIC contains only one source for an external interrupt - the general Mailbox. This
interrupt source is the OCMD register of the DSP Mailbox. Releasing the interrupt is
done by the µP resetting bit OBUSY:BUSY. Masking it may be done by resetting the
MASK bit of the µP interface Configuration Register (MCFG:IMASK).
The interrupt vector issued is the contents of the DSP Mailbox command register MCMD.
In Motorola mode, the interrupt vector is issued upon the first IACK pulse, while in
Siemens/Intel mode it is issued upon the second IACK pulse. In the latter case, the
interrupt vector due to the first IACK pulse (if needed), should be issued by an external
interrupt controller.
Preliminary Data Sheet
3-26
2003-08
DELIC
Interface Description
3.5
JTAG Test Interface
The DELIC provides fully IEEE Standard 1149.1 compatible boundary scan support to
allow cost effective board testing. It consists of:
• Complete boundary scan test
• Test access port controller (TAP)
• Five dedicated pins: JTCK, TMS, TDI, TDO (according to JTAG) and an additional
TRST pin to enable asynchronous resets to the TAP controller
• One 32-bit IDCODE register
3.5.1
Boundary Scan Test
• Depending on the pin functionality one or two boundary scan cells are provided.
Pin Type
Number of Boundary Scan Cells
Usage
Input
1
Input
Output
2
Output, enable
When the TAP controller is in the appropriate mode data is shifted into/out of the
boundary scan via the pins TDI/TDO using a clock of up to 6.25 MHz on pin JTCK.
The sequence of the DELIC pins can be taken from the BSDL files.
3.5.2
TAP Controller
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE 1149.1. Transitions on the pin TMS cause the TAP controller to
perform a state change.
The TAP controller supports a set of 5 standard instructions:
Table 3-7
TAP Controller Instruction Codes
Code
Instruction
Function
0000
EXTEST
External testing
0001
INTEST
Internal testing
0010
SAMPLE/PRELOAD
Snap-shot testing
0011
IDCODE
Reading ID code register
1111
BYPASS
Bypass operation
EXTEST is used to verify the board interconnections.
When the TAP controller is in the state “update DR”, all output pins are updated with the
falling edge of JTCK. When it has entered state “capture DR” the levels of all input pins
Preliminary Data Sheet
3-27
2003-08
DELIC
Interface Description
are latched with the rising edge of JTCK. The in/out shifting of the scan vectors is
typically done using the instruction SAMPLE/PRELOAD.
INTEST supports internal chip testing.
When the TAP controller is in the state “update DR”, all inputs are updated internally with
the falling edge of JTCK. When it has entered state “capture DR” the levels of all outputs
are latched with the rising edge of JTCK. The in/out shifting of the scan vectors is
typically done using the instruction SAMPLE/PRELOAD.
Note: 0011 (IDCODE) is the default value of the instruction register.
SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is
used to either preload (TDI) or shift out (TDO) the boundary scan test vector. Both
activities are transparent to the system functionality.
IDCODE
The 32-bit identification register is serially read out via TDO. It contains the version
number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB
is fixed to ’1’. The code for the DELIC version 1.1 is ’0001’.
Version
Device Code
Manufacturer Code
0001
0000 0000 0101 0111
0000 1000 001
Output
1
--> TDO
Note: In the state “test logic reset” the code “0011” is loaded into the instruction code
register.
BYPASS, a bit entering TDI is shifted to TDO after one JTCK clock cycle, e.g. to skip
testing of selected ICs on a printed circuit board.
Preliminary Data Sheet
3-28
2003-08
DELIC
PEB 20571
Functional Description
4
Functional Description
As the functionality of the DELIC-PB comprises the functionality of the DELIC-LC, the
following chapter discribes the functionality of the DELIC-PB. The Differences between
the two chip versions can be seen below:
Table 4-1
Differences between DELIC-LC - DELIC-PB
Functionality
DELIC-LC
DELIC-PB
GHDLC channels (maximum configuration)
Cha. 0
Cha. 0..3
HDLC channels (maximum configuration)
Cha. 0..23
Cha. 0..31
DMA interface
not available
available
DMA- mailbox
not available;
it is used to
increment the
general mailbox
can be used for
DMA operation
or as general
mailbox
no
yes
Pinout
Free programmability of DSP-system
Note: As the functionality is also dependent on the firmware package, please also refer
to the respective documentation.
Preliminary Data Sheet
4-1
2003-08
Figure 4-1
Preliminary Data Sheet
Different
Lines:
Upn
or
S/T
Upn
2
Subscribers
Uk0
PRI
Upn
4-2
4
VIP/ VIP-8
S/T
...
0
1
2x IOM /GCI
16.384
MHz
REFCLK
IOM-2000/
LNC16
2 x 2.048 Mbit/s or
1 x 4.096 Mbit/s
VIP 2
VIP 1
VIP 0
8 x UPN/ S/T
3.3 V
Layer-1
ICs
5V
PLL
µP Bus
MUX
Siemens
C166
µP
61.44 MHz
Clocks
DSP
TRANSIU
HDLC
Unit
IOM Unit
DMAC
8
µP Mail Box
16
16
3
MEMORY
DMA Interface
DMA Mail
Box
Memory
INT
Interrupt
Controller
DSP OAK+
GHDLC
Unit
PCM Unit
3.3 V
TEST
5
JTAG
MUX
DELIC
5
3
LNC0
PCM/
LNC2..3
4.1
t/r
S/T
Different Lines
DELIC
PEB 20571
Functional Description
Functional Overview and Block Diagram
Block Diagram
2003-08
DELIC
PEB 20571
Functional Description
4.2
IOM-2000 Transceiver Unit
4.2.1
TRANSIU Overview of Features
• The TRANSIU controls up to 24 layer-1 channels via up to three VIP/ VIP8 connected
on IOM-2000 interface
• IOM-2000 interface: all channels may be programmed in the TRANSIU to:
– UPN interface
– S/T interface in LT-S (subscriber master) or LT-T (trunk slave) mode
Note: The number of S/T interfaces in VIP PEB 20590 is limited to 4. Therefore it is
required to program the TRANSIU correctly to the required mode (refer to
TRANSIU register description)
• Data rates: 3.072 Mbit/s (1 VIP), 6.144 Mbit/s (2 VIPs) or 9.216 Mbit/s (3 VIPs)
• Data and maintenance bit handling for S/T and UPN interface, including multiframe
control and D-channel collision control.
4.2.2
TRANSIU Initialization
Reset Status
•
•
•
•
All IOM-2000 channels are configured to S/T interface, LT-S mode
The data rate in the TRANSIU is set to 3.072 Mbit/s
All buffers related to the IOM-2000 are undefined
The Command and Status buffers have the value ‘0’
Channel Programming
Every IOM-2000 channel may be configured in the TRANSIU as:
• UPN mode
• S/T channel in LT-S mode
• S/T channel in LT-T mode
Data Rate Programming
The TRANSIU supports three configurations regarding the number of VIPs connected
via IOM-2000:
• One VIP connected at data rate of 3.072 Mbit/s: 8 IOM-2000 channels at a clock rate
of 3.072 MHz
• Two VIPs connected at data rate of 6.144 Mbit/s: 16 IOM-2000 channels at a clock
rate of 6.144 MHz
• Three VIPs connected at data rate of 9.216 Mbit/s: 24 IOM-2000 channels at a clock
rate of 12.288 MHz. (Note the difference between clock rate and actual data rate)
Preliminary Data Sheet
4-3
2003-08
DELIC
PEB 20571
Functional Description
4.2.3
Initialization of VIP
During startup the VIP requires 3 frames with the right FSC and DCL_2000 to
synchronize to the DELIC. During this time the VIP is not able to detect commands or
data from the DELIC.
4.2.4
S/T Mode Control and Framing Bits on IOM-2000
4.2.4.1
Framing Bit (F-Bit)
The framing (F) bit is recognized on the IOM-2000 interface, when both data and control
bits are equal to ‘1’. In the transmit direction the data and control bits are inserted by the
TRANSIU at the beginning of every transmitted frame; in the receive direction the
framing bit is used for frame start recognition.
4.2.4.2
Multiframing Bits
In S/T interface, the multiframe includes 20 S/T frames. The start of a multiframe is
indicated by the M- and Fa-bits (the M-bit is set to ‘1’ in every 20-th frame, the Fa-bit is
set to ‘1’ in every 5-th frame).
The S/Q channel provides the additional capability for data exchange between LT-S and
TE or between the Central Office (CO) and the LT-T at the multiframe level. In the LT-Sto-TE direction the S-channel (S-bit in S/T frame) is used. In the opposite direction (TE
to LT-S) the data is transferred on the Q-channel. The Q-bits are defined to be the bits
in the Fa bit position of every 5-th frame. The Q-bit position is identified by Fa = ‘1’ in the
TE to LT-S direction. A multiframe is provided for structuring the Q-bits in groups of four
(Q1-Q4).
The Q- and S-channel coding with respect to the frame number is shown in Table 4-2.
S
TE
Q
LT-S
VIP
IOM-2000
DELIC
S
CO
LT-T
Q
Figure 4-2
S/Q Channel Assignment
Preliminary Data Sheet
4-4
2003-08
DELIC
PEB 20571
Functional Description
Table 4-2
S/T Mode Multiframe Bit Positions
Frame number
LT-S to TE or
CO to LT-T,
Fa bit position
LT-S to TE or
CO to LT-T,
M-bit
LT-S to TE or
CO to LT-T,
S-bit
TE to LT-S or
LT-T to CO
Fa bit position
1
1
1
S11
Q1
2
0
0
S21
0
6
1
0
S12
Q2
7
0
0
S22
0
11
1
0
S13
Q3
12
0
0
S23
0
16
1
0
S14
Q4
17
0
0
S24
0
...
...
...
...
...
Note: 1.Only frame positions (within the 20-frame multiframe) that carry S- or Q-channel
information are shown here
2.The Q- and S-bits, which are not used, are set to ‘1’.
On the IOM-2000 interface, the S/T multiframe information is included in the DX/DR data
stream (transparently to the VIP). The values of the multiframe are controlled by the DSP
software in the DELIC.
When multiframe synchronization is not achieved or lost, the VIP mirrors the received Fa
bits. Once the multiframe synchronization is established, the DSP sends the multiframe
synchronization command to the VIP (MSYNC bit). Upon reception of the MSYNC, the
VIP stops mirroring the Fa -bit.
4.2.4.3
Fa/N Bit
In the transmit direction the Fa/N bit pair is coded in such a way that N is the binary
opposite of the Fa. The Fa bit is equal to binary ‘0’, except every 5-th frame when it is set
to ‘1’, which indicates the Q-bit position to the TE.
The receive direction, the Fa bit positions represent the Q-channel.
4.2.4.4
DC-Balancing Bit (L-Bit)
In transmit (downstream) direction the L-bit is generated in compliance with ITU-T I.430:
• A balance bit is ‘0’ if the number of 0’s following the previous balance bit is odd.
• A balance bit is ‘1’ if the number of 0’s following the previous balance bit is even.
Preliminary Data Sheet
4-5
2003-08
DELIC
PEB 20571
Functional Description
It is inserted by the VIP according to the Balancing Bit Control (BBC) bit sent to the VIP
by the DELIC via the CMD line.
In receive (upstream) direction, the DC balancing bit is received on the line, but not
evaluated
4.2.5
UPN Mode Control and Framing Bits on IOM-2000
4.2.5.1
Framing Bit (LF-Bit)
On the UPN interface the framing (LF) bit is always logical ‘1’.
In the transmit direction the LF-bit is inserted by the TRANSIU at the beginning of every
transmitted UPN frame. The VIP assumes the start of the UPN frame when detecting the
first '1' (LF-bit) in the data stream on IOM-2000 DX line together with the 8 kHz IOM-2000
FSC pulse. This is required due to the 8 kHz clock rate of the FSC signal in comparison
to the 4 kHz frame length in the UPN interface.
The code violation in the LF position is generated by the VIP when INFO1 is transmitted,
according to the DSP command bits SMINI(2:0).
In the receive direction the first ‘1’ recognized on the line after “no signal”, which is
represented by logic ‘0’, is treated as the LF-bit. The code violation in the LF-bit position
is recognized by the VIP when INFO 2 is received. This information is forwarded to the
DELIC as part of the VIP receiver status bits RxSTA(1:0).
4.2.5.2
Multiframing Bit (M-Bit)
On the UPN interface, multiframes are composed of four UPN frames. The multiframe is
included at the M-bit position. Every fourth M-bit, a code violation indicates the start of a
new multiframe.
In transmit direction, the VIP extracts the multiframe bits out of the IOM-2000 data
coming from DELIC and inserts them in the UPN frame at the line side.
In receive direction, the VIP extracts the multiframe bits out of the data coming from the
UPN line and inserts them in the IOM-2000 frame to the DELIC.
A multiframe counter in the VIP guarantees the timing of the multiframe. It is
synchronized (reset) every 20th UPN frame (=every 40th IOM-2000 frame) by the
command bit ’SH_FSC’ issued by the DELIC.
Note: The SH_FSC bit performs the functionality of the short FSC pulse in OCTAT-P
and QUAT-S.
T-bit
The T-bit received on the UPN line is inserted by the VIP in the IOM-2000 data receive
(DR) line at the multiframe (M-bit) position in every frame; i.e. not only at the usual T-bit
position every third frame, but also at the S-bit position and the code violation (CV)
Preliminary Data Sheet
4-6
2003-08
DELIC
PEB 20571
Functional Description
position. The DELIC DSP software may evaluate the received T-bit to provide the user
with an additional data channel (under consideration). Note that this is an additional
feature to the OCTAT-P.
In transmit direction, the T-bit value is sent in the data stream from the DELIC to the VIP,
and passed on transparently to the UPN terminal. The T-bit value may be programmed in
DELIC’s data RAM. It is required e.g. for DECT synchronization.
S-bit
The S-bit received on the UPN line interface is extracted by the VIP out of the data
stream, and is logical OR’ ed with the detected far-end code violation. The result is sent
to the DELIC as status bit ’FECV’.
In transmit direction, the S-bit value is sent in the data stream from the DELIC to the VIP,
and passed on transparently to the UPN terminal. The S-bit value may be programmed
in DELIC’s data RAM. It is required e.g. for switching a digital loop in the terminal.
CV-bit
The code violation bit received on the line is not transmitted to the DELIC.
4.2.5.3
DC-Balancing Bit
A DC-balancing bit is inserted by the VIP according to the Balancing Bit Control (BBC)
bit transmitted to the VIP on the command line.
In receive direction, the DC balancing bit is received, but not evaluated.
4.2.6
IOM-2000 Command and Status Interface
All Command/Status bits used for VIP channel programming are divided into one group
used only during initialization, and one group used during normal operation.
Initialization Mode Command Bits
The bits of this group are used for VIP initialization or in operation modes where an
immediate reaction is not required. The initialization group includes command bits and
the channel address, stored in register TICCMR. Note that the usage of this group of bits
is limited in a way that only one channel may be accessed in each frame.
In test mode, the command word to VIP_n (CMD_n) and to Channel_m of VIP_n
(CMD_n_m) may be read by the DELIC in the next frame after issuing bits ’RD_n’ or
’RD’. The VIP mirrors the command word exactly as it was received, despite the bits
’WR’, ’WR_ST’, ’RD’. The VIP status is saved in the TRANSIU initialization status
(TICSTR) register, which includes status bits and the channel address.
Note: The commands must not be read during normal operation, since in this case the
reporting of the VIP status to the DELIC would not be possible.
Preliminary Data Sheet
4-7
2003-08
DELIC
PEB 20571
Functional Description
Operational Mode Command/Status Bits
The bits of this group are used during normal operation, hence they are evaluated in
every frame. They include all VIP receiver status bits and some of the command bits.
The operational mode command/status bits are buffered in the Data RAM.
The VIP receiver status bits do not reflect a status change, but the status itself, i.e. the
current value of the line interface INFOs, until the values change.
The FECV is only reported to the DELIC upon changes.
Command/Status Transmission
The command/status bits are transmitted/received by the TRANSIU at the same rate as
data transmission rate, starting with the 8 kHz FSC.
Transmit Direction
• The command information per VIP is prepared by the DSP in the VIPCMR0-2
registers
• The command bits from initialization command group are prepared by the DSP in the
ICCMR register for one of the channels
• TRANSIU operation mode command format in the Data RAM:
7
6
5
4
3
2
1
0
data byte 1
data byte 2
data byte 3
x
WR_ST
x
x
SMINI(2:0)
MSYNC WR_ST
Write Command to TST1 Bits (S/T, UPN)
0 = Data sent in these bits is invalid
1 = SMINI(2:0) and MSYNC contain valid data
Preliminary Data Sheet
4-8
2003-08
DELIC
PEB 20571
Functional Description
MSYNC
Multiframe Synchronization (LT-T)
0 = VIP mirrors the FA-bit
1 = VIP stops the FA-bit mirroring (for multiframe synchronization)
SMINI(2:0)
State Machine Initialization (S/T, UPN)
Command to VIP from the DELIC layer-1 state machine. Depending
on the state, the VIP may transmit data on the UPN or S/T interface.
The VIP responds by sending the receiver status bits
STAT_n_m.RxSTA(1:0) to the DELIC.
000 = INFO 0 in S/T or UPN
001 = INFO 1w in UPN
010 = INFO 1 in LT-T, INFO 2 in LT-S or UPN
011 = INFO 3 in LT-T, INFO 4 in LT-S or UPN
100 = Test mode ’Send Continuous Pulses SCP’:
’1s’ transmitted at 96 kHz (UPN) and at 192 kHz S/T)
101 = Test mode ’Send Single Pulses SSP’ (at 2 kHz burst rate)
Note: all other states are reserved
Receive Direction
• The received status per VIP is stored in the VIPSTR0-2 registers
• If the “read_status” command was transmitted in the previous frame for one of the
channels, the received status from this channel is saved in the TICSTR register
together with the 5-bit channel address
• TRANSIU operation mode status format in the Data RAM:
7
6
5
4
3
2
SLIP
FECV
1
0
data byte 1
data byte 2
data byte 3
x
MSYNC
Preliminary Data Sheet
FCV
FSYNC
4-9
RxSTA(1:0)
2003-08
DELIC
Functional Description
RxSTA(1:0)
Receiver Status Change (S/T, UPN)
00 = Receiver is not synchronized to the line; no signal on line
(INFO 0)
01 = Level detected on line (any signal) (INF 1 in LT-S mode)
10 = Receiver is synchronized to the line, but not activated
(INFO 2 in LT-T mode)
11 = Receiver is synchronized and activated (INFO 4 for LT-T mode
INFO 3 for LT-S and UPN)
FECV
Far-end Code Violation (S/T, UPN)
0 = Normal operation
1 = Illegal code: FECV according to ANSI T1.605 detected (S/T)
SLIP
Frame Slip Detected (LT-T)
0 = No frame slip detected
1 = A frame slip of more than 25 µs (tbd) was detected on the LT-T
channel
FSYNC *
F-Bit Synchronous (S/T + UPN test mode only!!)
FCV *
Code Violation in F-Bit detected (UPN test mode only!!)
MSYNC / LD *
Multiframe Synchronous (UPN), Level Detected (S/T), test mode!!
Note: with * marked bits are not evaluated by the DELIC, only for VIP testing.
Bits SLIP, FECV and are directly available to the DSP software in the TRANSIU
receive data RAM.
Preliminary Data Sheet
4-10
2003-08
DELIC
PEB 20571
Functional Description
4.2.7
IOM-2000 Data Interface
Data processing and frame handling in the TRANSIU is fully DSP controlled. Serial data
received and transmitted on the IOM-2000 Interface is arranged in the Shift Receive
RAM and Shift Transmit RAM.
The DSP processed bytes are stored in the TRANSIU Current Buffer. Every 8 kHz frame
the TRANSIU and DSP Current Buffers are switched.
4.2.7.1
UPN Mode
The data is received and transmitted at a nominal bit rate of 384 kbit/s. In the first half of
the 4 kHz UPN frame data is transmitted and ‘zeros’ are received, in the second half of
the frame ‘zeros’ are transmitted and data is received.
Scrambling and de-scrambling of the B-channel data is done automatically. The received
and transmitted data is stored in the Data RAM in the following format:
UPN Mode Receive / Transmit Data Format
7
6
5
4
3
2
1
0
x
x
x
B1-channel data
B2-channel data
D-channel
M-bit
x
x
Operation Mode Command/Status bits
In transmit direction, depending on the multiframe position, the M-bit contains either the
T-bit or the S-bit with the following functionality:
• T-bit: a) D-channel available info to the terminal
b) DECT synchronization signal
• S-bit: switches remote loop in terminal device
4.2.7.2
UPN Scrambler/Descrambler
B-channel data on all UPN channels of the IOM-2000 interface is scrambled to give a flat
continuous power density spectrum on the line.
Scrambling is done according to ITU-T V.27 with the generator polynomial 1 + x6 + x7
Initialization via History RAM (HRAM)
The scrambler is activated/de-activated for each UPN channel separately by a DSP write
to the history RAM address.
Preliminary Data Sheet
4-11
2003-08
DELIC
Functional Description
During initialization the DSP writes a value with '0' in its LSB (other bits are of no
importance) to every History RAM address associated to an UPN channel that is not to
be scrambled, and a value with '1' in its LSB for every UPN channel that must be
scrambled. The same values must be written to the descrambler history RAM.
The HRAM addresses are:
• 0x9000 - 0x9017 (scrambler UPN channel 0..23)
• 0x9020 - 0x9037 (descrambler UPN channel 0..23)
For example, in order to activate scrambling and descrambling for channel number 3, the
DSP must execute two write operations as follows:
• Write "xxxxxxxxxxxxxxx1" to address 0x9002
• Write "xxxxxxxxxxxxxxx1" to address 0x9022
These writes are executed only when the scrambler is in idle mode, i.e. value 0x0003
was written by the OAK to address 0xD010.
4.2.7.3
S/T Mode
Data is received/transmitted at a nominal rate of 192 kbit/s. Each S/T data bit is
translated into two bits on IOM_2000: data (bit0) and control (bit1).
LT-S Mode Transmit Data Format
7
6
5
4
3
2
1
0
S
x
x
2
1
0
x
x
x
B1-channel data
B2-channel data
D-channel
x
Fa
M
Operation Mode Command/Status bits
LT-S Mode Receive Data Format
7
6
5
4
3
B1 - channel data
B2 - channel data
D-channel
Fa
x
x
Operation Mode Command/Status bits
Preliminary Data Sheet
4-12
2003-08
DELIC
PEB 20571
Functional Description
LT-T Mode Receive Data Format
7
6
5
4
3
2
1
0
S
CBN
CDI
B1-channel data
B2-channel data
D-channel
x
Fa
M
Operation Mode Command/Status bits
CBN
Collision Detection Bit Number
0 = Collision was detected in the first D-bit of the frame
1 = Collision was detected in the second D-bit of the frame
CDI
Collision Detection Indication
0 = No collision in D-channel
1 = Collision in D-channel detected
LT-T Mode Transmit Data Format
7
6
5
4
3
2
1
0
x
x
x
B1-channel data
B2-channel data
D-channel
Fa
x
x
Operation Mode Command/Status bits
Preliminary Data Sheet
4-13
2003-08
DELIC
Functional Description
4.3
IOM-2 Unit
4.3.1
IOMU Overview of Features
The IOMU provides the DSP access to incoming time slots from the IOM-2 interface. The
DSP may switch the timeslots to the other DELIC system interfaces.
Features
• DSP access for switching of B1 and B2 data to the PCMU and the TRANSIU
(providing a constant switching delay of two 8 kHz frames)
• DSP access for extracting of D-channel information
• DSP access for control of IOM-2 Command/Indication (C/I) and Monitor channel
information
Interface Configuration
• Two IOM-2 ports providing up to 16 IOM-2 channels (up to 16 ISDN or 32 analog
subscribers)
• Available data rate modes:
– Two ports of 384 kbit/s each (2 x 6 time slots per frame)
– Two ports of 768 kbit/s each (2 x 12 time slots per frame)
– Two ports of 2.048 Mbit/s each (2 x 32 time slots per frame)
– One port of 4.096 Mbit/s (1 x 64 time slots per frame)
• Single or double data rate clock selectable in each data rate mode
• Programmable tri-state control for each port and channel (=4 time slots)
• Push-pull or open-drain configuration
• DRDY signal for D-channel control when connected to QUAT-S PEB 2084
Preliminary Data Sheet
4-14
2003-08
DELIC
PEB 20571
Functional Description
4.3.2
IOMU Functional and Operational Description
IOM-2 Interface
DELIC
FSC
PCM
Interface
CLOCKS
DCL
PCMU
DD0
B1
B2
D.C/I M
B2
B1
DU0
DD1
B1
B2
D.C/I M
SWITCHING
M D,C/I
M D,C/I
B2
B1
IOMU
DU1
IOM-2000
Interface
SWITCHING
DRDY
HDLCU
TRANSIU
DSP
Figure 4-3
4.3.2.1
IOMU Integration in DELIC
Frame-Wise Buffer Swapping
The main task of the IOMU is the serial-to-parallel conversion of incoming IOM-2 data to
a parallel data format which is directly read by the DSP. This access is required for the
DSP to perform switching of B-channels, extraction of D-channels, and layer-1 control
via the IOM-2 C/I and Monitor channels.
The data conversion in the IOMU is done by frame-wise swapping based on a circular
buffer structure. During each 8 kHz frame, one buffer is assigned to the IOMU (I-buffer),
and the other one to the DSP (D-buffer). At the end of every frame, the buffers are
swapped.
4.3.2.2
I-buffer Logical Structure
The logical partitioning of each frame buffer into input and output blocks is determined
according to the requested data rate as shown in the table below.
The address of each data byte in the I-buffer output blocks by the DSP must be selected
according to the IOM port and time slot index, in which it should be transmitted.
Preliminary Data Sheet
4-15
2003-08
DELIC
Functional Description
Table 4-3
I-Buffer Logical Memory Mapping
Data Rate
Input Blocks
Output Blocks
in0
in1
out0
out1
2 x 2.048 Mbit/s
2 x 384 kbit/s
2 x 768 kbit/s
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
1 x 4.096 Mbit/s
00H - 3FH
--
40H - 7FH
--
Note: In 2 x 384 / 768 kbit/s mode, only the first 6 / 12 bytes of each block are used.
4.3.2.3
DSP Access to the D-Buffer
The D-buffer is mapped to a fixed DSP address space. Every DSP access to the D-buffer
space is directed automatically to the appropriate sub-buffer.
.
Table 4-4
Data-Rate
Mode
D-Buffer Address Space
D-Buffer
in1
out0
out1
2 x 6/12/32
8000H time slots/frame 801FH
8020H 803FH
8040H 805FH
8060H 807FH
1 x 64
8000H time slots/frame 803FH
-
8040H 807FH
-
4.3.2.4
in0
IOM-2 Interface Data Rate Modes
The IOMU may support different serial data rates of the IOM-2 interface:
•
•
•
•
384 kbit/s (6 time slots per frame)
768 kbit/s (12 time slots per frame)
2.048 Mbit/s (32 time slots per frame = 8 IOM-2 channels per frame)
4.096 Mbit/s (64 time slots per frame = 16 IOM-2 channels per frame)
The IOMU circular buffer may handle up to 64 time slots per frame. Thus, when in 4.096
Mbit/s mode, only IOM-2 port 0 is used. In this case IOM-2 port 1 remains in IDLE mode,
i.e. the DD1 output pin is tri-stated.
Note that when using any of the two lower data rates, both IOM-2 ports are used.
In all data rate modes, single rate Data Clock (DCL) or double rate Data Clock may be
selected.
Preliminary Data Sheet
4-16
2003-08
DELIC
PEB 20571
Functional Description
Table 4-5
DCL Frequency in Different IOM-2 Modes
Single/Double
Rate DCL Mode
IOM-2 Mode
2x384 kbit/s
2x768 kbit/s
2x2.048 Mbit/s 1x4.096 Mbit/s
Single
384 kHz
768 kHz
2.048 MHz
4.096 MHz
Double
768 kHz
1536 kHz
4.096 MHz
8.192 MHz
The IOMU meets the IOM-2 interface timing specifications as described below.
Single Data Rate DCL Mode
• Serial transmission via DD0/DD1 with every DCL rising edge
• Sampling of the incoming serial data (DU0/DU1) with every DCL falling edge
• Sampling FSC with every DCL falling edge. Sampling of FSC = 1 after sampling of
FSC = 0 is considered to be the start of a frame.
Double Data Rate DCL Mode
•
•
•
•
Two DCL cycles per bit (the bits are aligned to the frame start)
Serial transmission via DU0/1 with every second DCL rising edge.
Sampling of incoming serial data (DD0/1) with the second DCL falling edge of each bit.
Sampling of FSC every DCL falling edge. Sampling of FSC = 1 after sampling of
FSC = 0, is considered to be the start of a new frame.
Figure 4-4 shows the IOM-2 interface timing with single and double rate DCL. For more
details refer to the general IOM-2 interface description.
Preliminary Data Sheet
4-17
2003-08
DELIC
Functional Description
Single Data Rate DCL
FSC
Frame Start
DCL
DD0/1
TS31
bit0
TS0
bit7
TS0
bit6
TS0
bit5
TS0
bit4
TS0
bit3
TS0
bit2
TS0
bit1
TS0
bit0
TS1
bit1
TS31
bit0
TS0
bit7
TS0
bit6
TS0
bit5
TS0
bit4
TS0
bit3
TS0
bit2
TS0
bit1
TS0
bit0
TS1
bit7
DU0/1
Double Data Rate DCL
FSC
Frame Start
DCL
DD0/1
TS31
bit0
DU0/1
TS31
bit0
TS0
bit7
TS0
bit6
TS0
bit7
TS0
bit5
TS0
bit6
4.3.2.5
TS0
bit5
TS0
bit4
= FSC Sampling
= Upstream Sampling
Figure 4-4
TS0
bit4
IOM-2 Interface Timing in Single/Double Clock Mode
IOMU Serial Data Processing
The IOMU serial data processing is according to the IOM-2 specifications. Incoming
serial data is converted into parallel bytes, and stored in the I-buffer input blocks. The
sequence for every time slot received is from MSB (bit 7) to LSB (bit 0). Transmission is
performed in the opposite direction, from MSB (bit 7) to LSB (bit 0).
4.3.2.6
IOMU Parallel Data Processing
The data read from the IOMU frame buffers by the DSP always reside in the low byte of
the 16-bit word. The high byte of the read word is driven by the 8-bit IOMU Data Prefix
Register (IDPR). The data prefix is used to accelerate the A-/µ-law to linear conversions
(refer to Chapter 4.5).
Note: Any octet written by the DSP to any location in the IOMU frame buffers should
reside in the low byte (8 LSB). The high byte of the written word is “don’t care”.
Preliminary Data Sheet
4-18
2003-08
DELIC
PEB 20571
Functional Description
4.3.2.7
IOM-2 Push-Pull and Open-Drain Modes
The IOM-2 ports can be configured to Push-Pull or Open-Drain modes by a dedicated
bit in the IOMU Control Register. When programmed to Open-Drain, DD0/DD1 is tristated when a ‘1’ is supposed to be transmitted, or during a time slot quadruplet with the
associated Tri-State Register bit set.
In both cases the external pull-up resistor, which is used when working in open-drain
mode, will “pull” the value to ‘1’.
Note: When the IOMU is programmed to 1x 64 time slots per frame mode, DD1 is tristated, independently of the IOM-2 interface push-pull or open-drain mode.
DELIC
IOMU
downstream0
data
mux
DD0
ITSR
DD1
Figure 4-5
mux
downstream1
data
IOM-2 Interface Open-Drain Mode
DELIC
IOMU
downstream0
data
mux
DD0
ITSR
DD1
Figure 4-6
mux
downstream1
data
IOM-2 Interface Push-Pull Mode
Preliminary Data Sheet
4-19
2003-08
DELIC
Functional Description
4.3.2.8
Support of DRDY Signal from QUAT-S
The DRDY input is used when connecting a Siemens QUAT-S transceiver to the DELIC
via the IOM-2 interface. It is driven by the QUAT-S to inform the DELIC when a Dchannel is occupied by another S-interface device.
The IOMU supports the synchronous DRDY mode, i.e. the QUAT-S is operated in LT-T
mode. In this mode, the DRDY signal is valid only during the D-channels.
DRDY = ‘0’ means STOP (ABORT HDLC message), and DRDY = ‘1’ means GO.
FSC
IOM-2 ch 7
DU0
B1 B2
MON D
IOM-2 ch 0
B1 B2
IOM-2 ch 1
B1 B2
MON D
IOM-2 ch 2
B1 B2
MON D
MON D
go
IOM-2 ch 3
B1 B2
MON D
go
DRDY
stop
stop
stop
= not valid
Figure 4-7
DRDY Signal Behavior
IOMU DRDY support features:
• Sampling DRDY only once every D-channel, at the first bit.
• Sampling with the first DCL falling edge (in single data-rate DCL mode), or with the
second falling DCL edge (in double data-rate DCL mode), refer to Figure 4-8.
• DRDY support via IOM-2 port 0 only (with a constant delay of one 8 kHz frame)
• The status of the DRDY line can be read from register IDRDYR
First bit of
a D-channel
DU0
second bit of
a D-channel
D0
DRDY
D1
valid
Sample point of DRDY
in single data-rate DCL mode
Single
Data-Rate DCL
Sample point of DRDY
in double data-rate DCL mode
Double
Data-Rate DCL
Figure 4-8
DRDY Sampling Timing
Preliminary Data Sheet
4-20
2003-08
DELIC
PEB 20571
Functional Description
4.4
PCM Unit
PCM Interface Features
The PCMU enables the DSP to control the 4 PCM ports. The DSP accesses the
incoming PCM time slots, and prepares the outgoing PCM time slots. In general, the
PCMU enables the DSP to switch time slots from and to the PCM ports.
The basic structure and programming model of the PCMU is similar to the IOMU. Note
that the PCMU provides the double capacity of the IOMU. Thus it may handle up to
4 PCM ports and an overall of 128 time slots per frame in the receive direction and 128
time slots per frame in the transmit direction.
The following PCMU data rate modes are available:
•
•
•
•
Four streams of 2.048 Mbit/s each (single and double clock)
Two streams of 4.096 Mbit/s each (single and double clock)
One stream of 8.192 Mbit/s (single and double clock)
One stream of 16.384 Mbit/s (single clock). It is programmable, whether the first or the
second 128 time slots of the 8 kHz frame are handled in the PCMU.
Tristate control is performed via pins TSCn, programmable per time slot and port.
Preliminary Data Sheet
4-21
2003-08
DELIC
Functional Description
4.4.1
PCMU Functional and Operational Description
PCM interface
PDC, PFS
TSC2
TSC3
PCM Unit
IOM Unit
RXD0, TXD0, TSC0
MUX
HDLC
Unit
RXD1, TXD1, TSC1
RXD2, TXD2
RXD3, TXD3
GHDLC
Unit
DSP OAK+
TRANSIU
Memory
Figure 4-9
PCMU Integration in DELIC
The PCM-unit signals share port pins with the GHDLC-unit. A multiplexer controlled by
register MUXCTRL allows to define the required functionality.
4.4.1.1
Frame-Wise Buffer Swapping
The main task of the PCMU is the serial-to-parallel conversion of incoming data to a
parallel data format (and vice versa) which is directly read by the DSP. This access is
required for the DSP to perform switching of B-channels.
The data conversion in the PCMU is done by frame-wise swapping based on a circular
buffer structure. During each 8 kHz frame, one buffer is assigned to the PCMU (I-buffer),
and the other one to the DSP (D-buffer). At the end of every frame, the buffers are
swapped.
4.4.1.2
DSP Inaccessible Buffer (I-buffer)
The logical partitioning of each frame buffer into input and output blocks is determined
according to the requested data rate as shown in the table below.
The address of each data byte in the I-buffer output blocks by the DSP must be selected
according to the PCM port and time slot index, in which it should be transmitted.
Preliminary Data Sheet
4-22
2003-08
DELIC
PEB 20571
Functional Description
Table 4-6
I-Buffer Logical Memory Mapping of Input Buffers
Data Rate
Input Blocks
related port
in0
in1
in2
in3
RXD0
RXD1
RXD2
RXD3
4 x 2.048 Mbit/s
00H - 1FH 20H - 3FH
2 x 4.096 Mbit/s
00H - 3FH 40H - 7FH
1 x 8.192 Mbit/s
00H - 7FH
1 x 16.384 Mbit/s
00H - 7FH
Table 4-7
40H - 5FH 60H - 7FH
I-Buffer Logical Memory Mapping of Output Buffers
Data Rate
Output Buffer Blocks
related port
out0
out1
out2
out3
TXD0
TXD1
TXD2
TXD3
4 x 2.048 Mbit/s
80H - 9FH A0H - BFH C0H - DFH E0H - FFH
2 x 4.096 Mbit/s
80H - BFH C0H - FFH
1 x 8.192 Mbit/s
80H - FFH
1 x 16.384 Mbit/s
80H -FFH
Note: In 1 x 16.384 Mbit/s only the first half of the frame is saved in the buffer
4.4.1.3
DSP Accessible Buffer (D-Buffer)
The D-buffer is mapped to a fixed DSP address space. Every DSP access to the D-buffer
space is directed automatically to the appropriate sub-buffer.
Table 4-8
DSP Access to D-Buffer Input Blocks
Data Rate
Input Buffer Blocks
related port
in0
in1
in2
in3
RXD0
RXD1
RXD2
RXD3
4 x 2.048 Mbit/s
A000H - A01FH A020H - A03FH A040H - A05FH
2 x 4.096 Mbit/s
A000H - A03FH A040H - A07FH
1 x 8.192 Mbit/s
A000H - A07FH
A060H - A07FH
1 x 16.384 Mbit/s A000H - A07FH
Preliminary Data Sheet
4-23
2003-08
DELIC
Functional Description
Table 4-9
DSP Access to D-Buffer Output Blocks
Data Rate
Output Buffer Blocks
related port
out0
out1
out2
out3
TXD0
TXD1
TXD2
TXD3
4 x 2.048 Mbit/s
A080H - A09FH A0A0H - A0BFH A0C0H - A0DFH A0E0H - A0FFH
2 x 4.096 Mbit/s
A080H - A0BFH A0C0H - A0FFH
1 x 8.192 Mbit/s
A080H - A0FFH
1 x 16.384 Mbit/s A080H - A0FFH
Note: In 1 x 16.384 Mbit/s only the first half of the frame is saved in the buffer
4.4.1.4
PCMU Interface Data Rate Modes
The PCMU may support different serial data rates:
•
•
•
•
up to 4 ports with 2048 Mbit/s (32 time slots per frame)
up to 2 ports with 4.096 Mbit/s (64 time slots per frame)
1 port with 8.196 Mbit/s (128 time slots per frame)
1 port with 16.384 Mbit/s (only 128 time slots of the frame are supported)
The PCMU circular buffer may handle up to 128 time slots per frame. Thus, when e.g.
configured in 4.096 Mbit/s mode, only PCM port 0 and 2 are used. In this case PCM
port 1 and 3 remain in IDLE mode, i.e. the TXD1, TXD3 output pins are tri-stated.
For the data rate modes up to 8.192 MBit/s, single rate Data Clock (PDC) or double rate
Data Clock may be selected. For 16.384 MHz mode only single clock is supported.
Single Data Rate PDC Mode
• Serial transmission via TXDn with every DCL rising edge
• Sampling of the incoming serial data (RXDn) with every PDC falling edge
• Sampling PFS with every PDC falling edge. Sampling of PFS = 1 after sampling of
PFS = 0 is considered to be the start of a frame.
Double Data Rate PDC Mode
•
•
•
•
Two PDC cycles per bit (the bits are aligned to the frame start)
Serial transmission via TXDn with every second PDC rising edge.
Sampling of incoming serial data (RXDn) with the second PDC falling edge of each bit.
Sampling of PFS every PDC falling edge. Sampling of PFS = 1 after sampling of
PFS = 0, is considered to be the start of a new frame.
Preliminary Data Sheet
4-24
2003-08
DELIC
PEB 20571
Functional Description
Figure 4-4 shows the PCM interface timing with single and double rate PDC.
Single Data Rate PDC
PFS
Frame Start
PDC
TXD
TS31
bit0
TS0
bit7
TS0
bit6
TS0
bit5
TS0
bit4
TS0
bit3
TS0
bit2
TS0
bit1
TS0
bit0
TS1
bit1
TS31
bit0
TS0
bit7
TS0
bit6
TS0
bit5
TS0
bit4
TS0
bit3
TS0
bit2
TS0
bit1
TS0
bit0
TS1
bit7
RXD
Double Data Rate PDC
PFS
Frame Start
PDC
TXD
RXD
TS31
bit0
TS31
bit0
TS0
bit7
TS0
bit6
TS0
bit7
TS0
bit5
TS0
bit6
TS0
bit4
TS0
bit5
TS0
bit4
= PFS Sampling
= data Sampling
Figure 4-10 IOM-2 Interface Timing in Single/Double Clock Mode
4.4.1.5
PCMU Serial Data Processing
The incoming serial data is converted into parallel bytes, and stored in the I-buffer input
blocks. The sequence for every time slot received is from MSB (bit 7) to LSB (bit 0).
Transmission is performed from MSB (bit 7) to LSB (bit 0).
4.4.1.6
PCMU Parallel Data Processing
The data read from the PCMU frame buffers by the DSP always reside in the low byte of
the 16-bit word. The high byte of the read word is driven by the 8-bit PCMU Data Prefix
Register (PDPR). The data prefix is used to accelerate the A-/µ-law to linear conversions
(refer to Chapter 4.5).
Preliminary Data Sheet
4-25
2003-08
DELIC
Functional Description
Any octet written by the DSP to any location in the PCMU frame buffers should reside in
the low byte (8 LSB). The high byte of the written word is “don’t care”.
4.4.1.7
PCMU Tri-state Control Logic
There are eight 16-bit tri-state control registers in the PCMU. Each bit determines
whether its associated time slot is valid or invalid.
• '0' = the controlled time slot is invalid
• '1' = the controlled time slot is valid
The tri-state bits control the data transmit pins TXD0 - TXD3.
A special set/reset write method is used for updating the tri-state control registers. Every
tri-state control register is mapped to 2 addresses: the first is used for set operation, the
second for reset operation. Both addresses may be used for read operation.
• Set operation: This operation is executed during DSP write access to the set address
of one of the TSC registers. The bits in the TSC register are set to '1' according to the
bits in the written word. The other bits maintain their value.
• Reset operation: This operation is executed during DSP write access to the reset
address of one of the TSC registers. The bits in the TSC register are reset to '0'
according to the bits in the written word. The other bits maintain their value.
The Tristate Control Registers (PTSR0-7) can be accessed by the DSP. Every bit of
them controls the TSC signal of one of the 4 PCM ports, for one time slot. The time slot
and the port controlled by every bit depend on the data rate mode. In 1x256 TS/frame, it
depends also on the selected half of the frame. Each TSC signals controls directly its
respective TxD port, and is also driven outward via the corresponding TSCn output pin.
For the 4 x 32 time slot per frame mode, the next table depicts which port is controlled
by each TSC register, and during which time slot. Bit 0 of each TSC register controls the
first time slot of the listed time slot range, bit 1 controls the second one etc.
Table 4-10
Time Slots
PCM TSC in 4 x 32 TS Mode
TSC0
TSC1
TSC2
TSC3
0..15
PTSC0
PTSC2
PTSC4
PTSC6
16..31
PTSC1
PTSC3
PTSC5
PTSC7
In 2 x 64 time slot per frame mode, only PCM ports 0 and 2 are used. TSC1 and TSC3
are permanently '0' (all time slots are invalid).
Preliminary Data Sheet
4-26
2003-08
DELIC
PEB 20571
Functional Description
Table 4-11
Time Slots
PCM TSC in 2 x 64 TS Mode
TSC0
TSC1
TSC2
TSC3
0..15
PTSC0
inactive
PTSC4
inactive
16..31
PTSC1
inactive
PTSC5
inactive
32..47
PTSC2
inactive
PTSC6
inactive
48..63
PTSC3
inactive
PTSC7
inactive
In 1 x 128 time slot per frame mode, only PCM port 0 is used. TSC1, TSC2 and TSC3
are permanently '0' (all time slots are invalid). In 1 x 256 time slot per frame mode, only
one half of the frame is used. All TSC pins are permanently '0' during the other half of
the frame.
Table 4-12
Time Slots
PCM TSC in 1 x 128 TS and 1 x 256 TS (1st Half) Mode
TSC0
TSC1
TSC2
TSC3
0..15
PTSC0
inactive
inactive
inactive
16..31
PTSC1
inactive
inactive
inactive
32..47
PTSC2
inactive
inactive
inactive
48..63
PTSC3
inactive
inactive
inactive
64..79
PTSC4
inactive
inactive
inactive
80..95
PTSC5
inactive
inactive
inactive
96..111
PTSC6
inactive
inactive
inactive
112..127
PTSC7
inactive
inactive
inactive
Note: The same structure applies to the 256 TS per frame (first frame half) mode, except
that all time slots (0..127) are transmitted in the first half of the 8 kHz frame.
Table 4-13
Time Slots
PCM TSC in 1 x 256 TS (2nd Half) Mode
TSC0
TSC1
TSC2
TSC3
0..127
inactive
inactive
inactive
inactive
128..143
PTSC0
inactive
inactive
inactive
144..159
PTSC1
inactive
inactive
inactive
160..175
PTSC2
inactive
inactive
inactive
176..191
PTSC3
inactive
inactive
inactive
192..207
PTSC4
inactive
inactive
inactive
Preliminary Data Sheet
4-27
2003-08
DELIC
Functional Description
Table 4-13
Time Slots
PCM TSC in 1 x 256 TS (2nd Half) Mode
TSC0
TSC1
TSC2
TSC3
208..223
PTSC5
inactive
inactive
inactive
224..239
PTSC6
inactive
inactive
inactive
240..255
PTSC7
inactive
inactive
inactive
Preliminary Data Sheet
4-28
2003-08
DELIC
PEB 20571
Functional Description
4.5
A-law/µ-law Conversion Unit
The A-/µ-law Unit performs a bi-directional conversion between a linear representation
of voice data and its companded representation (according to A-law or µ-law). The
conversion is possible for all B-channels transceived via IOM-2, IOM-2000 or PCM.
A-/µ-law to Linear Conversion
The conversion is done via a 512 x 16 ROM table. The low 256 bytes translate the A-law
value into linear, while the high 256 words translate the µ-law to linear.
The DSP issues a read cycle, in which the 8 MSBs of the 16-bit address represent the
ROM table address, and the 8 LSBs are the actual value which is to be converted. The
converted linear value is the contents read from the ROM. Note that no wait states are
required for this direction of conversion.
A-law values in the ROM are stored in the 13 MSBs. The 3 LSBs are always '0'. The µlaw values in the ROM are stored in the 14 MSBs. The 2 LSBs are always '0'.
Linear to A-/µ-law Conversion
The conversion is done by dedicated hardware. The DSP programs the control register
to perform either A-law or µ-law conversion. The linear value is written into the Input
register (AMIR), and the A-law or µ-law value is read from the Output register (AMOR).
Note that this is only possible one cycle later.
Preliminary Data Sheet
4-29
2003-08
DELIC
Functional Description
4.6
HDLC Unit
4.6.1
HDLCU Unit Overview
The HDLCU decodes and encodes HDLC messages to and from the DSP. It may
process up to 32 full-duplex HDLC channels in parallel. It is controlled by the DSP
through software and is thus very flexible.
The HDLCU includes a Receive Input Buffer, a Receive Output Buffer, a Transmit Input
Buffer and a Transmit Output Buffer, some HDLC protocol processing logic and a
command RAM.
DSP D-Buffer*
DSP D-Buffer*
* Frame-buffers of the IOMU,
PCMU or TRANSIU that belong to
the DSP during the present frame
32x8
32x16
Receive Input Buffer
Transmit Output Buffer
32 channels
32 channels
encoded
Internal
Processing
decoded
Receive Output Buffer
Internal
Processing
command
RAM
32x8
32x8
32 channels
DSP data double buffer
32x8
Transmit Input Buffer
32 channels
DSP Control
DSP Data Double Buffer
Figure 4-11 HDLCU General Block Diagram
Figure 4-11 shows the HDLCU structure. Each buffer, except the Transmit Output
Buffer, is a 32 x 8 RAM, hence one byte is assigned to each HDLC time slot channel.
Preliminary Data Sheet
4-30
2003-08
DELIC
PEB 20571
Functional Description
The Transmit Output Buffer is a 32 x 15 RAM because, in addition to each HDLC
channel, there is also a 7 bit status vector assigned to each channel stored in this buffer.
The DSP assigns each time slot used for transceiving an HDLC message to a different
address in the Receive/Transmit Input Buffers. The HDLCU decodes/encodes the time
slots into the corresponding addresses in the Receive/Transmit Output Buffers.
During every frame, two HDLCU activities are performed:
1. DSP access to the HDLCU
2. HDLCU encoding/decoding
At the beginning of a frame the DSP checks if the HDLCU is busy (HHOLD = ’0’). Note
that the DSP may only access the buffers and command RAM when DSPCTRL = ‘1’.
In the receive direction the DSP places HDLC message time slots to be processed from
the D-buffers into the Receive Input Buffer. Processed message time slot octets may be
read by the DSP from the Receive Output Buffer.
In the transmit direction the DSP places HDLC message time slots to be processed in
the Transmit Input Buffer. Processed time slots may be read from the Transmit Output
Buffer and placed into the D-Buffer of the IOMU, PCMU or TRANSIU from which they
will be transmitted during the next frame.
4.6.2
DSP Operation of the HDLCU
4.6.2.1
Initialization of the HDLCU
The first frame is used to reset the receive and transmit mechanisms of each channels.
1. The DSP asks for the HDLCU setup from the External Controller.
2. The DSP sets the bit DSPCTRL to ‘1’.
3. The DSP resets the receive mechanism and transmit mechanism of a channel by
setting the RECRES flag of its command vector to ‘1’ and inserting an abort command.
The DSP also writes the setup of the HDLCU.
4. The DSP sets DSPCTRL to ‘0’.
5. When the HDLCU finishes processing (HHOLD = ’1’), the HDLCU is initialized and is
ready for use.
4.6.2.2
Transmitting a Message
In order to transmit a message the DSP must place a Start transmission command in the
appropriate address in the command RAM.
If CRC encoding is required, then the DSP must set bit 1 to ‘1’ in the command vector.
In the unshared flag mode, during the first frame a flag is transmitted over the channel.
After the flag has been transmitted, the HDLCU starts to transmit the message. In the
Preliminary Data Sheet
4-31
2003-08
DELIC
Functional Description
shared flag mode the HDLCU starts transmitting the message in the frame adjacent to
the reception of the Start transmission command.
Note: Messages with zero byte data content are not supported.
4.6.2.3
Ending a Transmission
When placing the last octet of the message into the Transmit Input Buffer, the DSP
should place an End transmission command in place of the Start transmission command
without changing the CRC bit.
If CRC encoding is required, the CRC vector will be transmitted bit by bit after the octet
of the message, and then a flag will be transmitted. If CRC encoding is not required, a
flag will be transmitted directly after the last octet of the message. Note that in unshared
flag mode, if no adjacent frame exists, ’ones’ will be transmitted after the flag.
4.6.2.4
Aborting a Transmission
In order to abort transmission of a message over a dedicated channel, the DSP places
an abort command in the appropriate address in the command RAM. The message
being transmitted over the channel is aborted and ’ones’ are transmitted over the
channel instead (even in the shared flag mode).
4.6.2.5
DSP Access to the HDLCU Buffers
Reading a channel from the Receive Output Buffer and writing to a channel in the
Transmit Input Buffer is done according to the channel status vector and according to the
Empty and Full procedures as shown below:
Empty procedure
• If the EMPTY flag of a channel is set by the HDLCU to ‘1’, then move a new time slot
to be transmitted from the pipe to the Transmit Input Buffer.
• If the pipe is empty change the pipe page and ask for the next 16 bytes of data from
the external controller by means of DMA or interrupt.
Note: The B-channel buffer may be emptied within a single frame, while it takes at least
4 frames to empty a D-channel buffer.
Full procedure
• If the FULL flag of a channel is set by the HDLCU to ‘1’ then the DSP moves the time
slot from the Receive Output Buffer into the double buffer.
• If the pipe is full change the pipe page and transfer the next 16 bytes of data to the
External Controller by means of DMA or interrupt.
Note: The B-channel buffer may be filled within a single frame, while a D-channel buffer
will take at least 4 frames to fill.
Preliminary Data Sheet
4-32
2003-08
DELIC
PEB 20571
Functional Description
Reading Data from the Receive Output Buffers
When the DSP reads a time slot from an even address in the Receive Output Buffer, the
HDLCU will place it on the LSB byte of the data bus and ‘0’ on the MSB byte. When the
DSP reads a time slot from an odd address, the HDLCU will place it on the MSB byte of
the data bus and ‘0’ on the LSB byte.
Writing Data to the Transmit Input Buffers
When the DSP writes to an even address in the Transmit Input Buffer, the HDLCU will
write the LSB of the data bus. When the DSP writes to an odd address, the HDLCU will
write the MSB byte of the data bus.
Preliminary Data Sheet
4-33
2003-08
DELIC
Functional Description
4.7
GHDLC Unit
4.7.1
GHDLC Overview
The GHDLC (General HDLC) controls the dedicated serial communication interface of
the DELIC. The purpose of the GHDLC is to decode incoming HDLC messages and to
encode outgoing messages according to the HDLC protocol. The GHDLC transceives
HDLC data streams with up to 16.384 Mbit/s. A received message is collected bit by bit
from the line and stored as octets in the Receive buffer and read by the DSP. A
transmitted message which is placed by the DSP as octets in the Transmit buffer, is
transmitted bit by bit over the line.
.
status and interrupt vector
DSP
Double
Buffer
Receive
Processing
Receive Buffer
DSP
Double
Buffer
data in from line
bit by bit
LRxD
data out to line
bit by bit
Transmit
Transmit Buffer
Processing
LTxD
set-up vectors
command vector
Figure 4-12 Data Processing in the GHDLC
4.7.2
GHDLC Channel External Configurations
The GHDLC line interface may be connected to other ICs in three different ways:
• Point-to-point
• Point-to-multi-point
• Multi-slave
4.7.3
GHDLC General Modes
The GHDLC provides three main modes of operation:
• HDLC Mode: In this mode flag recognition/insertion, zero deletion/insertion and CRC
decoding/encoding are performed.
• Asynchronous Mode: This mode is used with request-to-send / clear-to-send
handshaking. In this mode data is transmitted at a very slow rate of up to 300 baud
and controlled directly by the DSP.
Preliminary Data Sheet
4-34
2003-08
DELIC
PEB 20571
Functional Description
4.7.4
GHDLC Protocol Features
The following GHDLC features related to the HDLC protocol may be selected in HDLC
mode:
• Collision Detection: May be active or inactive (relates only to the transmit direction)
• Flags / Ones Interframe: Flags or Ones are transmitted between each frame (relates
to both the transmit and receive direction)
Note that transmitted messages always use unshared flags.
• Shared / Unshared Flag: In shared flag mode only one flag separates adjacent
messages (relates only to the receive direction)
• CRC Mode: Three possible settings: 16-bit CRC / 32-bit CRC / No CRC (relates to
both the transmit and receive directions, and only when operating in the HDLC mode).
• Push-Pull / Open drain: In push pull mode a pin may be driven to ‘1’ or ‘0’. When in
open drain mode a pin may be driven to ‘0’ or high z.
4.7.5
External Configuration and Handshaking in Bus Mode
The GHDLC is connected to the following DELIC interface lines:
LTSC / RTS
LTxD
LRxD
GHDLC
LCxD / CTS
LCLK
Figure 4-13 GHDLC Interface Lines
Serial data is transceived over the LRxD/LTxD lines. The line clock can be driven by an
external GHDLC device or can be generated internally by the PCM clocking path. The
selected internal clock is also driven outward via LCLK.
4.7.5.1
External Tri-State in Point-to-Multi-Point Mode
LTSC is the external tri-state control line. When LTSC is high LTxD is disabled and in
high impedance state. When LTSC is low, LTxD may take on values 0 or 1 when in push
pull mode, 0 or high impedance when in open drain mode.
Preliminary Data Sheet
4-35
2003-08
DELIC
Functional Description
4.7.5.2
Arbitration of GHDLCs on a Collision Bus
Several GHDLC channels (in a point to multi-point configuration) may be connected to
an external signaling backplane. Arbitration between them may be done in two ways:
Polling or Collision Detection.
In Polling mode the GHDLC master (in a point to multi-point configuration) is
responsible to prevent collisions on the line.
In this case a DELIC-slave has to be polled by the GHDLC-master with a special
requesting frame. The DELIC GHDLC-unit simply receives this frame and passes it to
the µP (like any other frame).
Now it’s the task of the µP to handle the message and provide a corresponding answer
message.
When using Collision Detection many GHDLCs may start transmitting at the same
time. If the GHDLC detects a difference between the transmitted bit (LTxD) and the
collision bit (LCxD), the transmission is aborted. The GHDLC will try to send the
message again after the bus was detected idle for a specified time, according to its
priority class (refer to ITU-T I.430, section 6.1.4).
4.7.6
GHDLC Memory Allocation
The memory in the GHDLC is build by a 128x8 bit RAM equally divided between the
GHDLC and the DSP. The GHDLC has a receive buffer and a transmit buffer, divided
into two blocks. One block is allocated to the GHDLC channel in the receive direction,
the other block is read by the DSP. Similarly in the transmit buffer, one block is allocated
to the GHDLC channel in the transmit direction, the other block is written to by the DSP
as shown in Figure 4-14. Note that the GHDLC has higher priority for the buffer access,
whereas the DSP is able to read and write the RAM at a much higher frequency.
In the receive direction blocks are swapped in two cases:
• The receive buffer is full. The swap is issued immediately after the buffer has become
full.
• An end of a frame indication was detected at the beginning of a FSC-frame. To avoid
a loss of data in case of a buffer full indication followed by an end of frame indication,
this condition becomes only true if additionally there was no FULL interrupt during the
previous frame.
In the transmit direction blocks are swapped each time a start transmission command is
issued in the command register.
Preliminary Data Sheet
4-36
2003-08
DELIC
PEB 20571
Functional Description
Receive Buffer
DSP read
Transmit Buffer
DSP write
Block
GHDLC receive
Block
Block
GHDLC transmit
Block
Figure 4-14 GHDLC Receive and Transmit Buffer Structure
The GHDLC unit and DSP always read and write to different areas in the RAM. Memory
is equally allocated to each of the receive and transmit buffer blocks (32 bytes each).
The DSP always writes to the block addresses. The switching between blocks is done
internally and does not concern the DSP.
4.7.7
GHDLC Interrupts
Full Interrupt: A full interrupt is generated if:
• The receive buffer is full. The interrupt is issued immediately after the buffer has
become full.
• An end of a frame indication was detected at the beginning of a FSC frame. To avoid
a loss of data in case of a buffer full indication followed by an end of frame indication,
this condition becomes only true if additionally there was no FULL interrupt during the
previous frame.
Empty Interrupt: An empty interrupt is generated every time a transmit buffer was
emptied by the GHDLC.
Note: Messages with zero byte data content are not supported.
Preliminary Data Sheet
4-37
2003-08
DELIC
Functional Description
4.8
DSP Control Unit
4.8.1
General
The DCU controls the DSP access to DELIC’s blocks. It performs the following tasks:
•
•
•
•
•
•
DSP program and data address decoding
Interrupt handling
Data Bus and Program Bus arbitration
DSP run time statistics
Boot support
Emulation support
4.8.2
DSP Address Decoding
The DCU decodes the DSP data address bus (DXAP) and the DSP program address
bus (PPAP) for performing the following tasks:
• Generating the DSP memory mapped register controls, based on decoding of the
8 MSB lines of the data address bus
• Generating the GHDLC, TRANSIU, HDLCU, IOMU and PCMU RAM controls
• Generating program and data RAM controls upon detection of their address
• Generating the read signal for the program ROM
4.8.3
Interrupt Handling
The following events are reported by the various telecom peripheral blocks to the DSP:
•
•
•
•
•
GHDLC
DMA mailbox
µP mailbox
IOM interface Frame synchronization (FSC) interrupt
PCM interface Frame synchronization (PFS) interrupt
The GHDLC, DMA Mailbox and Microprocessor Mailbox interrupt sources are assigned
to the DSP interrupts (INT0, INT1 and INT2) as shown in Table 4-14. The FSC and PFS
are reported as status bits (require DSP polling) in the Status Event Register (STEVE).
Table 4-14
Interrupt Map
Interrupt
Source
INT0
µP DMA Mailbox
INT1
µP General Mailbox
INT2
FSC & PFS
NMI
GHDLC
Preliminary Data Sheet
4-38
2003-08
DELIC
PEB 20571
Functional Description
Note: The NMI interrupt maybe enabled/disabled in the INTMASK register.
4.8.4
DSP Run Time Statistics
The DSP run time statistics is used for the DSP work load estimation. By using this HW,
the maximum time spent by the DSP from the FSC until the tasks ends may be found.
The DSP statistics include an eight bit counter STATC which is counting up every 1µs.
Reset by FSC of the frame n+1, only if
the DSP has read the counter already
Maximum Value Register
Counter (in Frame n)
1 µs
STATI
STATC
DSP
DSP
Figure 4-15 Statistics Registers
STATC is reset upon FSC rising edge. When the DSP finishes a task, it reads STATC.
The time between two consecutive FSC is always 125 µs, therefore, if the DSP is
working properly, the counter value should always be less then 125 µs.
If the DSP failed to read the counter value and a new FSC rising edge has arrived, the
counter is not reset. Therefore, the DSP reads a value greater then 125. It means that
the DSP failed to finish it’s tasks within the time frame of 125 µs.
The STATI register is added for helping the user to perform the statistics. STATI is a
general purpose 8-bit read/write register.
The user program should perform statistics in the following way:
– The STATC is reset upon detection of FSC rising edge.
– The DSP finishes its activities and reads the value of STATC and STATI. The DSP
compares STATC to the previous maximum value saved in STATI.
– If the new value is larger, it is written to STATI.
The system programmer can get the counter value via µP Mailbox and thus can change
the DSP program.
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Functional Description
4.8.5
Data Bus and Program Bus Arbitration
The internal data bus (GEXDBP) and program data bus (GIP) are tristate buses. Since
these buses must never float, the DCU keeps track of the bus activities. If during a
dedicated cycle no driver is on the bus, the DCU puts a default value on the bus.
4.8.6
Boot Support
The µP boot is the process which loads the external µP program RAM via the µP Mailbox
into the on-chip DSP program RAM. The boot is controlled by a boot routine residing in
the internal DSP program ROM. This routine is started upon DELIC reset according to
the BOOT strap pin status.
The second boot option is the emulation boot, which loads the monitor (BI routine) to the
program RAM. This routine enables the PC emulator to control the DSP.
At system start-up the program code for the DSP is transferred into the internal RAM
from the external uP. The contents for the program and data boot is delivered in a so
called HEX file.
The code format of the HEX file is the following:
Code,:,16 bit address, 16 bit opcode
C:0000 4180
C:0001 0018
C:0004 4180
C:0005 00BA
C:0006 4180
C:0007 00BD
C:000E 4180
C:000F 00BE ...
The program boot starts with the "Start Loading Program RAM" command which is
coming from the DELIC boot routine.
OCMD = 0x1F
This command must be polled from the uP because the interrupt is still not activated.
The uP confirms this with the "Start Boot" command.
MCMD = 0x55
The program code is now transferred in pieces of maximum 15 words by use of the
"Write Program Memory Command".
MDT0 = 0xDESTINATION_ADDRESS
MDTn = 0xOPCODE_WORDn
MCMD = 0xAn
[n=1..15 number of code words to write to address++]
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Functional Description
Before writing this command, the uP must check that the mailbox is free. This is done by
reading the MBUSY bit (bit 7 of address 0x41). The uP must wait until this bit is reset
before sending the next command.
Missing addresses in the HEX file must not be loaded. The "Write Program Memory
Command" must be repeated until the program code is fully loaded. The end of the code
segment inside the HEX file is the change from C: (code) to D: (data). This is the start of
the data segment, which is needed for the Data Boot, described in the next step.
After all the code has been loaded, the "Finish Boot" command must be sent:
MCMD = 0x1F
4.8.7
Reset Execution and Boot Strap Pin Setting
The reset is executed via low signals on the DELIC RESET pin (29) and the VIP RESET
pin (44). It is recommended to connect the VIP RESET inputs to the DELIC RESIND
output pin (89). The RESIND signal is a delayed reset signal and stays at least 500 us
after termination of the DELIC RESET input. This mechanism ensures that all output
clocks of the DELIC have become stable even after a short reset was applied.
Connecting the VIP reset to this RESIND signal ensures stable VIP clocking after reset
(Layer1 clock, DCL2000, FSC).
Together with applying the reset signal to the DELIC, the strap pin signals must be
defined. There are 9 pins at the DELIC device which have a special functionality. These
so called strap pins are used as inputs while reset is active and determine different
modes like master/ slave mode of the PCM interface, test modes, boot mode,... Please
refer to page 2-28 for detailed information about the strap pin options.
The settings of the strap signals are sampled with the rising edge of the DELIC RESET
input signal. For a uP- boot, the default settings of strap 4 (emulation boot) and strap 6
(boot strap) are needed.
After a correct reset execution and strap pin setting, the DELIC sends the command
"Start Loading Program RAM" to the uP: OCMD = 0x1F
Preliminary Data Sheet
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Functional Description
4.9
General Mailbox
4.9.1
Overview
The µP and the DSP communicate via a bidirectional Mailbox according to the mailbox
protocol described in Chapter 11. The DELIC provides two dedicated Mailboxes that
may be used in two operational modes:
• DMA mode in which the two Mailboxes operate independently, one serves as a
general purpose Mailbox and the other serves as a DMA Mailbox.
• Expanded Mailbox mode in which the two Mailboxes are regarded as a enlarged
general purpose Mailbox, providing a double number of registers.
The general purpose Mailbox includes two separate parts:
• µP Mailbox - enables transfers from the µP to the OAK.
• OAK DSP Mailbox - enables transfers from the OAK to the µP.
Both parts include a command register, 9 x (16-bit) registers (17 registers in expanded
mode) and a busy bit. One of the data registers in every part has a special addressing
mode, i.e. the OAK may access either a certain byte of a word or the whole word which
is temporarily stored in the Mailbox. This requires to use 3 different addresses in OAK’s
direction.
Note: The Mailbox protocol commands structure is described in Chapter 11.
4.9.2
µP Mailbox
The µP Mailbox includes:
•
•
•
•
Eight 16-bit data registers (MDTn)
A16-bit general register (MGEN)
An 8-bit command register (MCMD)
A 1-bit busy register (MBUSY)
Registers MDTn, MGEN and MCMD may be written by the µP and read by the OAK. The
MBUSY register may be written by the DSP and read by the µP.
A write of the µP to the MCMD-register of the µP-mailbox generates an interrupt to the
OAK. Thus, the user has to provide all mailbox data prior to writing to register MCMD.
The MBUSY bit which may be read by the µP (register MBUSY) is set automatically after
a write to the µP command register (MCMD) and reset automatically by a direct OAK
write operation to it.
Note: The command Opcodes are defined in Chapter 11.
Data Transfer from the µP to the OAK
• The µP reads the busy bit and checks whether the Mailbox is available (MBUSY=’0’)
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Functional Description
• The µP writes to the Data registers MDTn(optional)
• The µP writes to the µP Command register (MCMD), this write must be performed and
sets automatically the µP Mailbox busy bit (MBUSY).
• An OAK interrupt (INT2) is activated due to the write to the Command register
(MCMD).
• The OAK INT2 routine reads MCMD and performs the command (the read of the
command register resets the INT2 activation signal).
• When finished, the INT2 routine resets MBUSY for enabling the µP to send the next
command.
Note: The µP may perform consecutive writes to the µP Mailbox, and the user must
guarantee that the data has been transferred to the OAK correctly (the busy bit has
been reset) before writing new data to the µP Mailbox.
4.9.3
OAK Mailbox
The OAK Mailbox includes:
•
•
•
•
Eight 16-bit data registers (ODTx)
A 16-bit general register (OGEN)
An 8-bit command register (OCMD)
A 1-bit busy register (OBUSY)
Registers ODTx, OGEN and OCMD may be written by the OAK and read by the µP. The
OBUSY bit may be written by the µP and read by the OAK. In addition, the µP can read
this bit (because the µP could poll this bit).
A write of the OAK to register OCMD of the OAK mailbox generates an interrupt to the
µP. Thus the OAK firmware provides all mailbox data prior to writing to register OCMD.
The OBUSY- bit which can be read by the OAK, is set automatically after a write of the
OAK to register OCMD and is reset by a direct µP write to it (when the µP has finished
reading the OAK Mailbox contents).
Note: The Opcodes indications are defined in Chapter 11.
Data Transfer from the OAK to the µP
• The OAK reads the busy bit and checks whether the MB is available (OBUSY=’0’)
• The OAK writes to the data registers ODTn (optional)
• The OAK writes to the command register (OCMD). This write must be performed and
automatically sets the OAK Mailbox busy bit (OBUSY)
• A µP interrupt is activated due to the write operation to the register OCMD.
• The µP reads the command register and performs the command.
• When finished, the µP resets OBUSY for enabling the OAK to send the next
command.
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Functional Description
Note: The OAK may perform consecutive writes to the OAK Mailbox and the OAK
firmware guarantees that the data has been transferred to the µP correctly
(OBUSY has been reset) before writing new data to the OAK Mailbox.
Preliminary Data Sheet
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PEB 20571
Functional Description
4.10
DMA Mailbox
4.10.1
Overview
This Mailbox is used for DMA transfers of data in “memory-to-memory” or “flyby” modes.
In a special mode, it may be used as an extension to the General Purpose Mailbox.
The transfer is done similarly to the general Mailbox, with some differences:
1. There are 2 configurations: DMA, and secondary Mailbox.
2. The master of the transfer in DMA mode is always the OAK.
The DMA Mailbox includes two separate parts:
• Transmit (µP) Mailbox for fast transfers from the DMA (µP) to the GHDLC (OAK).
• Receive (OAK) Mailbox for fast transfers from the GHDLC (OAK) to the DMA (µP).
In transactions between µP and OAK the later indicates when it is ready for transmit /
receive operation by driving DREQT/DREQR high, and µP replies by driving DACK low.
DACK acts like a Chip Select signal and remains low during the whole transaction. By
driving DACK high the DMA may stop the transaction on any stage, even if the data
transfer has not finished yet.
There are two possible modes in DMA transfers: Memory-to-memory and Flyby.
Selecting these modes is done by writing “1” or “0” to the Configuration Register.
The mode of DMA’s operation depends on the µP that initiates a DMA transfer (Intel/
Siemens or Motorola). This mode information is provided via the MODE input pin of the
DELIC.
The number of bytes (words) to be transferred is written to TX_CREG and copied to
TX_COUNT.
After finishing a transaction, INT1 is issued to the DSP in order to indicate that the
Mailbox is empty and available for the next operation.
4.10.2
Intel/Siemens Mode and Motorola Mode (Memory-to-Memory)
In Intel/Siemens mode the control lines are DACK, RD, WR . Driving RD low when DACK
is low causes a ‘Read’ from the Mailbox. Driving WR low when DACK is low causes a
‘Write’ to the Mailbox.
In Motorola mode the control lines are DACK, R/W, DS. Driving R/W high when DACK
and DS are low causes a ‘Read’ from the Mailbox. Driving R/W low when DACK and DS
are low causes a ‘Write’ to the Mailbox.
4.10.3
Fly-By Mode
In Fly-By mode DMA transfer is done in one bus transaction. The DMA should provide a
‘Read’ command to the Mailbox and, at the same time, a ‘Write’ command to the system
memory (or a ‘Write’ to the Mailbox and a ‘Read’ to the memory). The system memory
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Functional Description
must always get a ‘Write’ command for a write operation or a ‘Read’ for a read operation.
The Mailbox, however, reacts in the opposite way: it writes (puts data into a register)
upon receiving a ‘Read’ command and reads (drives data on the bus) upon receiving a
‘Write’ command.
4.10.4
PEC Mode
The additional mode which is possible in work with some Siemens µPs is PEC mode. In
this case DMA controller is edge sensitive, so edges are provided on DREQ lines in order
to initiate every DMA transfer.
4.10.5
Transmit Mailbox
The Transmit Mailbox includes:
• 18-byte FIFO which is accessed by the OAK (for Read) as 9 “regular” addressed 16bit-wide registers and by the DMA (for Write) like a FIFO. One of the nine registers is
a “special” register like in the General Mailbox and has 3 addresses associated with it.
• 5-bit counter for the general number of transactions in current transfer (TX_CREG)
• 5-bit counter for the number of transactions that remains in the transfer (TX_CNT).
• 1-bit status register (TX_STAT).
The OAK is always the master of this transfer, i.e. the transfer is initiated b the OAK, but
the functions of control and arbitration during the transfer are done by the DMA.
For DMA request, the OAK requests transfer of data to the high-speed GHDLC channel.
It writes the number of bytes needed to the TX_CREG register which sets TX_BSY bit,
and causes the assertion of DREQT (“DMA Request Transmit”) pin.
For DMA acknowledge, the DMA grants the bus to OAK by driving DACK low, and
begins toggling the control lines. In Intel/Siemens (Mem-to-Mem) mode it drives the WR
line low when it writes to the Mailbox, and high when it reads from the memory on the
second side. RD line stays high during the complete transfer, because there are no
‘Read’ operations from here. DACK is low all the time. In Motorola (Mem-to-Mem) mode
it drives R/W line low for ‘Write’ operations when DACK and DS are low; when DMA
refers to the external memory, it drives DS high.
Note that in Fly-by mode the meaning of ‘Read’ and ‘Write’ commands is opposite for the
Mailbox. After every ‘Write’ operation the counter (TX_CNT) is decremented by one. If
the DMA stops the transaction before finishing, it has to drive DACK high. The OAK
continues driving DREQT high, stops decrementing TX_CNT and waits until DACK
becomes low.
After a write of TX_CREG bytes by the DMA to the Transmit Mailbox, the TX_CNT
becomes ‘0’. Then TX_BSY bit is reset to ’0’, and DREQT is deasserted. A reset of
TX_BSY bit may be programmed to generate an interrupt (INT1) to the OAK.
The OAK will then read TX_CREG bytes from the Mailbox to the GHDLC, the first byte
being the LSB of the least significant word of the FIFO. Note that in case of an odd
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Functional Description
number of bytes to be transferred the last byte is available on the least significant byte
of the last word in FIFO.
Note: TX_BSY is not an indication for the transaction partners. It may be used for
internal software needs of the OAK.
Data Transfer via the Transmit Mailbox
•
•
•
•
•
•
The OAK writes to TX_CREG.
DREQT is asserted (’high’), and TX_BSY bit is set (’1’).
The DMA asserts DACK = 0 and issues TX_CREG write transactions to the Mailbox.
DREQT is deasserted (’low’), and TX_BSY bit is reset (’0’).
If TX_MASK bit is reset (’0’): an OAK interrupt (INT1) is activated.
The OAK reads the TX_REG bytes in the Mailbox and transfers them to the GHDLC.
Note: 1. The OAK must not write to the TX_CREG reg before TX_BSY is reset.
2. Writing’0’ to TX_CREG is not allowed.
4.10.6
Receive Mailbox
The Receive Mailbox includes:
• 18-byte FIFO which is accessed by the OAK (for write) as 9 “regular” addressed 16bit wide registers, and by the DMA (for read) like a FIFO. One of the nine registers is
a “special” register like in the General Mailbox and has 3 addresses associated with it.
• 5-bit counter for the general number of transactions in current transfer (RX_CREG).
• 5-bit counter for number of transactions that remains in the transfer (RX_CNT).
• 1-bit status register (RX_STAT).
Like in the Transmit Mailbox, the OAK is always the master of this transfer, i.e. the
transfer is initiated by the OAK, but controlled by DMA.
When the OAK requests a transfer of data from the high-speed GHDLC channel, it writes
this data to the Receive Mailbox, the first byte to the least significant byte of the least
significant word. Note that in case of odd number of bytes, the most significant byte of
the last word is don’t care.
Then, the OAK writes the number of bytes needed to the RX_CREG register which sets
RX_BSY bit, and causes the assertion of DREQR (“DMA Request Receive”) pin.
If DMA grants the bus to OAK, it drives DACK low and begins toggling the control lines.
In Intel/Siemens (Mem-to-Mem) mode it drives RD line low when it reads from the
Mailbox and high when it writes to the memory. WR line stays high during the complete
transfer, because there are no ‘Write’ operations from here. DACK is low all the time. In
Motorola (Mem-to-Mem) mode it drives R/W line high for ‘Read’ operations when DACK
and DS are low; when DMA refers to the external memory, it drives DS high.
Note that in Fly-by mode the meaning of ‘Read’ and ‘Write’ commands is opposite for the
Mailbox. After each ‘Read’ operation the counter (RX_CNT) is decremented by one. If
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Functional Description
the DMA stops the transaction before finishing, it has to drive DACK high. The OAK
continues driving DREQR high, stops decrementing RX_CNT and waits until DACK
becomes low.
After a read of RX_CREG bytes by the DMA from the Receive Mailbox, the RX_CNT
becomes ‘0’. Then RX_BSY bit is reset to ’0’, and DREQR is deasserted . Reset of
RX_BSY bit may be programmed to cause an interrupt (INT1) to the OAK.
Note: RX_BSY is not an indication for the transaction partners. It may be used for
internal software needs of the OAK .
Data Transfer via the Receive Mailbox
•
•
•
•
•
•
The OAK writes RX_CREG bytes to Receive Mailbox.
The OAK writes to RX_CREG.
DREQR is asserted (’high’), and RX_BSY bit is set (’1’).
The DMA asserts DACK and issues RX_CREG read transactions to the Mailbox.
DREQR is deasserted (’low’), and RX_BSY bit is reset (’0’).
If RX_MASK bit is reset (’0’): an OAK interrupt (INT2) is activated.
Note: 1. The OAK must not write to the RX_CREG reg before RX_BSY is reset.
2. Writing ’0’ to RX_CREG is not allowed.
4.10.7
Access to the DMA FIFOs
The size of the FIFOs is 18 bytes (9 words) for each Tx and Rx. On the OAK side, each
FIFO contains 9 registers (TDT0-8 and RDT0-8) which may be accessed separately. On
the DMA side, only the current top of the FIFO is available.
The transfer is divided to bulks, the size of the current bulk is determined in the
RX_CREG/TX_CREG.
Transmit FIFO
This FIFO is written by the DMA. The first write in a bulk will be to TDT0 least significant
byte, the second to TDT0 most significant byte, etc., until the size of the current bulk was
reached. Then the OAK will read the data from the relevant TDTn registers.
Receive FIFO
This FIFO is written by the OAK. The OAK fills RDT0 to RDTn. The DMA will then read
consecutive bytes from the FIFO, where the first byte will be RDT0 least significant byte,
the 2nd RDT0 most significant byte, etc. until the size of the current bulk was reached.
Note: This Rx FIFO and Tx FIFO functionality is only provided when the Mailbox is in
DMA mode (CFG:DMA = ‘1’). In case of non DMA mode (CFG:DMA = ‘0’), the
FIFOs are used as secondary (extension) to the General Purpose Mailbox, which
means that the General Purpose Mailbox will have 18 words for each direction
(OAK and µP), instead of 9.
Preliminary Data Sheet
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Functional Description
4.11
DSP Core OAK+
The DELIC integrates an OAK+ DSP core, an enhanced version of the OAK. It is clocked
using an on-chip PLL at a frequency of 61.44 MHz. It may also be driven by lower clock
rates provided by an external oscillator.
The OAK+ is a high performance fixed-point DSP with a 16-bit data and program bus.
Due to an optimized cost-performance rate, it is widely used not only in Line Cards and
PBX applications, but also in cellular phones, fast modems, advanced fax machines, and
answering machines.
The core’s main block is a high performance central processing unit, including a fullfeatured bit manipulation unit, RAM and ROM addressing units, and Program control
logic. All other application specific peripheral blocks, are defined as part of the user onchip logic.
The OAK+ provides an advanced set of DSP and generic microprocessor functions for
straightforward generation of efficient and compact code.
For more details on OAK architecture please refer to “DOC DSP Programmer’s
Reference Manual, 11.97”.
Preliminary Data Sheet
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Functional Description
4.12
Clock Generator
4.12.1
Overview
The DELIC clock generator provides all necessary clock signals for the DELIC and
connected clock slave devices. The internal clocks are generated by two on-chip PLLs:
1. A digital controlled oscillator (DCXO) generates a 16.384 MHz clock from an external
crystal.
2. A PLL multiplies the 16.384 MHz clock to a 61.44 MHz clock.
An overview of the clock signals and a block diagram is shown below.
Table 4-15
Overview of Clock Signals
Pin
Function
I/O During Reset
CLK16-XI
16.384 MHz External Crystal Input
I
I
CLK16-XO 16.384 MHz External Crystal Output
O
O
XCLK
External Reference Clock from layer-1 IC
(2.048 MHz, 1.536 MHz or 8 kHz)
I
I
(1.536 MHz)
REFCLK
PCM Reference Clock (8 kHz or 512 kHz)
I/O tristate
PFS
PCM Frame Synchronization 8 kHz (I/O) or 4 kHz (I) I/O I (Slave)
O (Master)
PDC
PCM Data Clock (2.048, 4.096, 8.192 or 16.384 MHz) I/O I (Slave)
O (Master)
(2.048 MHz)
CLKOUT
Auxiliary Clock
(2.048, 4.096, 8.192, 16.384, or 15.36 MHz)
O
O
(2.048 MHz)
DCL_2000 IOM-2000 Data Clock (3.072, 6.144 or 12.288 MHz)
O
O
(3.072 MHz)
DCL
IOM-2 Data Clock
(384 kHz, 768 kHz, 2.048 MHz or 4.096 MHz)
O
O
(384 kHz)
FSC
IOM-2 and IOM-2000 Frame Synchronization 8 kHz. O
O
L1_CLK
Layer-1 Clock 15.36 or 7.68 MHz
(e.g. OCTAT-P / QUAT-S)
O
(7.68 MHz)
DSP_CLK
DSP Test Clock.
I
(to run the DSP at clock rates other than 61.44 MHz)
Preliminary Data Sheet
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Functional Description
XCLK
REFCLK
(reference clock from (reference clock
L1 device,
PCM)
1.536 MHz or
512 kHz / 8 kHz
2.048 MHz or
8 KHz)
16.384 MHz
CLK16-XO
CLK16-XI
Filter
DELIC
SHP
REFS
PD
DCXO
:1
:3
:4
:192
:256
16.384 MHz
3.072 MHz
6.144 MHz
12.288 MHz
DCL_2000
DSP_CLK
(Fallback)
PLL
61.44
:20 MHz
:192
:256
:1
:10
:5
8
KHz
MUX
8
KHz
8
KHz
:2
:8
:1
:2:2
:15
:2
:30
:80
:160
PFS
:256
M/S(strap
option)
2.048
MHz
:2
:2
8.192
MHz
M/S
MUX
4.096
MHz
384 kHz
768 kHz
1.536 MHz
2.048 MHz
4.096 MHz
DCL
8 kHz
FSC
8
KHz
8 kHz
MUX
DSP CLK
15.36 MHz
7.68 MHz
L1_CLK
:64
:1
CLKOUT
:2
Short
FSC
:48
:2:96
:256
:512
PDC
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
LCLK
16.384 MHz
15.36 MHz
MUX
GHDLC
Figure 4-16 DELIC Clock Generator
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Functional Description
4.12.2
DSP Clock Selection
The default DSP clock is the internal 61.44 MHz generated by the PLL. For test purpose,
a different frequency may be provided via DSP_CLK input pin. The selection between
the internal 61.44 MHz or external clock source is done by the DSP_FRQ input pin.
4.12.3
PCM Master/Slave Mode Clocks Selection
In PCM Master mode, the PFS and PDC are derived from the internal 16.384 MHz
signal, and driven to the PCM interface via the PFS pin (output) and PDC pin (output).
In PCM Slave mode, the PFS and PDC are generated from an external signal, and input
to the DELIC via the PFS pin and the PDC pin.
Note: During reset, a strap pin determines whether the DELIC operates in clock Master
or Slave mode.
4.12.4
DELIC Clock System Synchronization
The PCM clock division chain is synchronized to an external reference clock, used as
one of the inputs to a phase comparator, after being divided into 8 KHz. The other phase
comparator input is the 8 KHz clock, derived from the 16.384 MHz clock. The phase
comparator output is used as control input of the DCXO, after being filtered by a low-pass
filter. The reference clock can be driven by one of the following input pins:
• XCLK - 2.048 MHz, 1.536 MHz or 8 KHz:
Can be driven by a layer-1 transceiver (e.g. VIP, QUAT-S) connected to the Central
Office. Only a clock master DELIC can be synchronized directly according to this
input. In other cases (clock slave DELIC), this input signal may be divided to 8 KHz or
512 KHz, and driven out via REFCLK, in purpose to be used for the synchronization
of the clock-master DELIC.
• REFCLK - 512 KHz or 8 KHz:
Used for synchronization of the clock master DELIC, when not synchronized by XCLK.
Usually this signal is driven by a clock slave DELIC, or another PBX in the system. In
a clock slave DELIC this pin is used as output.
• PFS - 8 KHz:
Driven by the system clock master. May be used for synchronization of the clock slave
DELICs. In a clock master DELIC this pin is used as output.
4.12.5
IOM-2 Clock Selection
The IOM-2 interface clocks FSC and DCL are always output.
The FSC output signal is usually generated with 50% duty cycle. A short FSC pulse is
required for multiframe start indication (one DCL cycle long). One cycle after the short
FSC pulse, the normal FSC is generated again with 50% duty cycle.
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Functional Description
4.12.6
IOM-2000 Clock Selection
The IOM-2000 interface uses the same FSC like IOM-2, whereas the data clock
DCL2000 is a dedicated pin (always output).
4.12.7
REFCLK Configuration
REFCLK is an I/O pin for synchronizing the PCM interface (to 8 kHz or 512 kHz).
The clock master DELIC may synchronize the internal clocks to REFCLK by selecting
REFCLK as the reference clock source.
A clock slave DELIC may use REFCLK as output, when REFCLK is driven by the XCLK
input pin. The slave DELIC may transfer the XCLK signal to the clock master DELIC, and
enable the clock master to synchronize to a layer-1 device, which is connected to
another DELIC in the system.
4.12.8
GHDLC Clock Selection
Any of the next signals may be provided to the GHDLC channel as input clock:
1. LCLK Input Pin
This option is possible only when a LNC interface is assigned to the GHDLC unit.
2. 2.048 MHz, 4.096 MHz, or 8.192 MHz
These clock signals are generated internally by the PCM clocking path. The selected
internal clock is also driven outward via LCLK.
Note that one of these signals must be selected as the clock of the GHDLC channel
when the DELIC is the clock master of this channel.
Preliminary Data Sheet
4-53
2003-08
DELIC
DELIC Memory Structure
5
DELIC Memory Structure
The following tables provide the DELIC memory map for the DSP and the µP.
5.1
DSP Address Space
5.1.1
DSP Register Address Space
T
Table 5-1
DSP Registers Address Space
Address
Description
D000 - D01F
DCU registers
D020 - D03F
A/µ-law registers
D040 - D05F
IOMU registers
D060 - D07F
PCMU registers
D080 - D09F
Clocks registers
D0A0 - D0BF
TRANSIU registers
D0C0 - D0DF
GHDLC registers
D100 - D17F
µP Mailbox and DMA Mailbox registers
D180 - D1FF
HDLCU registers
D1A0 - DFFF
not used
5.1.2
DSP Program Address Space
Table 5-2
DSP Program address space
Address
Size
Description
0000 - 0FFF
4Kw
Program RAM
1000 - F7FF
58Kw
Not used
F800 - FFFF
2Kw
Program ROM
Preliminary Data Sheet
5-1
2003-08
DELIC
DELIC Memory Structure
5.1.3
DSP Data Address Space
A1
Table 5-3
Occupied DSP Data Address space
Address
Size
Description
0000 - 03FF
1Kw
Internal XRAM
2000 - 203F
64w
GHDLC data buffer
2040 - 207F
64w
reserved for testt (**)
4000 - 401F
32w
HDLCU receive output buffer
4020 - 403F
32w
HDLCU transmit input buffer
4040 - 405F
32w
HDLCU command RAM
4060 - 407F
32w
HDLCU receive input buffer
4080 - 409F
32w
HDLCU transmit output buffer
40A0 - 40BF
32w
HDLCU status buffer
6000 - 605F
96w
TRANSIU receive data buffer
6080 - 60DF
96w
TRANSIU transmit data buffer
6100 - 61BF
192w
reserved for test (**)
6200 - 6248
72w
reserved for test (**)
6280 - 62C8
72w
reserved for test (**)
8000 - 803F
64w
IOMU receive data buffer
8040 - 807F
64w
IOMU transmit data buffer
8080 - 80FF
128w
reserved for test (**)
9000 - 9017
24w
HRAM for U PN scrambler
9020 - 9037
24w
HRAM for U PN descrambler
A000 - A07F
128w
PCMU receive data buffer
A080 - A0FF
128w
PCMU transmit data buffer
A100 - A1FF
256w
reserved for testt (**)
D000 - DFFF
4Kw
OAK memory mapped registers(*)
E000 - E1FF
0.5Kw
A/µ-Law ROM
F400 - F7EE
1Kw-16w
Emulation mail box (on SCDI)
F7F0 - F7FF
16w
OCEM® Registers
FC00 - FFFF
1Kw
Internal YRAM
Preliminary Data Sheet
5-2
2003-08
DELIC
DELIC Memory Structure
Note: (*) The OAK memory mapped registers address space is described in the
following table:
(**) Accessing these addresses may cause unpredictable results
Table 5-4
5.2
OAK memory mapped registers address space
Address
Description
D000 - D01F
DCU registers
D020 - D03F
A/m-law registers
D040 - D05F
IOMU registers
D060 - D07F
PCMU registers
D080 - D09F
Clocks registers
D0A0 - D0BF
TRANSIU registers
D0C0 - D0DF
HDLCU registers
D100 - D17F
CPU+DMA mailbox registers
D180 - D1FF
GHDLC registers
D1A0 - DFFF
not used
µP Address Space
The µP address space consists of the general mail-box registers, the DMA mail-box
registers (only in non-DMA mode), the µP-interface control register, and the µP-interface
status register (MISR)
.
Table 5-5
µP Address Space Table
Address
Description
00H - 43H
60H - 62H
µP- mail box registers
48H, 68H, 6AH
µP-configuration registers
6BH - 7FH
Reserved. Accessing these addresses may
cause unpredictable results
Preliminary Data Sheet
5-3
2003-08
DELIC
Register Description
6
Register Description
6.1
Register Map
Table 6-1
TRANSIU Register Map
Reg Name
Access Address
Reset
Value
Comment
Page
No.
TICR
RD/WR
D0A0H
0000H
IOM-2000 global configuration
6-10
TCCR0
RD/WR
D0A1H
FFFFH
Channel 7..0 configuration
6-11
TCCR1
RD/WR
D0A2H
FFFFH
Channel 15..8 configuration
6-11
TCCR2
RD/WR
D0A3H
FFFFH
Channel 23..16 configuration
6-11
VIPCMR0
WR
D0A8H
0000H
VIP_0 command registers
6-12
VIPCMR1
WR
D0A9H
0000H
VIP_1 command registers
6-12
VIPCMR2
WR
D0AAH
0000H
VIP_2 command registers
6-12
VIPSTR0
RD
D0AC
0000H
VIP_0 status register
6-14
VIPSTR1
RD
D0ADH
0000H
VIP_1 status register
6-14
VIPSTR2
RD
D0AEH
0000H
VIP_2 status register
6-14
TICCMR
WR
0000H
D0B0H
(LS-word)
D0B1H
0000H
(MS-word)
Channel initialization command
6-15
TICSTR
RD
0000H
D0B2H
(LS-word)
D0B3H
0000H
(MS-word)
Channel initialization status
6-20
Table 6-2
Scrambler Register Map
Reg Name
Access Address
Reset
Value
Comment
Page
No.
SCMOD
RD/WR
D010H
0003H
Scrambler mode
6-21
SCSTA
RD/WR
D011H
undef.
Scrambler status
6-21
Preliminary Data Sheet
6-1
2003-08
DELIC
Register Description
Table 6-3
IOMU Register Map
Reg Name
Access Address
Reset
Value
Comment
Page
No.
ICR
R/W
D040H
0002H
IOMU Control
6-22
ISR
R
D041H
undef.
IOMU Status
6-23
ITSCR
Set (W)
D042H
0000H
IOMU Tri-State Control
6-24
Reset
(W)
D043H
R
D044H
IDRDYR
R
D045H
undef.
IOMU DRDY
6-25
IDPR
R/W
D046H
00E0H IOMU Data Prefix
6-26
Table 6-4
PCMU Register Map
Reg Name
Access Address
Reset
Value
Comment
Page
No.
PCR
RD/WR
D060H
00H
PCMU Control
6-27
PSR
RD
D061H
undef.
PCMU Status
6-28
PTSC0
RD/WR
00H
D062H
(read/set)
D063H
(read/reset)
PCMU Tristate control 0
6-29
PTSC1
RD/WR
00H
D064H
(read/set)
D065H
(read/reset)
PCMU Tristate control 1
6-29
PTSC2
RD/WR
00H
D066H
(read/set)
D067H
(read/reset)
PCMU Tristate control 2
6-29
PTSC3
RD/WR
00H
D068H
(read/set)
D069H
(read/reset)
PCMU Tristate control 3
6-29
Preliminary Data Sheet
6-2
2003-08
DELIC
Register Description
Table 6-4
PCMU Register Map (Continued)
Reg Name
Access Address
PTSC4
RD/WR
PTSC5
Reset
Value
Comment
Page
No.
00H
D06AH
(read/set)
D06BH
(read/reset)
PCMU Tristate control 4
6-29
RD/WR
00H
D06CH
(read/set)
D06DH
(read/reset)
PCMU Tristate control 5
6-29
PTSC6
RD/WR
00H
D06EH
(read/set)
D06FH
(read/reset)
PCMU Tristate control 6
6-29
PTSC7
RD/WR
00H
D070H
(read/set)
D071H
(read/reset)
PCMU Tristate control 7
6-29
PDPR
RD/WR
D072H
PCMU Data Prefix
6-30
E0H
.
Table 6-5
A-/µ-law Unit Register Map
Reg Name
Access Address
Reset
Value
Comment
Page
No.
AMCR
R/W
D020H
00H
A/µ-law Unit Control
6-31
AMIR
W
D021H
undefin A/µ-law Unit Input
ed
6-31
AMOR
R
D022H
undefin A/µ-law Output
ed
6-32
Table 6-6
HDLCU Register Map
Reg Name
Access Address
Reset
Value
Comment
Page
No.
HCR
W
D180H
0001H
HDLC Control
6-33
HSTA
R
D180H
0001H
HDLC Status
6-34
Preliminary Data Sheet
6-3
2003-08
DELIC
Register Description
Table 6-6
HDLCU Register Map (Continued)
Reg Name
Access Address
Reset
Value
HCCV
R/W
4040H-405FH
undefin Channel Command Vector
ed
HCSV
R
40A0H-40BFH undefin Channel Status Vector
ed
Table 6-7
GHDLC Register Map
Reg Name
Access Address
Reset
Value
Comment
Page
No.
GTEST
W
D0C0H
0001H
GHDLC Test/ Normal Mode
6-38
GCHM
W
D0C1H
0000H
GHDLC Channel Mode
6-38
GINT
R
D0D4H
0000H
GHDLC Interrupt
6-39
GFINT
R/W
D0D3H
0000H
GHDLC Frame Interrupt
6-39
GRSTA0
R
D0C2H
001FH
GHDLC Receive Status cha. 0
6-40
GRSTA1
R
D0C3H
001FH
GHDLC Receive Status cha. 1
6-40
GRSTA2
R
D0C4H
001FH
GHDLC Receive Status cha. 2
6-40
GRSTA3
R
D0C5H
001FH
GHDLC Receive Status cha. 3
6-40
RXDAT
RD
2000H203FH
0000H
Receive data and status
6-41
GMOD0
W
D0C6H
0140H
GHDLC Mode cha. 0
6-42
GMOD1
W
D0C7H
0140H
GHDLC Mode cha. 1
6-42
GMOD2
W
D0C8H
0140H
GHDLC Mode cha. 2
6-42
GMOD3
W
D0C9H
0140H
GHDLC Mode cha. 3
6-42
GTCMD0
W
D0CAH
0000H
GHDLC TX Command cha. 0
6-43
GTCMD1
W
D0CCH
0000H
GHDLC TX Command cha. 1
6-43
GTCMD2
W
D0CEH
0000H
GHDLC TX Command cha. 2
6-43
GTCMD3
W
D0D0H
0000H
GHDLC TX Command cha. 3
6-43
GASYNC
R/W
D0D2H
0000H
ASYNC Control/ Status
6-44
GLCLK0
R/W
D08AH
0000H
LCLK0 Control Register
6-45
GLCLK1
R/W
D08BH
0000H
LCLK1 Control Register
6-46
GLCLK2
R/W
D08CH
0000H
LCLK2 Control Register
6-47
Preliminary Data Sheet
6-4
Comment
Page
No.
6-35
6-36
2003-08
DELIC
Register Description
Table 6-7
GHDLC Register Map (Continued)
Reg Name
Access Address
Reset
Value
Comment
Page
No.
GLCLK3
R/W
D08DH
0000H
LCLK3 Control Register
6-48
MUXCTRL
R/W
D14AH
0000H
Multiplexer Control
6-49
Table 6-8
DCU Register Map
Reg Name
Access
Address
Reset
Value
Comment
Page
No.
IMASK
R/W
D002H
0000H
Interrupt Mask
6-50
STEVE
R
D003H
0000H
Status Event
6-50
STATC
R
D004H
unchan. Statistics Counter
6-51
STATI
R
D005H
0000H
6-52
Table 6-9
µP Configuration Register Map
Regist. DesReset
(16 bit) cription Value
Statistics
Bit
µPµP
DSP
Addr.
Byte
Word
Access Access MSB
of
Word
µPAddr.
LSB
of
Word
DSP
Addr.
Page
No.
MCFG
configur 0H
ation
6
R
R/W
none
48H
D148H
6-52
VDEV
device
version
hardwired
8
none
R
none
6AH
none
6-54
IVEC
int
vector
reg
unchanged
8
R/W
R
none
68H
D168H
6-54
Preliminary Data Sheet
6-5
2003-08
DELIC
Register Description
Table 6-10
General Mailbox Register Map
Register Descrip(16 bit) tion
Reset
Value
Bit DSP
µP
µPWord
Byte Addr.
Access Acc. MSB
of
Word
µPAddr.
LSB
of
Word
DSP
Addr.
Page
No.
MCMD
µP
command
00H
8
R
W
none
40H
D140H 6-55
MBUSY
µP MB busy
0H
1
W
R
41H
none
D141H 6-55
MGEN
µP generic
data reg.
unchanged 16
R
W
43H
42H
D142H 6-56
(LSB)
D143H
(MSB)
D144H
(All)
MDT0
µP data reg0 unchanged 16
R
W
01H
00H
D100H 6-57
MDT1
µP data reg1 unchanged 16
R
W
03H
02H
D102H 6-57
MDT2
µP data reg2 unchanged 16
R
W
05H
04H
D104H 6-57
MDT3
µP data reg3 unchanged 16
R
W
07H
06H
D106H 6-57
MDT4
µP data reg4 unchanged 16
R
W
09H
08H
D108H 6-57
MDT5
µP data reg5 unchanged 16
R
W
0BH
0AH
D10AH 6-57
MDT6
µP data reg6 unchanged 16
R
W
0DH
0CH
D10CH 6-57
MDT7
µP data reg7 unchanged 16
R
W
0FH
0EH
D10EH 6-57
OCMD
DSP
command
00H
8
W
R
none
60H
D160H 6-57
OBUSY
DSP MB
busy
0H
1
R
R/W
61H
none
D161H 6-58
OGEN
DSP generic unchanged 16
data reg
W
R
63H
62H
D162H 6-59
(LSB)
D163H
(MSB)
D164H
(All)
ODT0
DSP data
reg0
W
R
21H
20H
D120H 6-59
Preliminary Data Sheet
unchanged 16
6-6
2003-08
DELIC
Register Description
Table 6-10
General Mailbox Register Map (Continued)
Register Descrip(16 bit) tion
Reset
Value
µPµP
Bit DSP
Byte Addr.
Word
Access Acc. MSB
of
Word
µPAddr.
LSB
of
Word
DSP
Addr.
Page
No.
ODT1
DSP data
reg1
unchanged 16
W
R
23H
22H
D122H 6-59
ODT2
DSP data
reg2
unchanged 16
W
R
25H
24H
D124H 6-59
ODT3
DSP data
reg3
unchanged 16
W
R
27H
26H
D126H 6-59
ODT4
DSP data
reg4
unchanged 16
W
R
29H
28H
D128H 6-59
ODT5
DSP data
reg5
unchanged 16
W
R
2BH
2AH
D12AH 6-59
ODT6
DSP data
reg6
unchanged 16
W
R
2DH
2CH
D12CH 6-59
ODT7
DSP data
reg7
unchanged 16
W
R
2FH
2EH
D12EH 6-59
Note: MDT8..15 and ODT8..15 are accessible only in non-DMA mode, when the DMA
Mailbox data registers are used for doubling the size of General Mailbox.
Table 6-11
DMA Mailbox Register Map
Register
Description
Reset
Value
DSP Page
µP
Bit DSP
DMA µP
Addr. No.
Access / µP MSB LSB
Acc. Addr. Addr.
DTXCNT
Tx counter
0H
4
R/W
none none
none
D150
6-60
H
DINSTA
DMA Int status 0H
4
R
none none
none
D152
6-61
H
TDT0/
MDT8
Tx data reg0/
µP data reg8
un16 R
changed
W
TDT1/
MDT9
Tx data reg1/
µP data reg9
un16 R
changed
W
TDT2/
MDT10
Tx data reg2/ un16 R
µP data reg10 changed
W
Preliminary Data Sheet
11H
10H
D110
6-57
H
13H
12H
D112
6-57
H
15H
14H
D114
6-57
H
6-7
2003-08
DELIC
Register Description
Table 6-11
DMA Mailbox Register Map (Continued)
Description
TDT3/
MDT11
Tx data reg3/ un16 R
µP data reg11 changed
W
TDT4/
MDT12
Tx data reg4/ un16 R
µP data reg12 changed
W
TDT5/
MDT13
Tx data reg5/ un16 R
µP data reg13 changed
W
TDT6/
MDT14
Tx data reg6/ un16 R
µP data reg14 changed
W
TDT7/
MDT15
Tx data reg7/ un16 R
µP data reg15 changed
W
DRXCNT Rx counter
Reset
Value
DSP Page
µP
Bit DSP
DMA µP
Addr. No.
Access / µP MSB LSB
Acc. Addr. Addr.
Register
0H
4
17H
16H
D116
6-57
H
19H
18H
D118
6-57
H
1BH
1AH
D11A
6-57
H
1DH
1CH
D11C 6-57
H
1FH
1EH
D11E
6-57
H
R/W
none none
none
D170
6-60
H
RDT0/
ODT8
Rx data reg0/ un16 W
DSP data reg8 changed
R
RDT1/
ODT9
Rx data reg1/ un16 W
DSP data reg9 changed
R
RDT2/
ODT10
Rx data reg2/
DSP data
reg10
un16 W
changed
R
RDT3/
ODT11
Rx data reg3/
DSP data
reg11
un16 W
changed
R
RDT4/
ODT12
Rx data reg4/
DSP data
reg12
un16 W
changed
R
RDT5/
ODT13
Rx data reg5/
DSP data
reg13
un16 W
changed
R
RDT6/
ODT14
Rx data reg6/
DSP data
reg14
un16 W
changed
R
RDT7/
ODT15
Rx data reg7/
DSP data
reg15
un16 W
changed
R
Preliminary Data Sheet
6-8
31H
30H
D130
6-59
H
33H
32H
D132
6-59
H
35H
34H
D134
6-59
H
37H
36H
D136
6-59
H
39H
38H
D138
6-59
H
3BH
3AH
D13A
6-59
H
3DH
3CH
D13C 6-59
H
3FH
3EH
D13E
6-59
H
2003-08
DELIC
Register Description
Note: MDT8..15 and ODT8..15 are accessible only in non-DMA mode, when the DMA
Mailbox data registers are used for doubling the size of General Mailbox.
..
Table 6-12
Clock Generator Register Map
Reg Name
Access
Address
Reset
Value
Comment
Page
No.
CPDC
R/W
D080H
0000H
PDC Control
6-62
CPFS
R/W
D081H
0001H
PFS Control
6-62
CLKOUT
R/W
D082H
0008H
CLKOUT Control
6-63
CREFSEL
R/W
D083H
0000H
DCXO Reference Clock
Selection
6-64
CREFCLK
R/W
D084H
0003H
REFCLK Control
6-65
CDCL2
R/W
D085H
0004H
DCL_2000 Control
6-65
CDCL
R/W
D086H
000BH
DCL Control
6-66
CFSC
R/W
D087H
0002H
FSC Control
6-67
CL1CLK
R/W
D088H
0000H
L1_CLK Control
6-68
CPFSSY
R/W
D089H
0000H
PFS Synchronization Mode
6-69
CRTCNT
R
D08EH
0000H
Real-time Counter
6-69
CSTRAP
R/W
D08FH
xxxx
xxxx
xxxx
xx10B
Strap Status Register
6-70
Preliminary Data Sheet
6-9
2003-08
DELIC
Register Description
6.2
Detailed Register Description
6.2.1
TRANSIU Register Description
6.2.1.1
TRANSIU IOM-2000 Configuration Register
TICR Register
read/write
Address: D0A0H
Reset value: 0000H
Note: The reset value of bit 4KFSC is undefined, since this read-only bit is toggled every
250 µs.
DR1..0
DXEN
CMDEN
4KFSC
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
4KFSC
CMDEN
DXEN
DR1
DR0
IOM-2000 Data Rate and Channel Number
00 =
3.072 Mbit/s data rate; 8 IOM-2000 channels are supported
01 =
6.144 Mbit/s data rate; 16 IOM-2000 channels are supported
10 =
12.288 Mbit/s data rate; 24 IOM-2000 channels are supported
11 =
Reserved
DX Line Enable
0=
IOM-2000 DX line to the VIP is in tri-state
1=
IOM-2000 DX line to the VIP is enabled (starting with the next 4 kHz
frame)
CMD Line Enable
0=
IOM-2000 CMD line to the VIP is in tri-state
1=
IOM-2000 CMD line to the VIP is enabled
4 kHz FSC (read only)
0=
In the TRANSIU, the current 8 kHz IOM-2000 frame starts in the
second half of the current 4 kHz Upn of S/T frame
1=
In the TRANSIU, the current 8 kHz IOM-2000 frame starts in the
first half of the current 4 kHz Upn of S/T frame
Preliminary Data Sheet
6-10
2003-08
DELIC
Register Description
Note: ’x’ = unused (read as ’0’)
6.2.1.2
TRANSIU Channel Configuration Registers
The Channel registers are used for IOM-2000 channel disabling and mode
programming. Each IOM-2000 channel may be programmed to Upn, LT-S, or LT-T
mode, or completely disabled.
Important
Only four channels out of eight channels are programmable to Upn and S/T modes in
VIP PEB 20590, the remaining four channels may be operated as Upn transceiver only.
It is the user’s responsiblity to ensure that the IOM-2000 channels in the TRANSIU are
correctly configurated in order to match with the line configuration of the VIP (see below:
Table 6-13
Available ISDN Modes for each VIP Channel
VIP_0,1,2
channel
0
1
2
3
4
5
6
7
TRANSIU
channel
0
8
16
1
9
17
2
10
18
3
11
19
4
12
20
5
13
21
6
14
22
7
15
23
Available
VIP Mode
Upn
Upn
S/T
Upn
Upn
S/T
Upn
Upn
S/T
Upn
Upn
S/T
Available
VIP8 Mode
Upn
S/T
Upn
S/T
Upn
S/T
Upn
S/T
Upn
S/T
Upn
S/T
Upn
S/T
Upn
S/T
Registers TCCR0 - 3
Reset values:
15
Address:
TCCR0: D0A1H
TCCR1: D0A2H
TCCR2: D0A3H
FFFFH
14
C7M(1:0)
7
read/write
6
C3M(1:0)
Preliminary Data Sheet
13
12
C6M(1:0)
5
11
10
C5M(1:0)
4
3
C2M(1:0)
2
C1M(1:0)
6-11
9
8
C4M(1:0)
1
0
C0M(1:0)
2003-08
DELIC
Register Description
C7..0M(1:0)
Operational Mode of IOM-2000 Channel7..0
00 =
Channel is configured to S mode (LT-S)
01 =
Channel is configured to S mode (LT-T)
10 =
Channel is configured to Upn mode
11 =
Channel is disabled, ’0’s are sent on the DX line
Note: TCCR0 (channel 7..0), TCCR1 (channel 15..8) and TCCR2 (channel 23..16) have
the same structure, only TCRR1 is shown here.
6.2.1.3
VIP Command Registers (VIPCMR0, VIPCMR1, VIPCMR2)
The VIPCMR0-2 registers contain command information dedicated to the VIP 0, 1, 2
(only the VIPCMR0 is shown here, VIPCMR1 and VIPCMR2 have the same structure).
VIPCMR Register
write
Address:
VIPCMR0: D0A8H
VIPCMR1: D0A9H
VIPCMR2H: D0AAH
Reset value: 0000H
15
14
13
12
11
x
x
x
x
RD_n
7
6
5
4
3
DELCH(2:0)
WR_n
REFSEL(2:0)
EXREF
10
9
8
PLLPPS SH_FSC DELRE
2
REFSEL (2:0)
1
0
WR_n
Write Command to VIP_n (S/T, UPN)
0=
Data sent to VIP_n is invalid
1=
Data sent to VIP_n is valid
Reference Clock Channel Select (LT-T)
Preliminary Data Sheet
6-12
2003-08
DELIC
Register Description
The reference clock signal for the DELIC oscillator is generated from
the internal VIP_n Channel_m coded in these 3 bits and passed on via
pin REFCLK to the next cascaded VIP or directly to the DELIC
000 =
Reference clock provided by Channel_0
001 =
Reference clock provided by Channel_1
...
007 =
EXREF
DELCH(2:0)
Reference clock provided by Channel_7
External Reference Clock Selection (LT-T)
0=
No external reference clock source. Reference clock is
generated from internal VIP_n channel specified in
REFCLK(2:0) and passed on via REFCLK pin to VIP_n-1 or
directly to DELIC.
1=
Reference clock is generated from external source via pin
INCLK and passed on via REFCLK pin to VIP_n-1 or directly to
DELIC. The internal reference clock generation logic is
disabled.
Note that VIP_0 has the highest priority in terms of clock
selection
Delay Measurement Channel Selection (UPN)
Selects one of the eight Upn line interface channels of each VIP where
the delay is to be measured.
000 =
Delay is measured in Upn Channel_0
001 =
Delay is measured in Upn Channel_1
...
111 =
DELRE
Delay is measured in Upn Channel_7
Delay Counter Resolution (UPN)
Resolution of the delay counter.
0=
Resolution of 65 ns (15.36 MHz period)
1=
Resolution of 130 ns (7.68 MHz period)
Note: Using a resolution of 65 ns, the maximum delay of
20.8 µs is not covered (refer to DELAY(7:0) bits)
SH_FSC
PLLPPS
Short FSC Pulse
0=
The next FSC frame is no superframe
1=
The next FSC is assumed as superframe
PLL Positive Pulse Sensing
Preliminary Data Sheet
6-13
2003-08
DELIC
Register Description
RD_n
0=
Normal operation
1=
The clock recovering PLLs of all VIP channels operate on
positive line pulses only
Read Request to VIP Status Register S_n (S/T, UPN)
0=
No register read
1=
The DSP reads the VIP register (during initialization,
debugging or error conditions). The register value is available
for the read operation in the consecutive frame (after the next
FSC).
Note: To avoid blocking, the DSP must not issue this bit during
normal operation.
Note: Unused bits (x) read as ‘0’. The registers are reset upon every 8 kHz frame sync
to avoid multiple data transmit/receive to/from the VIP.
6.2.1.4
VIP Status Registers
The VIPSTR0-2 registers contain the status bits received from the dedicated VIP for
VIPs 0, 1, 2 respectively (all three registers have the same structure).
VIPSTR Register
read
Address:
VIPSTR0: D0ACH,
VIPSTR1: D0ADH,
VIPSTR2: D0AEH
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
DELAY(7:0)
Preliminary Data Sheet
6-14
2003-08
DELIC
Register Description
DELAY(7:0)
Line Delay Value (UPN)
Returns the value of the measured line delay (in µs) between the Upn
transmit and receive frame with a resolution of 65 ns or 130 ns
(programmable in VIPCMR.DELRE bits).
The value indicates the delay between the transmitted M-bit and the
received LF-bit (minus the UPN guard time of 2 bits). The delay for one
direction equals to the measured delay divided by two.
The channel address for the delay measurement is coded in
VIPCMR.DELCH(2:0) bits.
The VIP provides 2 values in one UPN frame (one every 125 µs) from
which the bigger one is the valid.
Note: The transceiver delays of the VIP are included in the delay
measurement.
Note: Unused bits (x) read as ‘0’.
6.2.1.5
TRANSIU Initialization Channel Command Register
The Initialization Channel Command Register contains the Command bits for VIP_n,
Channel_m together with 5 bits of the VIP channel address.
The VIP only acts upon the command bits if they were declared valid by the DELIC
issuing a write command. Bit WR is dedicated to the command bits of groups CONF1,
CONF2 and TST2, whereas WR_ST informs the VIP about changes in the layer 1 state
machine of the DELIC (SMINI(2:0) and MSYNC bits).
The DELIC may also explicitly read the VIP’s status information by issueing bit RD.
The reset value of each bit is ’0’ except bits MODE(2:0) which are set to ’011’
Note: A read command to the VIP must not be issued during normal operation to avoid
a loss of information when the VIP is reporting status information at the same time.
Preliminary Data Sheet
6-15
2003-08
DELIC
Register Description
TICCMR Register
write
LS-word: D0B0H,
Address:
MS-word: D0B1H
Reset value: 0000H
31
x
30
29
28
VIPADR(1:0)
27
26
CHADR(2:0)
25
24
FIL
EXLP
23
22
21
20
19
18
17
16
PLLS
PD
DHEN
x
x
PDOWN
LOOP
TX_EN
15
14
13
12
11
10
9
8
PLLINT
AAC(1:0)
7
6
MF_EN
WR
5
BBC(1:0)
4
3
MODE(2:0)
OWIN(2:0)
2
MOSEL(1:0)
1
0
RD
WR
Write Command (S/T, UPN)
0=
Data sent in these bits is invalid
1=
All configuration bits contain valid data
Note: Does not apply to SMINI(2:0) and MSYNC bits
RD
MOSEL(1:0)
Read Request to VIP Command Bits (S/T, UPN)
0=
Normal operation
1=
DELIC read request of the TICCMR register which was sent to
the VIP. It includes initialization and configuration commands
and the channel addresses. The VIP returns these values
(instead of sending the actual VIP status information) within
the IOM-2000 STAT_n_m bit stream. The values are available
in the next frame (after next FSC) in DELIC TICSTR register.
Note: To avoid blocking, the DELIC must not issue this bit
during normal operation.
Interface Mode Selection (S/T, UPN)
00 =
Channel programmed to S/T mode
01 =
Channel programmed to UPN mode
10 =
reserved
Preliminary Data Sheet
6-16
2003-08
DELIC
Register Description
11 =
MODE(2:0)
reserved
Mode Configuration (S/T, UPN)
001 =
Channel programmed to LT-T mode
011 =
Channel programmed to LT-S mode (point-to-point
extended passive bus configuration) or UPN mode
111 =
Channel programmed to LT-S mode (short passive bus mode)
or
Note: All other states are reserved. The reset value is 011, e.g.
the default mode of VIP is LT-S
MF_EN
OWIN(2:0)
Multiframe Enable (S/T)
0=
Multiframes are disabled
1=
Multiframes are enabled
Oversampling Window Size (S/T, UPN)
Specifies the width of the oversampling window in bit samples. The
window is centered about the middle of the bit. For example, a size of
16 means that, upon detection of (16/2) = 8 times logical ’1’, the
received bit is detected as ’1’. The window size is programmed in steps
of two as shown below:
BBC(1:0)
AAC(1:0)
000 =
2
001 =
4
010 =
6
...
111 =
16
Balancing Bit Control (UPN)
0x =
Adaptive generation of balancing bit (depending on line delay).
upon reception of INFO3 or INFO4
10 =
Balancing bit control is disabled, and no balancing bit is added
11 =
Balancing bit control is disabled, and balancing bit is added
after each code violation in the M-bit (INFO3 or INFO4)
Adaptive Amplifier Control (S/T, UPN)
0x =
Adaptive amplifier control in VIP is enabled. The amplifier and
the equalizer are switched on/off depending on the level of the
received line signal with respect to the comparator threshold.
10 =
Adaptive amplifier control is disabled. The amplifier and the
equalizer are switched off permanently.
Preliminary Data Sheet
6-17
2003-08
DELIC
Register Description
11 =
PLLINT
TX_EN
LOOP
PDOWN
DHEN
PD
PLLS
EXLP
Adaptive amplifier control is disabled. The amplifier and the
equalizer are switched on permanently
Receive PLL Integrator (UPN)
0=
Programmable deviation disabled
1=
Programmable deviation enabled, i.e., the RxPLL reacts only
after a certain number of consequent deviations from the PLL
controlling range.
Transmitter Enable (S/T, UPN)
0=
Transmitter (analog line driver) is disabled (e.g. for nontransparent analog loops in LT-T)
1=
Transmitter is enabled (e.g. for switching of transparent analog
loops in LT-S)
Loop-back Mode in VIP Enable (S/T, UPN)
0=
Loops disabled
1=
Loop-back enabled. Channel_m transmit data is looped back
to the receive data path (either transparent or non-transparent
according to state of bit TX_EN). Depending on bit EXLP the
loop is closed internally or externally.
Power Down Mode (S/T, UPN)
0=
Operational mode
1=
Channel_m in power-down mode (only the level detector in the
VIP receiver is in operational mode)
D-channel Handling Enable (LT-T)
0=
D-channel transmitted transparently, without any condition
1=
D-channel transmitted transparently if no collision is detected
(E=D), if collision is detected (E ≠ D) ’1s’ are transmitted in Dchannel
Phase Deviation Selection (LT-T)
0=
Phase deviation = (2 bits - 2 oscillator periods + analog delay)
1=
Phase deviation = (2 bits - 4 oscillator periods + analog delay)
Receive PLL Adjustment (S/T, UPN)
0=
tracking step equals 0.5 oscillator period
1=
tracking step equals 1.0 oscillator period
External Loop (S/T, UPN)
Preliminary Data Sheet
6-18
2003-08
DELIC
Register Description
FIL
CHADR(2:0)
VIPADR(2:0)
0=
No external analog loop. If bit LOOP=1 the loop is closed
internally
1=
External analog loop. If bit LOOP=1 the loop is closed
externally
Filter Enable (UPN only)
0=
Filter of equalizer inside the VIP receiver disabled
1=
Filter of equalizer inside the VIP receiver enabled
Channel_m Address for Commands
000 =
Command word is dedicated to VIP_n Channel_0
001 =
Command word is dedicated to VIP_n Channel_1
010 =
Command word is dedicated to VIP_n Channel_2
011 =
Command word is dedicated to VIP_n Channel_3
100 =
Command word is dedicated to VIP_n Channel_4
101 =
Command word is dedicated to VIP_n Channel_5
110 =
Command word is dedicated to VIP_n Channel_6
111 =
Command word is dedicated to VIP_n Channel_7
VIP_n Address for Commands
00 =
Command word is dedicated to VIP_0
01 =
Command word is dedicated to VIP_1
10 =
Command word is dedicated to VIP_2
11 =
Reserved
Note: Unused bits (x) read as ‘0’.
Preliminary Data Sheet
6-19
2003-08
DELIC
Register Description
6.2.1.6
TRANSIU Initialization Channel Status Register (TICSTR)
The Initialization Channel Status Register contains the Command bits to VIP_n,
Channel_m mirrored by the VIP in response to a read command issued by the DELIC in
the previous frame.
Note: The actual Status information from the VIP channels is stored in the data RAM to
make it accessible for the DELIC layer-1 state machine software in the DSP.
TICSTR Register
read
Address:
LS-word: D0B2H, MS-word: D0B3H
Reset value: 0000H
31
x
30
29
28
VIPADR(1:0)
27
26
CHADR(2:0)
25
24
FIL
EXLP
23
22
21
20
19
18
17
16
PLLS
PD
DHEN
x
x
PDOWN
LOOP
TX_EN
15
14
13
12
11
10
9
8
PLLINT
7
AAC(1:0)
6
MF_EN
Preliminary Data Sheet
5
BBC(1:0)
4
3
MODE(2:0)
OWIN(2:0)
2
MOSEL(1:0)
6-20
1
0
RD
WR
2003-08
DELIC
Register Description
6.2.1.7
Scrambler Mode Register
SCMOD Register
read/write
Address: D010H
Reset value: 0003H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
SCMOD1..0
SCMOD1..0 Scrambling Mode of the Upn Line Interface
00 = Scrambling according to ITU-T V.27
01 = Scrambling compatible to OCTAT-P PEB 2096
10 = Reserved
11 = No scrambling
6.2.1.8
Scrambler Status Register
SCSTA Register
read/write
Address: D011H
Reset value: undefined
SCSTA
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
SCSTA
Scrambler Status
0=
Write access: start of scrambling algorithm for all channels enabled
in the HRAM
read access: scrambler is processing data
Preliminary Data Sheet
6-21
2003-08
DELIC
Register Description
1=
Write access: start of scrambling algorithm for all channels enabled
in the HRAM
read access: scrambling has finished
Note: Both values ’0’ or ’1’ written to SCSTA will start the scrambling
6.2.2
IOMU Register Description
6.2.2.1
IOMU Control Register
ICR Register
read/write
Address: D040H
Reset value: 02H
ICDB
A
OD
DC
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
ICDB
A
OD
DC
DR(1:0)
Idle Current D-Buffer ( for test purpose; only if IOMU is in idle mode: ICR:A
= ’0’)
0=
Make frame buffer 0 accessible to the DSP
1=
Make frame buffer 1 accessible to the DSP
IOMU Activation
0=
The IOMU is Idle. The state machine of the IOMU is idle, and no
accesses to the I-buffer are executed by the IOMU.
1=
The IOMU is active, and works according to the programming of the
other Control Register bits.
DD0 and DD1 Output Mode
0=
Push-Pull mode.
1=
Open-Drain mode
Double Data Rate Clock
0=
Single clock (DCL frequency is identical to the IOM-2 data rate)
Preliminary Data Sheet
6-22
2003-08
DELIC
Register Description
1=
DR(1:0)
Double clock (DCL frequency is double the IOM-2 data rate)
IOM-2 Data Rate
6.2.2.2
00 =
IOM-2 data rate of 1 x 384 kbit/s (1 x 6 time slots/frame)
01 =
IOM-2 data rate of 1 x 768 kbit/s (1 x 12 time slots/frame)
10 =
IOM-2 data rate of 2 x 2.048 Mbit/s (2 x 32 time slots/frame)
(default)
11 =
IOM-2 data rate of 1 x 4.096 Mbit/s (1 x 64 time slots/frame)
IOMU Status Register
ISR Register
read/write
Address: D041H
Reset value: undefined
IBUFF
15
14
13
12
11
10
9
8
IBUFF
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
I-Buffer Index
Note: Used for testing. May also be used in double data rate mode of the
IOMU to determine if the IOMU buffers have been swapped already
0=
Buffer 0 is currently used as I-buffer, buffer 1 is used as D-buffer
1=
Buffer 1 is currently used as I-buffer, buffer 0 is used as D-buffer
Note: (x) unused bits read as ’0’
Preliminary Data Sheet
6-23
2003-08
DELIC
Register Description
6.2.2.3
IOMU Tri-State Control Register
ITSCR Register
read/write
Address:
Set Address: D042H
Reset Address: D043H
Read Address: D044H
Reset Value: 00H
15
14
13
12
11
10
9
8
2
1
0
TS(15:8)
7
6
5
4
3
TS(7:0)
TS(15:0)
Every bit determines whether DD0/1 output is in tri-state during the time slot
sequence. The time slot sequence length, indices and port controlled by
each TS-bit is defined according the IOMU data rate mode (ICR.DR(1:0))
0=
DD0/1 is in tri-state during the related time slot sequence
1=
DD0/1 is driven by the IOMU during the related time slot sequence
Table 6-14
ITSCR
Bit
Tristate Control Assignment for IOM-2 Time Slots
1 x 6 TS/frame
DD0
TS
1 x 12 TS/frame
DD0
TS
2 x 32 TS/frame
1 x 64 TS/frame
DD0/1
DD0/1
TS
TS
TS0
DD0
0
DD0
0
DD0
0-3
DD0
0-3
TS1
DD0
1
DD0
1
DD0
4-7
DD0
4-7
TS2
DD0
2
DD0
2
DD0
8-11
DD0
8-11
TS3
DD0
3
DD0
3
DD0
12-15
DD0
12-15
TS4
DD0
4
DD0
4
DD0
16-19
DD0
16-19
TS5
DD0
5
DD0
5
DD0
20-23
DD0
20-23
TS6
not used
DD0
6
DD0
24-27
DD0
24-27
TS7
not used
DD0
7
DD0
28-31
DD0
28-31
TS8
not used
DD0
8
DD1
0-3
DD0
32-35
Preliminary Data Sheet
6-24
2003-08
DELIC
Register Description
Table 6-14
ITSCR
Bit
Tristate Control Assignment for IOM-2 Time Slots (Continued)
1 x 6 TS/frame
DD0
TS
1 x 12 TS/frame
DD0
TS
2 x 32 TS/frame
1 x 64 TS/frame
DD0/1
DD0/1
TS
TS
TS9
not used
DD0
9
DD1
4-7
DD0
36-39
TS10
not used
DD0
10
DD1
8-11
DD0
40-43
TS11
not used
DD0
11
DD1
12-15
DD0
44-47
TS12
not used
not used
DD1
16-19
DD0
48-51
TS13
not used
not used
DD1
20-23
DD0
52-55
TS14
not used
not used
DD1
24-27
DD0
56-59
TS15
not used
not used
DD1
28-31
DD0
60-63
6.2.2.4
IOMU DRDY Register
IDRDYR Register
Reset value: undefined
read
Address: D045H
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
DS(7:0)
bit
DRDY Sample
DSx indicates the availability of the D-channels of the previous frame.
0 = STOP (D-channel blocked due to collision), 1 = GO
e.g. DS1 was sampled during the D-channel of IOM-2 channel 1, etc.
DS0
corresponds to D-channel of IOM-2 port 0 cha 0
DS1
corresponds to D-channel of IOM-2 port 0 cha 1
DS2
corresponds to D-channel of IOM-2 port 0 cha 2
DS3
corresponds to D-channel of IOM-2 port 0 cha 3
DS4
corresponds to D-channel of IOM-2 port 0 cha 4
DS5
corresponds to D-channel of IOM-2 port 0 cha 5
DS6
corresponds to D-channel of IOM-2 port 0 cha 6
DS7
corresponds to D-channel of IOM-2 port 0 cha 7
Preliminary Data Sheet
6-25
2003-08
DELIC
Register Description
Note: In 1 x 4.096 Mbit/s mode (i.e.16 IOM-2 channels/frame), DRDY is sampled only
during the D-channels of the first eight IOM-2 channels of every frame.
6.2.2.5
IOMU Data Prefix Register
IDPR Register
Reset value: E0H
15
read/write
14
13
12
11
Address: D046H
10
9
8
IDP(7:0)
IDP(7:0)
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
IOMU Data Prefix
Determines the high byte of every word being read from the IOM circularbuffer (I-buffer or D-buffer). The low byte is the data being read from the
circular buffer.
After reset this register contains the MSB of the base address of the A-lawto-linear ROM table: E0H.
Note: (x) unused bits read as ’0’
Preliminary Data Sheet
6-26
2003-08
DELIC
Register Description
6.2.3
PCMU Register Description
6.2.3.1
PCMU Command Register
PCR Register
read/write
Address: D060H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
SFH
ICDB
PA
PDCL
PDR(1:0)
PDR(1:0) PCM Data Rate
PDCL
PA
ICDB
SFH
00 =
4 x 2.048 Mbit/s (4 x 32 time slots per frame)
01 =
2 x 4.096 Mbit/s (2 x 64 time slots per frame)
10 =
1 x 8.092 Mbit/s (1 x 128 time slots per frame)
11 =
1 x 16.384 Mbit/s (1 x 256 time slots per frame, if only first or
second half of 8 kHz frame is handled)
PCM Double Data Rate Clock
0=
Single Data Rate Clock
1=
Double Data Rate Clock
PCMU Activation
0=
The PCMU is in idle mode
1=
The PCMU is in active mode
Idle Current D-Buffer
Used only for testing of PCMU in IDLE mode (PCR:PA = '0') to determine
which buffer is being accessed by the DSP
0=
Frame buffer 0 is accessed by the DSP
1=
Frame buffer 1 is accessed by the DSP
Second Frame Half
Used only in 1 x 256 time slots per frame data rate mode
0=
The first 128 time slots of each frame are handled by the PCMU
Preliminary Data Sheet
6-27
2003-08
DELIC
Register Description
1=
The second 128 time slots of each frame are handled by the PCMU
Note: ’x’ = unused (read as ’0’)
6.2.3.2
PCMU Status Register
PSR Register
read/write
Address: D061H
Reset value: undefined
15
14
13
12
11
10
9
8
PBUFF
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
PBUFF
P-Buffer Index
Note: Used for testing. May also be used in double data rate mode of the
PCMU to determine if the PCMU buffers have been swapped already
0=
Buffer 0 is currently used as P-buffer, buffer 1 is used as D-buffer
1=
Buffer 1 is currently used as P-buffer, buffer 0 is used as D-buffer
Note: (x) unused bits read as ’0’
Preliminary Data Sheet
6-28
2003-08
DELIC
Register Description
6.2.3.3
PCMU Tri-state Control Registers
PTSC0 Register
read/write
(set/reset)
read Address: D062-63H
set Address: D062H
reset Address: D063H
PTSC1 Register
read/write
(set/reset)
read Address: D064-65H
set Address: D064H
reset Address: D065H
PTSC2 Register
read/write
(set/reset)
read Address: D066-67H
set Address: D066H
reset Address: D067H
PTSC3 Register
read/write
(set/reset)
read Address: D068-69H
set Address: D068H
reset Address: D069H
PTSC4 Register
read/write
(set/reset)
read Address: D06A-6BH
set Address: D06AH
reset Address: D06BH
PTSC5 Register
read/write
(set/reset)
read Address: D06C-6DH
set Address: D06CH
reset Address: D06DH
PTSC6 Register
read/write
(set/reset)
read Address: D06E-6FH
set Address: D06EH
reset Address: D06FH
PTSC7 Register
read/write
(set/reset)
read Address: D070-71H
set Address: D070H
reset Address: D071H
Reset values (PTSC0..7): 0000H
15
14
13
12
11
10
9
8
PTSCn(15:8)
Preliminary Data Sheet
6-29
2003-08
DELIC
Register Description
7
6
5
4
3
2
1
0
PTSCn(7:0)
PTSCn
(15..0)
Tristate Control for each PCM Time Slot
6.2.3.4
0=
The controlled time slot is invalid
1=
The controlled time slot is valid
PCMU Data Prefix Register
PDPR Register
Reset value: E0H
15
read/write
14
13
12
11
Address: D072H
10
9
8
PDP(7:0)
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
PDP(7:0) PCMU Data Prefix
The data written to this register is read as the most significant byte of every
time slot read by the DSP from the PCMU frame buffers. Can be used for
quick access to the a/µ-law ROM, for conversion of compressed data
(received via the PCM interface) into linear value.
After reset this register contains the MSB of the base address of the a-lawto-linear ROM table: E0H. To enable quick conversion from µ-law to linear,
the PCMU Data Prefix Register should be programmed to E1H.
Note: (x) unused bits read as ’0’
Preliminary Data Sheet
6-30
2003-08
DELIC
Register Description
6.2.4
A-/µ-law Unit Register Description
6.2.4.1
A/µ-law Unit Control Register
A/µ-law Unit Control Register (AMCR) read/write
Address:
D020H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
MODE
Note: ’x’ = unused bits
This register controls the conversion mode of the A/µ-law unit
MODE
A/µ-law Mode Programming
6.2.4.2
0=
Conversion from linear value to A-law value (default)
1=
Conversion from linear value to µ-law value
A/µ-law Input Register
A/µ-law Unit Input Register (AMIR)
write
Address:
D021H
Reset value: undefined
15
14
13
12
11
10
9
8
2
1
0
IND(15:8)
7
6
5
4
3
IND(7:0)
Note: - In µ-law mode, only the 14 MSBs are processed.
- In A-law mode, only the 13 MSBs are processed.
IND(15:0)
Linear Input Data
Preliminary Data Sheet
6-31
2003-08
DELIC
Register Description
Provides the linear input data that is to be converted into logarithmic
data format according to A-law or µ-law algorithm.
6.2.4.3
A/µ-law Output Register
A/µ-law Unit Output Register (AMOR) read
Address:
D022H
Reset value: undefined
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
OUTD(7:0)
Note: ’x’ = unused bits, driven to ’0’
OUTD(7:0)
Logarithmic Output Data
Provides the logarithmic output data generated by the A/-µ-law unit out
of the linear input data. The data format (A-law or µ-law) depends on the
the selected conversion algorithm.
Preliminary Data Sheet
6-32
2003-08
DELIC
Register Description
6.2.5
HDLCU Registers Description
6.2.5.1
HDLCU Control Register
In order to enable DSP access all the buffers and RAMS, DSPCTRL bit must be set to ‘1’.
HCR Register
write
Address:
D180H
Reset value: 0001H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
HPRS(5:0)
HPRS(5:0)
DSPCTRL
HDLCU Channel Preset
The number of HDLC channels to be processed by the HDLCU
DSPCTRL
DSP Access Control to the HDLCU
0=
The DSP must not access the HDLCU buffers and RAMs
1=
The DSP may access the HDLCU buffers
Note: Each time DSPCTRL is set, HPRS is also set.
Preliminary Data Sheet
6-33
2003-08
DELIC
Register Description
6.2.5.2
HDLCU Status Register
HSTA Register
read
Address:
D180H
9
8
1
0
Reset value: 0001H
15
14
13
HHOLD
BITOR
x
7
6
5
CHCNT(0)
DSPCTRL
HPRS(5:0)
12
11
10
CHCNT(5:1)
4
3
2
HPRS(5:0)
DSPCTRL
DSP Access Control to the HDLCU
0=
The HDLCU is currently processing the channel
1=
The DSP is currently accessing the HDLCU
HDLC Channel Preset
Number of HDLC channels handled by the HDLCU (max. 32)
CHCNT(5:0)
Channel Count
Number of channels that have already been processed in the
current frame
BITOR
Bitorder
Determines the order of bits inside an HDLC data byte going to (coming
from) the IOMU, PCMU or TRANSIU.
HHOLD
0=
HDLC data is transmitted with MSB first
1=
HDLC data is transmitted with LSB first
HDLCU Busy Indicator
0=
HDLCU is processing the current frame
1=
HDLCU has finished processing the current frame
Preliminary Data Sheet
6-34
2003-08
DELIC
Register Description
6.2.5.3
Channel Command Vector
HCCV Registers
read/ write
Addresses:
4040H - 405FH
Each of the 32 HDLC channels has a 7-bit command vector that resides in the
corresponding address of the command RAM. The structure of a command vector is as
follows:
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
DBSEL
RECRES
CRC
IDLE
TXCMD(2:0)
Note: Accesses to these registers are possible only if register bit HCR:DSPCTRL = 1
’x’ = unused
DBSEL
RECRES
TXCMD(2:0)
D- or B-Channel Select
0=
Indication for a B-channel. HDLC protocol is performed on all 8
data bits
1=
Indication for a D-channel. HDLC protocol is performed only on
the 2 MSB data bit in the Receive Input Buffer and Transmit
Output Buffer
Receiver Reset
0=
Normal operation
1=
Reset the HDLC receiver
Transmit Command
000=
End transmition
001=
Start transmission at the first bit of the D-channel
010=
Start transmission at the second bit of the D-channel
011=
Start transmitting a flag (beginning with the fifth bit of the flag,
since ’0111’ is automatically inserted)
100=
Abort transmission
Note: other combinations are reserved
CRC
CRC Enable
0=
Preliminary Data Sheet
CRC checking algorithm off
6-35
2003-08
DELIC
Register Description
1=
IDLE
CRC checking algorithm on
IDLE Mode
0=
Transmit ’ones’ over an idle channel - the unshared flag mode
1=
Transmit ’flags’ over an idle channel - the shared flag mode
Note: In the receive direction, the only function of the command vector is to indicate
whether the channel is a D-channel or a B-channel, and whether to use CRC
decoding or not.
The main function of the command vector is to control the flow of time slots in the
transmit direction.
6.2.5.4
Channel Status Vector
HCSV Registers
read
Addresses:
40A0H - 40BFH
Reading a channel from the Receive Output Buffer and Writing to a channel in the
Transmit Input Buffer is done according to the channel’s status vector in the Transmit
Output Buffer. This vector contains 7 flags:
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
FLAG
EMPTY
FULL
ABORT
STOP
CRC
NO
Note: Accesses to these registers are possible only if register bit HCR:DSPCTRL = 1
’x’ = not used
NO
CRC
STOP
Not Octet
0=
Normal operation
1=
The last bits of a message have not filled an octet (8 bits)
CRC Error
0=
No CRC error in received message
1=
CRC error was detected in the received message
Stop Indication
0=
Preliminary Data Sheet
Normal operation
6-36
2003-08
DELIC
Register Description
1=
ABORT
FULL
EMPTY
HDLCU has detected an end of message flag in the receive
direction. The DSP must read the octet in the Receive Output
Buffer before the next message start flag is detected
Abort Indication
0=
Normal operation
1=
The DSP has detected an incoming abort message (7
consecutive ’1s’). The STOP flag is also set to 1. This means
that the DSP should ignore the current message being
transmitted over the channel in question and report to the
external microcontoller
Receive Buffer Full Indication
0=
Normal operation
1=
Indicates that the Receive Output Buffer has a newly processed
octet in it. The DSP must read this octet before starting the next
processing session, otherwise it might be lost.
Transmit Buffer Empty
0=
The transmit buffer is full.
1=
The transmit buffer is empty. The current time slot in the
Transmit Input Buffer has been fully processed by the HDLCU.
The Transmit Input buffer is ready to receive the next octet of
the message by the DSP.
Note: The DSP must put a new octet into the buffer before
starting the next processing session, otherwise the same
octet will be read again.
FLAG
Status Vector Flag
0=
Ignore the status vector and do not read or write on this channel
1=
Read the channel’s status vector and process accordingly
Note: FLAG will go to ‘1’ as soon as EMPTY or FULL go to ‘1’.
Preliminary Data Sheet
6-37
2003-08
DELIC
Register Description
6.2.6
GHDLC Register Description
6.2.6.1
GHDLC Test/ Normal Mode Register
GTEST Register
write
Address: D0C0H
Reset value: 0001H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
TEST
CHMOD1..0
Channel Mode
0=
Normal operation mode
1=
Test mode
Note: As GTEST has a reset value of 01H this register has to set to 0 to enable the
GHDLCU
6.2.6.2
GHDLC Channel Mode Register
GCHM Register
write
Address: D0C1H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
CHMOD1..0
CHMOD(1..0)
Channel Mode
00 =
Preliminary Data Sheet
Channel 0 used up to 16.384 MHz
6-38
2003-08
DELIC
Register Description
6.2.6.3
01 =
2 channels (ch 0+3) used up to 8.192 MHz
10 =
4 channels (ch 0..3) used up to 4.096 MHz
11 =
Reserved
GHDLC Interrupt Register
GINT Register
read
Address: D0D4H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
INT3
INT2
INT1
INT0
INTn bits
Interrupt Indication for GHDLC Channel n (= 0..3)
6.2.6.4
0=
Normal operation
1=
GHDLC interrupt has occurred
GHDLC FSC Interrupt Control Register
GFINT Register
read
Address: D0D3H
Reset value: 0000H
FINTn
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
FINT3
FINT2
FINT1
FINT0
FSC Interrupt Control GHDLC Channel n (= 0..3)
Preliminary Data Sheet
6-39
2003-08
DELIC
Register Description
6.2.6.5
0=
FSC rising edge causes a receiver interrupt only if a full interrupt
has not occurred during the previous frame
1=
FSC rising edge causes a receiver interrupt regardless whether
or not a full interrupt occurred during the previous frame
GHDLC Receive Channel Status Registers 0..3
GRSTA Register 0
GRSTA Register 1
GRSTA Register 2
GRSTA Register 3
read
read
read
read
Address:
Address:
Address:
Address:
D0C2H
D0C3H
D0C4H
D0C5H
Reset value: 001FH
15
14
13
12
11
10
9
8
x
x
x
x
x
x
COLLD
UNDER
7
6
5
4
3
2
1
0
EMPTY
OVER
FULL
RBFILL(4:0)
RBFILL(4:0) Receive Buffer Fill
Indicates to the DSP the currently available number of bytes - 1 in the
receive buffer
FULL
OVER
EMPTY
Receive Buffer Full
0=
No receive buffer full indication
1=
Receive buffer block of the GHDLC is full. The blocks have been
switched.
Buffer Overrun
0=
No buffer overrun indication
1=
Two consecutive full interrupts were received without a GHDLC
access to the status register in between, i.e. a buffer was missed.
Transmit Buffer Empty
0=
No transmit buffer empty indication
1=
The transmit buffer block currently being transmitted over the
GHDLC channel has been emptied
Preliminary Data Sheet
6-40
2003-08
DELIC
Register Description
UNDER
Buffer Underrun
COLLD
0=
No buffer underrun indication
1=
A buffer containing an uncomplete message has been emptied
without a continuation of the message in the other buffer
Collision Detected
0=
No collision detection indication
1=
Collision detected during transmission. The message needs to be
re-sent.
Note: Only relevant in HDLC-Mode, if one device does not
operate conform to the HDLC protocol definition
Note: Reading the register GRSTA resets its bits to the default value.
6.2.6.6
GHDLC Receive Data and Status
To each data byte in the receive buffer 4 flag bits are appended
RXDAT Registers
.
read
Address:
2000H -203FH
15
14
13
12
11
10
9
8
ABORT
END
CRC
NO
x
x
x
x
7
6
5
4
3
2
1
0
RDAT7..0
NO
CRC
Not Octet
0=
Received message is a multiple of eight bits
1=
Received message is not a multiple of eight bits
CRC Error Flag
0=
Received byte contains no CRC error flag.
1=
Received byte contains a CRC error flag.
A CRC error was detected in the received frame.
END
END Flag
0=
Received byte contains no END flag
1=
Received byte contains an END flag
Preliminary Data Sheet
6-41
2003-08
DELIC
Register Description
ABORT
ABORT Flag
RD7..0
0=
Received byte contains no ABORT flag
1=
Received byte contains an ABORT flag
Received data byte
6.2.6.7
GHDLC Mode Registers
GMOD Register 0
GMOD Register 1
GMOD Register 2
GMOD Register 3
write
write
write
write
Address:
Address:
Address:
Address:
D0C6H
D0C7H
D0C8H
D0C9H
Reset value: 0140H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
EDGE
TE
7
6
5
4
3
2
1
0
CLASS
COLLD
PPOD
IFTF
OPMOD(1:0)
CRCMOD(1:0)
CRCMOD(1:0) CRC Mode
00 =
CRC algorithm disabled
01 =
16-bit CRC algorithm (X16+X12+X5+1)
10 =
32-bit CRC algorithm
(X31+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X1+1)
11 =
reserved
OPMOD(1:0) Operational Mode
Programs the mode of the GHDLC channel
IFTF
00 =
HDLC mode
01 =
reserved
10 =
Asynchronous mode (enables accesses to register GASYNC)
11 =
reserved
Interframe Time Fill
0=
Preliminary Data Sheet
Sequence of ’1s’ is used as interframe time fill characters
6-42
2003-08
DELIC
Register Description
1=
PPOD
Flags (7EH) are used as interframe time fill characters
Push-Pull / Open-Drain Configuration
COLLD
0=
Open-drain
1=
Push-pull
Collision Detection
CLASS
0=
Collision detection disabled
1=
Arbitration between several GHDLC on a bus is done using
collision detection
Priority Class Assignment
TE
0=
Channel has priority class 8
1=
Channel has priority class 10
Transmit Enable
EDGE
0=
Transmit line is only enabled during the transmission of a
message including opening and closing flags
1=
Transmit line is always enabled
Edge Programming for Receive Data Sampling
6.2.6.8
0=
Receiver samples data on rising edge of the line clock
1=
Receiver samples data on falling edge of the line clock
GHDLC Channel Transmit Command Registers
GTCMD Register 0
GTCMD Register 1
GTCMD Register 2
GTCMD Register 3
write
write
write
write
Address:
Address:
Address:
Address:
D0CAH
D0CCH
D0CEH
D0D0H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
STOP
TXCMD
Preliminary Data Sheet
TBFILL(4:0)
6-43
2003-08
DELIC
Register Description
TBFILL(4:0)
Transmit Buffer Fill
Indicates to the GHDLC unit the currently available number of bytes - 1
in the transmit buffer.
TXCMD
Transmission Command
0=
Transmission is not started
1=
Start transmission
Stop Command
STOP
6.2.6.9
0=
Message continues in the next buffer
1=
End of the message is in this buffer
ASYNC Control Register
GASYNC Register
read/ write
Address: D0D2H
Reset value: 0000
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
IOPORT(7..0)
Accesses to register GASYNC:
IOPORT Writing a "1" to the bit position
bits
sets the port pin below
Reading from the bit position indicates the
current state of the port pin below
bit 0
LTXD0
LRXD0
bit 1
LTXD1
LRXD1
bit 2
LTXD2
LRXD2
bit 3
LTXD3
LRXD3
bit 4
LRTS0
LCTS0
bit 5
LRTS1
LCTS1
bit 6
LRTS2
LCTS2
bit 7
LRTS3
LCTS3
Accesses to the different bits of this register are only possible in ASYNC mode of the
corresponding GHDLC channel (See “GHDLC Mode Registers” on page 42.).
Preliminary Data Sheet
6-44
2003-08
DELIC
Register Description
Note: GHDLC channels 3..1 are only accessible, if respective bits in register MUXCTRL
are set.
6.2.6.10 LCLK0 Control Register
LCLK0 Control Register (GLCLK0)
read/write
Address: D08AH
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
LCLK0EN
LCLK0(1:0)
Note: ’x’ = unused bits, read as 0.
LCLK0EN
LCLK0 Output Enable
0=
LCLK0 is input (default)
1=
LCLK0 is driven outward via LCLK0 pin
LCLK0(1:0) LCLK0 Output Clock Rate
Note: This option is valid only when LCLK0 is output. When LCLK0 is
input the frequency is determined externally.
00 =
2.048 MHz (default)
01 =
4.096 MHz
10 =
8.192 MHz
11 =
16.384 MHz
Preliminary Data Sheet
6-45
2003-08
DELIC
Register Description
6.2.6.11 LCLK1 Control Register
LCLK1 Control Register (GLCLK1)
read/write
Address: D08BH
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
LCLK1EN
LCLK1(1:0)
Note: ’x’ = unused bits, read as 0.
LCLK1EN
LCLK1 Output Enable
0=
LCLK1 is input (default)
1=
LCLK1 is driven outward via LCLK1 pin
LCLK1(1:0) LCLK1 Output Clock Rate
Note: This option is valid only when LCLK1 is output. When LCLK1 is
input the frequency is determined externally.
00 =
2.048 MHz (default)
01 =
4.096 MHz
10 =
8.192 MHz
11 =
16.384 MHz
Preliminary Data Sheet
6-46
2003-08
DELIC
Register Description
6.2.6.12 LCLK2 Control Register
LCLK2 Control Register (GLCLK2)
read/write
Address: D08CH
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
LCLK2EN
LCLK2(1:0)
Note: ’x’ = unused bits, read as 0.
LCLK2EN
LCLK2 Output Enable
0=
LCLK2 is input (default)
1=
LCLK2 is driven outward via LCLK2 pin
LCLK2(1:0) LCLK2 Output Clock Rate
Note: This option is valid only when LCLK2 is output. When LCLK2 is
input the frequency is determined externally.
00 =
2.048 MHz (default)
01 =
4.096 MHz
10 =
8.192 MHz
11 =
16.384 MHz
Preliminary Data Sheet
6-47
2003-08
DELIC
Register Description
6.2.6.13 LCLK3 Control Register
LCLK3 Control Register (GLCLK3)
read/write
Address: D08DH
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
LCLK3EN
LCLK3(1:0)
Note: ’x’ = unused bits, read as 0.
LCLK3EN
LCLK3 Output Enable
0=
LCLK3 is input (default)
1=
LCLK3 is driven outward via LCLK3 pin
LCLK3(1:0) LCLK3 Output Clock Rate
Note: This option is valid only when LCLK3 is output. When LCLK3 is
input the frequency is determined externally.
00 =
2.048 MHz (default)
01 =
4.096 MHz
10 =
8.192 MHz
11 =
16.384 MHz
Preliminary Data Sheet
6-48
2003-08
DELIC
Register Description
6.2.6.14 Muxes Control Register
MUXCTRL Register
OAK: read/write
Address: D14AH
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
PMUX1
PMUX0
IMUX
IMUX
0=
IOM-2000 pins are used for the IOM-2000 interface
1=
IOM-2000 pins are used for the GHDLC cha. 1
0=
PCM ports 0 & 2 pins are used for PCM
1=
PCM ports 0 & 2 pins are used for GHDLC cha. 2
0=
PCM ports 1 & 3 pins are used for PCM
1=
PCM ports 1 & 3 pins are used for GHDLC cha. 3
PMUX0
PMUX1
Preliminary Data Sheet
6-49
2003-08
DELIC
Register Description
6.2.7
DCU Register Description
6.2.7.1
Interrupt Mask Register
IMASK Register
read/write
Address:
D002H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
IMASK
IMASK
GHDLC Interrupt Mask
0=
GHDLC interrupt disabled
1=
GHDLC interrupt enabled
Note: The unused bits (x) are read as ‘0’.
6.2.7.2
Status Event Register
STEVE Register
read
Address:
D003H
Reset value: 0000H
PFS
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
PFS
FSC
FP
PFS Status Bit
0=
normal operation
1=
PFS rising edge has occurred (reset by DSP read access)
Preliminary Data Sheet
6-50
2003-08
DELIC
Register Description
FSC
FSC Status Bit
FP
0=
normal operation
1=
FSC rising edge has occurred (reset by DSP read access)
FSC & PFS Status Bit
0=
normal operation
1=
Both FSC and PFS rising edges have occurred, i.e. bits PFS and
FSC are set (reset by DSP read access)
Note: Unused bits (’x’) are read as ‘0’.
6.2.7.3
Statistics Counter Register
STATC Register
read/write
Address:
D004H
Reset value: unchanged
Reset value: unchanged upon chip reset, but reset upon FSC detection if STATC was
read by the DSP since last occurence of FSC.
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
STATC(7:0)
STATC
(7:0)
Statistics Counter Value
Note: The unused bits (x) are read as ‘0’.
Preliminary Data Sheet
6-51
2003-08
DELIC
Register Description
6.2.7.4
Statistics Register
STATI Register
read/write
Address:
D005H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
MSC(7:0)
MSC(7:0) Max. Statistics Count
Note: The unused bits (x) are read as ‘0’.
6.2.8
µP Configuration Registers
6.2.8.1
µP Interface Configuration Register
MCFG Register
DSP: read
µP: read/write
DSP Address: D148H
µP high address: none
µP low address: 48H
Reset value: 00H
DMA
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
MODE
7
6
5
4
3
2
1
0
DRQLV
IRQLV
IRQMO
IMASK
IACK
PEC
FB
DMA
DMA Mode Enabled
0=
No DMA
Preliminary Data Sheet
6-52
2003-08
DELIC
Register Description
1=
FB
PEC
IACK
IMASK
IRQMO
IRQLV
DRQLV
MODE
DMA enabled
Fly-by Mode
0=
Memory-to-memory mode used for DMA transfers
1=
Fly-by mode used for DMA transfers
PEC Transfers Enable
0=
No PEC Transfers
1=
PEC transfers are supported (for connection of C16x µP)
Interrupt Acknowledge Mode
0=
Interrupt vector is provided to CPU after 1st IACK pulse.
1=
Interrupt vector is provided to CPU after 2nd IACK pulse.
Interrupt Mask
0=
IREQ pin is disabled
1=
IREQ pin is enabled
IREQ Pin Mode
0=
Open-drain mode
1=
Push-pull mode
IREQ Pin Level
0=
Low active
1=
High active
DREQR/DREQT Pins Level
0=
High active
1=
Low active
µP Interface Mode
Contains the value of MODE input pin sampled by rising edge of RESET
Note: This signal is hardwired.
0=
Intel/Siemens mode
1=
Motorola mode
Preliminary Data Sheet
6-53
2003-08
DELIC
Register Description
6.2.8.2
Device Version Register
VDEV Register
µP: read
µP address: 6AH
Reset value: none (hardwired)
7
6
5
4
3
2
1
0
VDEV(7:0)
VDEV
Device Version
Contains the information about the device status.
6.2.8.3
1H
DELIC Version 1.1
2H
DELIC Version 2.1
Interrupt Vector Register
IVEC Register
DSP: read/ write
µP: read
DSP Address: D168H
µP high address: none
µP low address: 68H
4
2
Reset value: unchanged
7
6
5
3
1
0
IVEC(7:0)
IVEC7..0
Interrupt vector
Contains the interrupt vector address that is output during an INTA cycle of
the µP
Preliminary Data Sheet
6-54
2003-08
DELIC
Register Description
6.2.9
µP Mailbox Registers Description
6.2.9.1
µP Command Register
MCMD Register
DSP: read
µP: write
DSP address: D140H
µP address: 40H
4
2
Reset value: 00H
7
6
5
3
1
0
MCMD
MCMD
µP Command
Contains the µP command (8-bit opcode) to the DELIC.
6.2.9.2
µP Mailbox Busy Register
MBUSY Register
DSP: write
µP: read
DSP Address: D141H
µP high address: 41H
µP low address: none
Reset value: 00H
15
14
13
12
11
10
9
8
MBUSY
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
MBUSY
µP Mailbox Busy Bit
0=
Mailbox is available for the external µP. The µP may write a
command to MCMD.
Preliminary Data Sheet
6-55
2003-08
DELIC
Register Description
1=
Mailbox is blocked for the external µP. The µP may not write a
command to MCMD.
Note: MBUSY is automatically set each time a command is written
to MCMD by the µP.
MBUSY is reset automatically by a direct OAK write
operation to the MBUSY register.
6.2.9.3
µP Mailbox Generic Data Register
MGEN Register
DSP: read
µP: write
DSP Address: D144H
DSP high: D143H
DSP low: D142H
µP high: 43H
µP low: 42H
Reset value: unchanged
15
14
13
12
11
10
9
8
2
1
0
MGEN(15..8)
7
6
5
4
3
MGEN(7..0)
MGEN
(15..0)
µP Mailbox Generic Data (16 bits)
Preliminary Data Sheet
6-56
2003-08
DELIC
Register Description
6.2.9.4
µP Mailbox (General and DMA Mailbox) Data Registers
MDTn Register (n=0..7)
TDTn/ MDTn+8 Register (n=0..7)
DSP: read
µP: write
Addr. see table on page 6-6
Reset value: unchanged
15
14
13
12
11
10
9
8
2
1
0
MDTn(15..8)
7
6
5
4
3
MDTn(7..0)
MDTn
(15..0)
µP Mailbox Data (each byte is addressed seperately by the external µP)
Note: The 16 data registers (MDT1..7, TDT0/MDT8..TDT7/MDT15) have the same
structure. The addresses are displayed in the register map (page 6-6, page 6-7).
6.2.9.5
DSP Command Register
OCMD Register
DSP: write
µP: read
DSP address: D160H
µP address: 60H
4
2
Reset value: 00H
7
6
5
3
1
0
OCMD
OCMD
DSP Command
Contains the DSP command/ indication (8-bit opcode) to the
DELIC.
Preliminary Data Sheet
6-57
2003-08
DELIC
Register Description
6.2.9.6
DSP Mailbox Busy Register
OBUSY Register
DSP: read
µP: read/ write
DSP Address: D161H
µP high address: 61H
µP low address: none
Reset value: 00H
15
14
13
12
11
10
9
8
OBUSY
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
OBUSY
DSP Mailbox Busy Bit
0=
Mailbox is available for the DSP. The DSP may write a command/
indicationto OCMD.
1=
Mailbox is blocked for the DSP. The DSP may not write a
command/ indication to OCMD.
Note: OBUSY is automatically set each time a command/
indication is written to OCMD by the DSP.
OBUSY is reset automatically by a direct µP write operation
to the OBUSY register
Preliminary Data Sheet
6-58
2003-08
DELIC
Register Description
6.2.9.7
DSP Mailbox Generic Data Register
OGEN Register
DSP: write
µP: read
DSP address: D164H
DSP high: D163H
DSP low: D162H
µP high: 63H
µP low: 62H
Reset value: unchanged
15
14
13
12
11
10
9
8
2
1
0
OGEN(15..8)
7
6
5
4
3
OGEN(7..0)
OGEN
15..0
DSP Mailbox Generic Data (16 bits)
6.2.9.8
DSP Mailbox (General and DMA Mailbox) Data Registers
ODTn Register (n= 0..15)
RDTn/ ODTn+8 Register (n=0..7)
DSP: write
µP: read
Addr. see table on page 6-7
Reset value: unchanged
15
14
13
12
11
10
9
8
2
1
0
ODTn(15..8)
7
6
5
4
3
ODTn(7..0)
(
ODTn
(15..0)
DSP Mailbox Data (each byte is addressed seperately by the external µP)
Note: The 16 data registers (ODT1..7, RDT0/ODT8..RDT7/ODT15) have the same
structure. The addresses are displayed in the register map (page 6-6, page 6-7).
Preliminary Data Sheet
6-59
2003-08
DELIC
Register Description
6.2.10
DMA Mailbox Registers Description
6.2.10.1 DMA Mailbox Transmit Counter Register
DTXCNT Register
DSP: read/write
Address: D150H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
TXCNT(3:0)
Note: Writing to TXCNT initiates a DMA transfer of TXCNT bytes to the DMA Tx Mailbox.
This register value does not change during the current transfer.
6.2.10.2 DMA Mailbox Receive Counter Register
DRXCNT Register
DSP: read/write
Address: D170H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
RXCNT(3:0)
Note: Writing to RXCNT initiates a DMA transfer of RXCNT bytes to the DMA Rx
Mailbox. This register value does not change during the current transfer.
Preliminary Data Sheet
6-60
2003-08
DELIC
Register Description
6.2.10.3 DMA Mailbox Interrupt Status Register
DINSTA Register
DSP: read
Address: D152H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
INSTA(3:0)
Contains the status of the DMA Mailbox.
Preliminary Data Sheet
6-61
2003-08
DELIC
Register Description
6.2.11
Clock Generator Register Description
6.2.11.1 PDC Control Register
PDC Control Register (CPDC)
read/write
Address:
D080H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
PDC(1:0)
Note: ’x’ = unused bits, read as 0.
PDC(1:0) PDC Frequency Selection (Only in Master Mode when PDC is output)
00 =
PDC = 2.048 MHz (default)
01 =
PDC = 4.096 MHz
10 =
PDC = 8.192 MHz
11 =
PDC = 16.384 MHz
6.2.11.2 PFS Control Register
PFS Control Register (CPFS)
read/write
Address:
D081H
Reset value: 0001H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
PFS
Note: ’x’ = unused bits, read as 0.
PFS
PFS Frequency Selection
(Selectable in Slave mode when PFS is input; in Master mode PFS = 8 kHz)
0=
PFS = 4 kHz
Preliminary Data Sheet
6-62
2003-08
DELIC
Register Description
1=
PFS = 8 kHz (default)
Note: When the PFS is output, its frequency is always 8 kHz, therefore this bit should be
left in its reset-value ('1') and not to be changed.
The direction of PFS and PDC: input (slave) or output (master) is determined by
the Master/Slave strap (DREQR pin) during reset.
6.2.11.3 CLKOUT Control Register
CLKOUT Control Register (CLKOUT) read/write
Address:
D082H
Reset value: 0008H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
CLKOUTEN
CLKOUT
Note: ’x’ = unused bits, read as 0.
CLKOUTEN CLKOUT Pin Enable
CLKOUT
0=
CLKOUT pin is in tri-state.
1=
CLKOUT pin is active. (default)
CLKOUT Pin Frequency
000 =
2.048 MHz (default)
001 =
4.096 MHz
010 =
8.192 MHz
011 =
15.36 MHz
100 =
16.384 MHz
Preliminary Data Sheet
6-63
2003-08
DELIC
Register Description
6.2.11.4 DCXO Reference Clock Select Register
REFSEL Register (CREFSEL)
read/write
Address:
D083H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
REFSEL
EN
REFSEL(2:0)
Note: ’x’ = unused bits, read as 0
This register controls the selection of the source of the DCXO 8kHz reference clock
REFSELEN
DCXO Reference Clock Enable
0=
The reference clock is disabled (default)
1=
The reference clock is enabled
REFSEL(2:0) DCXO Reference Clock Select
000 =
DXCLK/192 (default)
001 =
XCLK/256
010 =
XCLK
011 =
REFCLK (when input)
100 =
REFCLK (when input)/64
101 =
PFS (when input)
Preliminary Data Sheet
6-64
2003-08
DELIC
Register Description
6.2.11.5 REFCLK Control Register
REFCLK Control Register (CREFCLK) read/write
Address:
D084H
Reset value: 0003H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
REFCLKEN
REFDIV(2:0)
Note: ’x’ = unused bits, read as 0.
REFCLK may be configured as an input or as an output. When configured as an input,
it may be used as a source for the on-chip DCXO 8kHz reference clock. This option is
handled by the DCXO Reference Clock Select Register (CREFSEL).
When configured as an output it is derived from XCLK input pin. In order to drive
REFCLK, XCLK may be divided by 256, 192, 4, 3 or 1.
REFCLKEN
REFCLK Pin Output Enable
0=
REFCLK is input, the pad is not output enabled
1=
REFCLK is output
REFDIV(2:0) REFCLK Pin Output Divider Selection
This determines the value by which the XCLK maximum clock of 2.048
MHz is divided internally.
000 =
Division by 256
001 =
Division by 192
010 =
Division by 4
011 =
Division by 3 (default)
100 =
Division by 1
Preliminary Data Sheet
6-65
2003-08
DELIC
Register Description
6.2.11.6 DCL_2000 Control Register
DCL_2000 Control Register (CDCL2) read/write
Address:
D085H
Reset value: 0004H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
DCL2EN
DCL2(1:0)
Note: ’x’ = unused bits, read as 0.
DLC2EN
DCL_2000 Clock Enable
0=
DCL_2000 clock is disabled
1=
DCL_2000 clock is enabled (default)
DCL2(1:0) DCL_2000 Clock Rate
00 =
3.072 MHz (default)
01 =
6.144 MHz
10 =
12.288 MHz
6.2.11.7 DCL Control Register
DCL Control Register (CDCL)
read/write
Address:
D086H
Reset value: 000BH
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
DCLEN
DCL(2:0)
Note: ’x’ = unused bits, read as 0.
DCLEN
DCL Clock Enable
0=
DCL is disabled
Preliminary Data Sheet
6-66
2003-08
DELIC
Register Description
1=
DCL is enabled (default)
DCL(2:0) DCL Clock Rate
000 =
384 kHz
001 =
768 kHz
010 =
1536 kHz
011 =
2048 kHz (default)
100 =
4096 kHz
6.2.11.8 FSC Control Register
FSC Control Register (CFSC)
read/write
Address:
D087H
Reset value: 0002H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
IFSCD
EFSC
FSCEN
FSCSH
Note: ’x’ = unused bits, read as 0.
FSCEN
FSCSH
EFSCD
IFSCD
FSC Clock Enable
0=
FSC is disabled (stuck at '0')
1=
FSC is enabled (default)
Short FSC Pulse
0=
The next FSC pulse will be longer than 2 DCL cycles (default)
1=
The next FSC pulse will be shorter than 2 DCL cycles (short FSC)
External FSC Delay
0=
no delay between FSC and DCL rising edge
1=
FSC rising edge is delayed by one CLK61 clock (16 ns) relative to
DCL/ DCL2000
Internal FSC Delay (only valid of CSTRAP: bit0 = 1)
0=
no delay between FSC and DCL rising edge
Preliminary Data Sheet
6-67
2003-08
DELIC
Register Description
1=
FSC rising edge is delayed by one CLK61 clock (16 ns) relative to
DCL/ DCL2000
Note: If only one short FSC pulse is needed, this bit should be reset to '0' by the DELIC
software, after the next FSC rising edge detection (after the begining of the next
frame). It is not executed automatically by the hardware.
6.2.11.9 L1_CLK Control Register
L1_CLK Control Register (CL1CLK)
read/write
Address:
D088H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
x
x
L1CLKDIS
L1CLK
Note: ’x’ = unused bits, read as 0.
L1CLKEN L1_CLK Disable
L1CLK
0=
L1_CLK is enabled (default)
1=
L1_CLK is disabled
L1_CLK Clock Rate
0=
7.68 MHz (default)
1=
15.36 MHz
Preliminary Data Sheet
6-68
2003-08
DELIC
Register Description
6.2.11.10 PFS Sync Register
PFS Sync Register (CPFSSY)
read/write
Address:
D089H
Reset value: 0000H
15
14
13
12
11
10
9
8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
x
x
x
x
PFSSYNC(1:0)
Note: ’x’ = unused bits, read as 0.
During read cycle the 2 LSBs are driven by the the PFS-sync state-machine's state bits.
This is needed only for testing.
The PFS-sync Signal actually resets the 61.44 MHz-Clock-division-Chain. The PFSsync signal activated with the PFS-rising edge detection, but only when the internal-reset
is activated or after a "PFS-sync" instruction was carried out by the OAK. The goal of
reseting the 61.44MHz-Clock-division-Chain by PFS-sync, is to lead to a situation in
which FSC rises with PFS. After the initial reset by the PFS-sync a small- and flexible
phase difference is maintained by the DCXO-PLL. A write access to PFS-Sync Register,
resets the 61MHz clock-division chain, including FSC, by the next PFS rising-edge
detection. This is true only if the write access was carried-out before the falling edge of
PFS. If the write-access comes after the falling edge of PFS, the acctuall sync operation
will not be carried out by the next PFS rising-edge, but with one that will come after it.
The written value does not make any difference.
6.2.11.11 Realtime Counter Register
RT Counter Register (CRTCNT)
read
Address: D08EH
Reset value: 0000H
15
14
13
12
11
10
9
8
2
1
0
RTCOUNT(15:8)
7
6
5
4
3
RTCOUNT(7:0)
This 18-bit counter counts 8 kHz cycles. It is used by the software to time the handling
of required tasks. One period of the counter (counting from 0000H to FFFFH and back
Preliminary Data Sheet
6-69
2003-08
DELIC
Register Description
to 0000H) is 32.768 sec. Only the 16 MSBs of the counter may be read by the OAK,
therefore the actuall resolution is 0.5 ms. .
RTCOUNT(15:0)
The 16 MSBs of the realtime counter
6.2.11.12 Strap Status Register
Strap Status Register (CSTRAP)
read/ write
Address: D08FH
Reset value: xxxx xxxx xxxx xx10B
15
14
13
12
11
x
x
x
x
x
7
6
5
4
3
10
9
8
STRAP(10:8)
2
1
0
STRAP(7:0)
Note: ’x’ = unused bits, read as 0.
STRAP
(10:0)
This register enables the OAK to read the straps values, as sampled
during reset
bit 10
PCM Clock Master Strap
bit 9:7
Test Mode Strap
bit 6
Emulation Boot Strap
bit 5
PLL Bypass Strap
bit 4
DSP PLL Power-Down Strap
bit 3
Boot Strap
bit 2
Reset counter Bypass Strap
bit 1
DCXO Fast-Synchronization Enable
0=
1=
bit 0
Internal Source Clock Strap
0=
1=
Preliminary Data Sheet
Linear (slow) synchronization (for DECT applications)
Fast synchronization (default)
PFS, PDC, DCL, FSC, DCL2000 are delayed by some
ns (default)
PFS, PDC, DCL, FSC, DCL2000 are not delayed
6-70
2003-08
DELIC
Package Outlines
7
Package Outlines
GPM05247
P-TQFP-100-1
(Plastic Thin Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Preliminary Data Sheet
7-1
Dimensions in mm
2003-08
DELIC
PEB 20571
Electrical Characteristics
8
Electrical Characteristics
8.1
Absolute Maximum Ratings
Parameter
Symbol
Storage temperature
Tstg
VDD
VI
VO
– 65 to 150
°C
– 0.3 to 4.6
V
– 0.3 to 6.0
V
– 0.3 to VDD + 0.3
V
DC output voltage (including I/Os);
output in tri-state
VI, VO
– 0.3 to 6.0
V
ESD robustness1)
HBM: 1.5 kΩ, 100 pF
VESD,HBM
1000
V
IC supply voltage
DC input voltage (except I/Os)
DC output voltage (including I/Os);
output in high or low state
1)
Limit Values
Unit
According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
The Pins (TBD) are not protected against voltage stress > (TDB) V (versus VS or GND). The (TBD)
performance prohibits the use of adequate protective structures.
Note:
Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible
damage to the integrated circuit.
8.2
Operating Range
Parameter
Symbol
Limit Values
min.
VDD
VSS
VIN
Power Supply Voltage
Ground
Voltage applied to input pins
Voltage applied to output or I/O pins
outputs enabled
outputs high-Z
Operating temperature
Input transition rise or fall time
PEB
PEF
Unit
max.
3.13
3.47 V
0
0 V
0
5.5 V
0
0
VDD V
VOUT
VOUT
TA
TA
0
-40
∆t/∆v
0
5.5 V
70 ° C
85 ° C
10 ns/V
Note: In the operating range, the functions given in the circuit description are performed.
Preliminary Data Sheet
8-1
2003-08
DELIC
PEB 20571
Electrical Characteristics
8.3
DC Characteristics
Parameter
Symbol
VIH
Low-Level Input Voltage
VIL
High-Level Output voltage VOH
High-Level Input Voltage
Limit Values
Unit Test Condition
min.
max.
2.0
VDD + 0.3 V
VOUT >= VOH (min)
– 0.3
0.8
V
VOUT <= VOL (max)
V
VDD = min,
IOH = – 2 mA
V
VDD = min,
IOL = 2 mA
V
VDD = min,
IOH = – 7 mA
0.4
V
VDD = min,
IOL = 7 mA
1
µA
VDD = 3.3 V,
2.4
(all pins except DD0, DD1,
DX, LTxD0, TxD0, TxD1)
Low-Level Output voltage VOL
(all pins except DD0, DD1,
DX, LTxD0, TxD0, TxD1)
High-Level Output voltage VOH
(pins DD0, DD1, DX,
LTxD0, TxD0, TxD1)
0.4
2.4
Low-Level Output voltage VOL
(pins DD0, DD1, DX,
LTxD0, TxD0, TxD1)
Input leakage current
IIL
GND = 0 V; all
other pins are
floating; VIN = 0 V
Output leakage current
IOZ
1
µA
VDD = 3.3 V,
GND = 0 V;
VOUT = 0 V
Avg. power
supply current
ICC (AV)
TBD
mA
VDD = 3.3 V,
TA = 25 ° C:
PDC = 8 MHz
DSP @ 61.44 MHz
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 ° C and
the given supply voltage.
Preliminary Data Sheet
8-2
2003-08
DELIC
PEB 20571
Electrical Characteristics
8.4
Capacitances
Parameter
Symbol
Limit Values
min.
Input Capacitance
I/O Capacitance
Output Capacitance
Crystal input capacitance
(pin CLK16-XI)
CIN
CI/O
COUT
CXIN
max.
7
7
pF
pF
10
pF
3.3 (TBD) pF
Crystal output capacitance CXOUT
(pin CLK16-XO)
8.5
Unit Notes
fC = 1 MHz,
The pins, which
are not under test,
are connected to
GND
3.3 (TBD) pF
Recommended 16.384 MHz Crystal Parameters
Parameter
Symbol
Limit Values
min.
Unit Test Condition
max.
C1
Shunt Capacitance
C0
External Load Capacitance CL
Resonance Resistance
Rr
25
fF
7
pF
≤15
pF
≤30
Ω
Frequency Calibration
Tolerance
≤150
ppm
Motional Capacitance
Preliminary Data Sheet
8-3
2003-08
DELIC
Timing Diagrams
9
Timing Diagrams
9.1
General
For TTL and CMOS voltage levels refer to the relevant JEDEC specifications, e.g. to
JEDEC8-A for 3V/3.3V devices which are 5V compatible.
Note: The complete AC characteristics will be provided after the electrical
characterization of the device.
All timing shown are preliminary.
9.2
µP Access Timing
µP accesses of the DELIC are performed by an activation of the address and CS.
• By driving the MODE pin ‘high’ the user selects Motorola mode, by driving it ‘low’ Intel/Infineon mode. The pin is sampled during the rising edge of RESET.
• In Intel/Infineon mode, a distinction is needed between working in multiplexed
address/data bus mode and de-multiplexed address and data bus mode. In Motorola
Mode, only de-multiplexed buses are used. The selection between multiplexed and
de-multiplexed bus configurations is done by using the ALE pin.
9.2.1
µP Access Timing in Motorola mode
In this mode R/W distinguishes between Read and Write interactions, and DS is used for
timing.
Preliminary Data Sheet
9-1
2003-08
DELIC
Timing Diagrams
Table 9-1
Timing For Write Cycle In Motorola Mode
Parameter
Symbol
Limit Values
min.
Unit
Test
Condition
Output load
capacity of
50 pF
max.
R/W setup time before DS x CS rising tSRWS
edge
15
ns
R/W hold time after DS x CS rising
edge
tHRWS
5
ns
A-bus setup time before DS x CS
rising edge
tSAS
15
ns
A-bus hold time after DS x CS rising
edge
tHAS
5
ns
D-bus setup time before DS x CS
rising edge
tSDS
12
ns
D-bus hold time after DS x CS rising
edge
tHDS
10
ns
DS X CS pulse width
tWS
15
ns
Note: DS X CS is active (low) when both, DS and CS, are active (low)
tSRWS
tHRWS
tSAS
tHAS
R/W
A
tSDS
tHDS
D
tWS
DS x CS
Figure 9-1
Write Cycle in Motorola Mode
Preliminary Data Sheet
9-2
2003-08
DELIC
Timing Diagrams
Table 9-2
Timing For Read Cycle In Motorola Mode
Parameter
Symbol
Limit Values
min.
Unit
Test
Condition
Output load
capacity of
50 pF
max.
R/W setup time before DS X CS
falling edge
tSRWS
0
ns
R/W hold time after DS X CS rising
edge
tHRWS
5
ns
A-bus valid to D-bus valid
tDAD
0
20
ns
DS X CS falling edge to D-bus
tDSD
0
20
ns
0
15
ns
D-bus float after DS X CS rising edge tDSDH
Note: DS X CS is active (low) when both, DS and CS are active (low)
A
tSRWS
tHSRW
R/W
DSxCS
tDAD
tDSD
tDSDH
D
Figure 9-2
9.2.2
Read Cycle in Motorola Mode
µP Access Timing in Intel/Infineon Mode
In this mode driving RD ‘low’ causes a read access, driving WR ‘low’ causes a write
access.
Timing for Demultiplexed Bus
In de-multiplexed bus configuration, ALE must be driven ‘high’.
Preliminary Data Sheet
9-3
2003-08
DELIC
Timing Diagrams
Table 9-3
Timing For Write Cycle In Intel/Infineon Demultiplexed Mode
Parameter
Symbol
Limit Values
Unit
Test
Condition
12
ns
A-bus hold time after WR rising edge tHAW
5
ns
Output load
capacity of
50 pF
CS setup time before WR rising edge tSCW
12
ns
CS hold time after WR rising edge
tHCW
5
ns
D-bus setup time before WR rising
edge
tSDW
12
ns
D-bus hold time after WR rising edge tHDW
10
ns
WR pulse width
15
ns
min.
A-bus setup time before WR rising
edge
tSAW
tWW
max.
tWW
tSCW
tSAW
tSDW
tHCW
tHAW
tHDW
WR
A
CS
D
Figure 9-3
Write Cycle in Intel/Infineon De-multiplexed Mode
Preliminary Data Sheet
9-4
2003-08
DELIC
Timing Diagrams
Table 9-4
Timing For Read Cycle In Intel/Infineon De-multiplexed Mode
Parameter
Symbol
Limit Values
min.
max.
Unit
Test
Condition
Output load
capacity of
50 pF
A-bus valid to D-bus valid
tDAD
0
20
ns
RD X CS falling edge to D-bus
tDRD
0
20
ns
0
15
ns
D-bus float after RD X CS rising edge tDRDH
Note: RD X CS is active (low) when both RD and CS are active (low)
A
RDxCS
tDAD
tDRD
tDRDH
D
Figure 9-4
Read Cycle in Intel/Infineon De-multiplexed Mode
Preliminary Data Sheet
9-5
2003-08
DELIC
Timing Diagrams
Timing for Multiplexed Bus
In this mode the ALE pin is used to lock the address send via the multiplexed A/D bus.
Table 9-5
Timing For Write Cycle In Intel/Infineon Multiplexed Mode
Parameter
Symbol
Limit Values
Unit
Test
Condition
12
ns
A-bus hold time after ALE falling edge tHAL
5
ns
Output load
capacity of
50 pF
ALE pulse width
10
ns
CS setup time before WR rising edge tSCW
12
ns
CS hold time after WR rising edge
tHCW
5
ns
D-bus setup time before WR rising
edge
tSDW
12
ns
D-bus hold time after WR rising edge tHDW
10
ns
ALE hold time after WR rising edge
tHLW
5
ns
WR pulse width
tWW
15
ns
min.
A-bus setup time before ALE falling
edge
tSAL
tWL
max.
tWW
WR
tSCW
tHCW
tSDW
tHDW
CS
tSAL
tHAL
Address
AD
Data
tWL
tHLW
ALE
Figure 9-5
Write Cycle in Intel/Infineon Multiplexed Mode
Preliminary Data Sheet
9-6
2003-08
DELIC
Timing Diagrams
Table 9-6
Timing For Read Cycle In Intel/Infineon Multiplexed Mode
Parameter
Symbol
Limit Values
min.
Unit
Test
Condition
Output load
capacity of
50 pF
max.
ALE low before RD X CS falling edge tHRL
5
ns
ALE hold time after RD X CS rising
edge
tHLR
5
ns
ALE pulse width
tWL
10
ns
A-bus setup time before ALE falling
edge
tSAL
12
ns
A-bus hold time after ALE falling edge tHAL
5
ns
RD X CS falling edge to D-bus valid
0
20
ns
0
15
ns
tDRD
D-bus float after RD X CS rising edge tDRDH
tHRL
RDxCS
tWL
tHLR
ALE
tHAL
tSAL
Address
AD
Figure 9-6
9.3
tDRD
tDRDH
Data
Read Cycle in Intel/Infineon Multiplexed Mode
Interrupt Acknowledge Cycle Timing
The IREQ (Interrupt REQuest) output signal of the DELIC is activated upon a DSP write
operation to the OCMD register (OAK Mailbox command register). This operation sets
the OAK Mailbox busy bit (OBUSY), which drives directly the IREQ output signal. The
IREQ signal may be masked, by programming the MASK bit within the µP interface
Control Register (UPCR).
The microprocessor may force the DELIC to drive the interrupt vector over the data bus
by activation of the interrupt acknowledge input signal (IACK).
Preliminary Data Sheet
9-7
2003-08
DELIC
Timing Diagrams
In Motorola mode, an interrupt acknowledge cycle consists of one IACK pulse, during
which the interrupt vector is issued by the DELIC. In Intel/Infineon mode, an interrupt
acknowledge cycle consists of two IACK pulses. Note that the interrupt vector is issued
as a response to the second pulse. The source of the vector is the OAK Mailbox interupt
vector register (IVEC). The DSP determines the value stored in this register by a write
operation.
IREQ is not deactivated by the IACK pulses directly, but by a µP write access to OBUSY.
Table 9-7
Interrupt Acknowledge Cycle Timing
Parameter
Symbol
Limit Values
min.
max.
Unit
Test
Condition
Output load
capacity of
50 pF
D-bus valid after IACK falling edge
tDADV
0
20
ns
D-bus float after IACK rising edge
tDADT
0
15
ns
IACK pulse width
tWA
25
ns
Interval between two ACK pulses
tHA
101)
ns
1)
Valid only for Intel/Infineon mode.
IACK
tDADT
tDADV
vector
D
Figure 9-7
Interrupt Acknowledge Cycle Timing in Motorola Mode
tWA
tHA
tWA
IACK
tDADT
tDADV
D
Figure 9-8
vector
Interrupt Acknowledge Cycle Timing in Intel/Infineon Mode
Preliminary Data Sheet
9-8
2003-08
DELIC
Timing Diagrams
DSxCS
WR
tDWI
IREQ
Figure 9-9
IREQ Deactivation Timing
Note: IREQ is deactivated due to µP write operation to OBUSY register. In Motorola
mode DS and CS together time the write access. In Intel mode WR alone times
the write access. For more details regarding the timing required during write
access to the DELIC, refer to section 9.2. The other signals required for a write
operation to OBUSY in each mode, are assumed to be driven.
9.4
DMA Access Timing
The exact behavior required from the µP interface signals during a DMA access depends
on the following modes:
• Motorola or Intel Mode: Determined by the MODE input pin.
• Normal or ’fly-by’ Mode: Programmable in the control register of the µP interface.
In any mode, the DACK input is used to indicate that this is a DMA transaction, and to
select the DMA Mailbox. An activation via the CS signal is not required in such cases.
9.4.1
DMA Access Timing In Motorola Mode
In this mode DS is used for timing the access, while R/W is used to distinguish between
DMA read transactions and DMA write transactions. The R/W input signal is used
differently in normal mode and in fly-by mode. The next table shows how R/W should be
used in each mode during DMA transactions:
Table 9-8
R/W Behavior During DMA Transactions in Normal and Fly-By Mode
Mode
R/W = ‘0’
R/W = ‘1’
Normal (Non-Fly-By)
Write DMA transaction.
(A response to DMA
transmitter request)
Read DMA transaction.
(A response to DMA receiver
request)
Fly-By
Read DMA transaction.
(A response to DMA
receiver request)
Write DMA transaction.
(A response to DMA transmitter
request)
Preliminary Data Sheet
9-9
2003-08
DELIC
Timing Diagrams
In fly-by mode R/W is used inverted to the normal mode, since the same signal, R/W, is
required for concurrent accesses of an external memory device.
Table 9-9
DMA Transaction timing in Mototrola Mode
Parameter
Symbol
Limit Values
min.
Unit
Test
Conditions
Output load
capacity of
50 pF
max.
DACK setup time to DS
falling edge
tSAS
7
ns
DACK hold time after DS
rising edge
tHSA
5
ns
D-bus setup time to DS rising tSDS
edge
5
ns
ns
D-bus hold time after DS
rising edge
tHSD
10
DREQT/DREQR delay after
DS falling edge
tDSR
0
36
ns
R/W setup time to DS falling tSRWS
edge
7
ns
R/W hold time after DS rising tHSRW
edge
5
ns
ns
DS pulse width and interval
between DS pulses
tWS
30
D-bus valid after DS falling
edge
tDSDV
0
22
D-bus float (high impedance) tDSDT
after DS rising edge
0
15
Preliminary Data Sheet
9-10
2003-08
DELIC
Timing Diagrams
tWS
tSRWS
tSAS
tWS
tSDS
tHSA
DS
DACK
tHSRW
R/W
tHSD
D
last byte
tDSR
DREQT
Figure 9-10 DMA Write Transaction Timing in Motorola Mode
Note: R/W is shown for normal mode. In Fly-by mode, R/W should be high during DMA
write transactions.
Preliminary Data Sheet
9-11
2003-08
DELIC
Timing Diagrams
tWS
tWS
tSRWS
tSAS
tHSA
DS
DACK
tHSRW
R/W
tDSDT
tDSDV
D
last byte
tDSR
DREQR
Figure 9-11 DMA Read-Transaction Timing in Motorola Mode
Note: R/W is shown for normal mode. In Fly-by mode, R/W should be low during DMA
read transactions.
9.4.2
DMA Access Timing in Intel/Infineon Mode
In this mode, R and W are used for timing the access and to determine whether a DMA
read cycle or DMA write cycle has occured. R and W input signals are used in opposite
ways in normal mode and in fly-by mode.
The next table shows how R and W should be used in each mode during DMA
transactions:
Preliminary Data Sheet
9-12
2003-08
DELIC
Timing Diagrams
Table 9-10
R/W Behavior During DMA Transactions in Normal and Fly-By Mode
Mode
R = ‘1’, W = ‘0’
R = ‘0’, W = ‘1’
Normal (Non-Fly-By)
Write DMA transaction.
(A response to DMA
transmitter request)
Read DMA transaction.
(A response to DMA receiver
request)
Fly-By
Read DMA transaction.
(A response to DMA
receiver request)
Write DMA transaction.
(A response to DMA transmitter
request)
In Fly-By mode R and W are used inverted to the normal mode, because these signals
are required also for concurrent accesses of an external memory device.
Table 9-11
DMA Transaction Timing in Intel/Infineon Mode
Parameter
Symbol
Limit Values Unit
min.
max.
DACK setup time to W or R falling
edge
tSAW tSAR
7
ns
DACK hold time after W or R rising
edge
tHWA
tHRA
5
ns
D-bus setup time to W rising edge
tSDW
5
ns
D-bus hold time after W rising edge
tHWD
10
ns
DREQT/DREQR delay after W or R
falling edge
tDWR
tDRR
0
36
30
ns
R pulse width and interval between R
pulses
tWR
30
ns
D-bus valid after R falling edge
tDRDV
0
22
D-bus float (high impedance) after R
rising edge
tDRDT
0
15
9-13
Output load
capacity of
50 pF
ns
W pulse width and interval between W tWW
pulses
Preliminary Data Sheet
Test
Conditions
2003-08
DELIC
Timing Diagrams
tWW
tWW
tSDW
tSAW
tHWA
WR(RD)
DACK
tHWD
D
last byte
tDWR
DREQT
Figure 9-12 DMA Write Transaction Timing in Intel/Infineon Mode
Note: The figure shows a transaction in normal mode. In Fly-by mode, RD is used during
DMA write transactions, instead of WR
tWR
tSAR
tWR
tHRA
RD(WR)
DACK
tDRDT
tDRDV
D
last byte
tDRR
DREQR
Figure 9-13 DMA Read Transaction Timing in Intel/Infineon Mode
Note: The figure shows a transaction in normal mode. In Fly-by mode, WR is used during
DMA read-transactions, instead of RD.
Preliminary Data Sheet
9-14
2003-08
DELIC
Timing Diagrams
9.5
IOM®-2 Interface Timing
Figure 9-14 IOM®-2 Interface Timing with Single Data Rate DCL
Table 9-12
Timing Characteristics of the IOM®-2
Parameter
Symbol
Limit Values
min.
Frame sync. hold
Frame sync. setup
Frame sync. high
Frame sync. low
Data delay to clock
Data delay to frame1)
Data setup
Data hold
tFH
tFS
tFWH
tFWL
tDDC
tDDF
tDS
tDH
typ.
Unit
Conditions
max.
30
ns
70
ns
130
ns
tDCL
100
ns
150
ns
20
ns
50
ns
Note: 1) tDDF = 0.5 tDCL + tDDC – tFH
Preliminary Data Sheet
9-15
2003-08
DELIC
Timing Diagrams
Figure 9-15 Timing of the IOM®-2 Interface with Double Data Rate DCL
Table 9-13
Timing Characteristics of the IOM®-2
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
30
ns
70
ns
130
ns
Data delay to frame1)
tFH
tFS
tFWH
tFWL
tDDC
tDDF
Data setup
tDS
20
ns
Data hold
tDH
50
ns
Frame sync hold
Frame sync setup
Frame sync high
Frame sync low
Data delay to clock
Conditions
tDCL
100
ns
150
ns
Note: 1) tDDF = 0.5 tDCL + tDDC – tFH
Preliminary Data Sheet
9-16
2003-08
DELIC
Application Hints
10
Application Hints
10.1
DELIC Connection to External Microprocessors
ALE
CSn
WR
CS
WR
RD
RD
IREQ
INTR
DRQ0
DREQR
DRQ1
DREQT
DACK0
DACK
DACK1
A(5..1)
A0
A(5..1)
D(7..0)
AD(7..0)
BLE
80386EX
DELPHI
Vcc 2.7V-3.6V,25MHz
80386EX.vsd
Figure 10-1 DELIC Connection to Intel 80386EX (Demuxed Configuration)
Preliminary Data Sheet
10-1
2003-08
DELIC
Application Hints
DMA Controller
HOLD
HOLD
8237
8237
HLDA
HLDA
DRQ0
DRQ1
DACK0
DACK1
DREQR
DREQT
DACK
ALE
CSn
CS
WR
WR
RD
RD
IREQ
INTn
A(5..0)
A(5..0)
AD(7..0)
D(7..0)
Infineon C165
DELIC
Vcc 5V, 20MHz
C165.vsd
Figure 10-2 DELIC Connection to Siemens C165 (Demuxed Configuration)
Preliminary Data Sheet
10-2
2003-08
Preliminary Data Sheet
10-3
15
0
00:
01:
10:
11:
DC
0:
1:
OD
0:
1:
A
0:
1:
ICDB 0:
1:
SFH 0:
1:
DR
4 x 2.048 Mbit/s
2 x 4.096 Mbit/s
1 x 8.192 Mbit/s
1 x 16.384 Mbit/s
single clock
double clock
push pull mode
open drain mode
PCMU is idle
PCMU is active
frame buffer 0 accessed by the DSP
frame buffer 1 accessed by the DSP
the first 128 time-slots are used
the second 128 time-slots are used
Address: 0xd070 set and read
0xd071 reset and read
Address: 0xd06e set and read
0xd06f reset and read
15
PTSCR7
0
PTSCR6
15
Address: 0xd06c set and read
0xd06d reset and read
Address: 0xd06a set and read
0xd06b reset and read
15
PTSCR5
0
PTSCR4
15
Address: 0xd068 set and read
0xd069 reset and read
15
PTSCR3
Address: 0xd066 set and read
0xd067 reset and read
0
PTSCR2
15
Address: 0xd064 set and read
0xd065 reset and read
Address: 0xd062 set and read
0xd063 reset and read
15
OUT 3
OUT 2
OUT 1
OUT 0
IN 3
IN 2
IN 1
IN 0
PTSCR1
0
0xA0FF
0xA0DF
0xA0E0
0xA0BF
0xA0C0
0xA09F
0xA0A0
0xA07F
0xA080
0xA05F
0xA060
0xA03F
0xA040
0xA01F
0xA020
0xA000
PCMU Data Buffer
PTSCR0
15
0
0 0 0 0 0 0 0 0
0
0
0
0
TSC3
TSC2
TSC1
TSC0
TxD3
TxD2
TxD1
TxD0
RxD3
RxD2
RxD1
RxD0
10.2
Address: 0xd060
PCR
DSP
15
Address: 0xd072
PDPR
DELIC
Application Hints
DELIC Worksheets
Figure 10-3 DELIC-LC PCM unit mode 0 ( 4 ports with 2 MBit/s)
2003-08
µP
MBUSY
(µP <- DSP)
Preliminary Data Sheet
10-4
MDT5
MDT6
MDT7
0x0D
0x0C
0x0F
0x0E
MDT12
MDT13
MDT14
MDT15
0x19
0x18
0x1B
0x1A
0x1D
0x1C
0x1F
0x1E
0xD11E
0xD11C
0xD11A
0xD118
0xD116
MDT11
0xD112
0xD114
MDT9
0x13
0x12
0xD110
MDT10
MDT8
0x11
0x10
0x15
0x14
0x17
0x16
0xD10E
0xD10C
0xD10A
0xD108
µP Expanded Mailbox
MDT4
0x0B
0x0A
0xD106
0x09
0x08
MDT3
0xD102
0xD104
MDT1
0x03
0x02
0xD100
0xD144 (All)
DSP
0xD143 (MSB)
0xD142 (LSB)
0xD141 (Inh. bel.)
0xD140 (8 Bit)
MDT2
MDT0
0x01
0x00
0x05
0x04
0x07
0x06
MGEN
µP Mailbox
Bit
7
MCMD (µP -> DSP)
0x43
0x42
0x41
0x40
Mailbox-Synchr.
µP
ODT5
ODT6
ODT7
0x2D
0x2C
0x2F
0x2E
ODT12
ODT13
ODT14
ODT15
0x3B
0x3A
0x3D
0x3C
0x3F
0x3E
0xD13E
0xD13C
0xD13A
0xD138
0xD136
0x39
0x38
ODT11
0xD132
0xD134
ODT9
0x33
0x32
0xD130
ODT10
ODT8
0x31
0x30
0x35
0x34
0x37
0x36
0xD12E
0xD12C
0xD12A
0xD128
DSP Expanded Mailbox
ODT4
0x2B
0x2A
0xD126
0x29
0x28
ODT3
0xD122
0xD120
0xD124
ODT1
0x23
0x22
DSP
0xD163 (MSB)
0xD162 (LSB)
(16 Bit)
0xD164 (All)
0xD161
0xD160 (8 Bit)
ODT2
ODT0
0x21
0x20
0x25
0x24
0x27
0x26
OGEN
DSP Mailbox
OBUSY
(µP -> DSP)
0x63
0x62
(Inh. Bel.)
Bit
OCMD (µP <- DSP)
0x61 (8 Bit) 15
0x60
Mailbox-Synchr.
DELIC
Application Hints
Figure 10-4 Command/ Indication handshake of general mailbox
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11
Mailbox Protocol Description
The following chapters describe the way of communication between DELIC and an
external µP via the mailbox. If no DMA is used the general mailbox contains 32 data
registers. If DMA is used there are actually two different mailboxes. In this case the DMA
mailbox consists of 16 data registers and the general mailbox also contains 16 data
registers.
For more details especially initialization of the different units refer to the provided
application notes.
Note: As a reference, ELIC registers with similar functionality are appended in brackets.
11.1
Mailbox Access
11.1.1
Mailbox Access Transmit Direction (µP->DELIC)
The general mailbox for transmit direction (Figure 11-1) consists of 20 (36) registers.
One register (MCMD) contains the command to be processed by the DELIC. Another
register (MBUSY) just consists of a Busy Bit indicating whether the mailbox is free to be
written to or not. Two other registers (MGEN Low and MGEN High) serve for general
parameters. A block of 16 (32) parameter registers contains data. Writing to the
command register sets the Busy Bit and thereby an interrupt in the DELIC. If the DELIC
has processed the command it clears the Busy Bit to release the mailbox.
11.1.2
Mailbox Access Receive Direction (DELIC->µP)
The mailbox for receive direction (Figure 11-2) consists of 20 (36) registers. One register
(OCMD) contains the indication to be processed by the µP. Another register (OBUSY)
just consists of a Busy Bit which has to be cleared by the µP after processing the
indication in order to release the mailbox. Two other registers (OGEN Low and OGEN
High) serve as general parameters. A block of 16 (32) parameter registers contains data
associated with the indication.
Preliminary Data Sheet
11-1
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
7
µP
6
5
4
3
2
1
MCMD
0
DELIC
LSB
Command
0x40
MBUSY
0x41
bsy
0
0
0
0
0
0
0
MGEN Low
0x42
General Parameter 1
MGEN High
0x43
General Parameter 2
MDT0 Low
0x00
Parameter 1
MDT7 High
0x0F
Parameter 16
MDT8/TDT0 Low
0x10
Parameter 17
MDT15/TDT7 High
0x1F
Parameter 32
deli_552.emf
Figure 11-1 Transmit Mailbox Structure
Preliminary Data Sheet
11-2
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
7
6
5
4
µP
3
2
1
OCMD
0
LSB
DELIC
Indication
0x60
OBUSY
0x61
bsy
0
0
0
0
0
0
0
OGEN Low
0x62
General Parameter 1
OGEN High
0x63
General Parameter 2
ODT0 Low
0x20
Parameter 1
ODT7 High
0x2F
Parameter 16
ODT8/RDT0 Low
0x30
Parameter 17
ODT15/RDT7 High
0x3F
Parameter 32
deli_551.emf
Figure 11-2 Receive Mailbox Structure
Both sides, µP and DELIC, use the same procedure to perform write accesses to the
mailbox. If one side wants to put a message into the mailbox it has to check whether the
mailbox is free. If the mailbox is free the parameters have to be written first than the
command (Figure 11-3).
Preliminary Data Sheet
11-3
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Is mailbox free (test
OBUSY)?
No
Yes
write parameters to mailbox
(MDTx, MGEN)
write command to mailbox
(MCMD)
deli_553.emf
Figure 11-3 Flow Diagram: Mailbox Write Access
11.2
Subscriber Address (SAD) Interpretation
In this chapter SAD is used commonly for the subscriber address. There are two
possibilities to interpret SAD
11.2.1
SAD as IOM-2 Port and Channel Number
The DELIC has two IOM-2 ports. The subscriber address has to be interpreted as
follows.
bit
SAD3
7
6
5
4
3
2
1
0
SAD3
SAD2
SAD1
SAD0
IOM-2 port number (2.048 Mbit/s)
0=
IOM-2 port 0 is addressed
1=
IOM-2 port 1 is addressed
SAD2..0 IOM-2 channel number (range: 0..7) (2.048 Mbit/s)
SAD3..0 IOM-2 channel number (range: 0..15) (4.096 Mbit/s)
Preliminary Data Sheet
11-4
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.2.2
SAD as IOM-2000 VIP and Channel Number
It is possible to connect up to 3 VIPs to the DELIC via the IOM-2000 interface. Each VIP
contains up to 8 channels. The subscriber address has to be interpreted as follows.
bit
7
6
5
4
3
2
1
0
SAD4
SAD3
SAD2
SAD1
SAD0
SAD4..3 VIP number
00 = VIP 0 is addressed
01 = VIP 1 is addressed
10 = VIP 2 is addressed
11 = reserved
SAD2..0 IOM-2000 channel number (range: 0..7)
11.3
Overview of Commands and Indications
The following tables give an overview of all commands and indications according name,
code value, parameters and the referring page where the detailed description can be
found.
11.3.1
Table 11-1
Commands and Indications for Boot Sequence
Boot Commands
Name
Start Boot
MCMD
MDT0
MDT1..15
0x55
Page
11-13
Write Program Memory
0xAn
n = Amount
Start Address
Data
11-13
Write Data Memory
0xEn
n = Amount
Start Address
Data
11-14
Finish Boot
Preliminary Data Sheet
0x1F
11-13
11-5
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Table 11-2
Boot Indications
Name
OCMD
Start Loading Program RAM
0x1F
11-15
Start Loading Data RAM
0xEF
11-15
0b011100XX
XXX=Error Code
11-15
Error
Firmware Version Indication
11.3.2
Table 11-3
ODT0
0x00
Page
Version Number
11-15
ODTx
Page
General Commands and Indications
General Commands
Name
OCMD OGEN Low OGEN
High
Write Register
0x01
Size
MDT0: Destination address
MDTx: Register value(s)
11-16
Read Register
0x02
Size
MDT0: Start address for read
11-17
Table 11-4
General Indications
Name
Read Register
OCMD OGEN Low OGEN
High
0x01
Preliminary Data Sheet
Size
ODTx
Value(s) read from register
11-6
Page
11-18
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.3.3
Commands and Indications for Configuration
Table 11-5
Configuration Commands
Name
MCMD MGEN Low MGEN
High
MDTx
Page
IOM-2000
Reference
Channel Select
0x05
IOM-2000
VIP and
channel no.
11-20
IOM-2000 Delay
Measurement
0x04
IOM-2000
VIP and
channel no.
11-21
IOM-2000 VIP
Channel
Configuration
0x03
GHDLC
Configuration
0x14
Finish
Initialization
0x06
Table 11-6
GHDLC no.
11-22
MDT0 L = Mode Information
MDT1 = Normal Address
MDT2 = Broadcast Address
11-22
11-24
Configuration Indications
Name
OCMD OGEN Low OGEN
High
IOM-2000 Farend Code
Violation
0x07
IOM-2000
Delay
0x04
Delay Value
Finish VIP
Channel
Configuration1)
0x02
Delay Value
1)
MDT0 H= TICCMR[31..24]
MDT0 L= TICCMR[23..16]
MDT1 H= TICCMR[15..8]
MDT1 L= TICCMR[7..0]
Size
ODTx
Page
IOM-2000 VIP and channel no. 11-24
FECV
11-25
ODT0 H= TICSTR[31..24]
ODT0 L= TICSTR[23..16]
ODT1 H= TICSTR[15..8]
ODT1 L= TICSTR[7..0]
11-26
this indication is only sent if the read bit of TICCMR has been set in IOM-2000 VIP
Channel Configuration Command
Preliminary Data Sheet
11-7
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.3.4
Commands and Indications for IOM-2 C/I Channels
Table 11-7
IOM-2 C/I Command
Name
MCMD MGEN High
Write C/I Value
Table 11-8
Size
Page
IOM-2 port and channel no.
C/I value
11-27
IOM-2 C/I Indication
Name
OCMD OGEN High
Change Detected
11.3.5
0x23
MDTx
0x41
Size
ODTx
Page
IOM-2 port and channel no.
new C/I value
11-27
Commands and Indications for IOM-2 Monitor Channel
Table 11-9
IOM-2 Monitor Commands
Name
MCMD
MGEN Low
MGEN MDTx Page
High
Search On
0x2B
11-29
Search Reset
0x2C
11-30
Monitor Reset
0x2D
11-30
Transmit Continuous
0x29
IOM-2 port and channel no.
Size
Data
11-30
Transmit
0x28
IOM-2 port and channel no.
Size
Data
11-30
Transmit&Receive/
Receive Only
0x2A
IOM-2 port and channel no.
Size
Data
11-30
Preliminary Data Sheet
11-8
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Table 11-10 IOM-2 Monitor Indications
Name
OCMD
OGEN Low
OGEN ODTx Page
High
Transfer Ready
0x53
Receive Continuous
0x52
Size
Data
11-31
Receive
0x51
Size
Data
11-31
Transmit Abort
0x55
Monitor Active
0x54
11.3.6
11-31
11-32
IOM-2 port and channel no.
11-32
Commands and Indications for IOM-2000 C/I Channels
Table 11-11 IOM-2000 C/I Command
Name
Write C/I Value
MCMD MGEN High
0x0B
Size
MDTx
IOM-2000 VIP and channel no.
C/I value
Page
11-38
Table 11-12 IOM-2000 C/I Indication
Name
Change Detected
Preliminary Data Sheet
OCMD OGEN High
0x11
Size
ODTx
IOM-2000 VIP and channel no.
new C/I value
11-9
Page
11-38
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.3.7
Commands and Indications for HDLC Channel
Table 11-13 HDLC Commands
Name
MCMD MGEN Low MGEN
High
Size
MDTx
Page
Reset
0x1F
Transmit
0x1D
HDLC No.
Size
Data
11-41
Transmit
Continuous
0x1E
HDLC No.
Size
Data
11-41
Activation/
Deactivation
0x20
Size
HDLC No.
Receiver or Transmitter or both
HDLC No. and activation
information
11-40
11-41
Table 11-14 HDLC Indications
Name
OCMD OGEN Low OGEN High
Page
Error
0x34
HDLC No.
Transmit Ready
0x33
HDLC No.
Receive
0x31
HDLC No.
Size
Data
11-44
Receive Continuous
0x32
HDLC No.
Size
Data
11-44
11.3.8
0x01
ODTx
ODT0 L: Error Code 11-42
11-43
Commands and Indications for GHDLC Channel
Table 11-15 GHDLC Commands
Name
MCMD MGEN Low MGEN
High
MDTx
Page
Size
GHDLC No.
11-46
Reset
0x15
Transmit
0x11
GHDLC No.
Size
Data
11-47
Transmit
Continuous
0x12
GHDLC No.
Size
Data
11-48
Preliminary Data Sheet
11-10
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Table 11-16 GHDLC Indications
Name
OCMD OGEN Low OGEN High
ODTx
Page
Error
0x24
GHDLC No.
0x01
ODT0 L: Error Code 11-48
Fatal Error
0x25
GHDLC No.
0x02
ODT0: Status Word 11-48
Transmit Ready
0x23
GHDLC No.
Receive
0x21
GHDLC No.
Size
Data
11-49
Receive Continuous
0x22
GHDLC No.
Size
Data
11-49
11.3.9
11-49
Switching
Table 11-17 Switching Commands
Name
MCMD
MGEN High
Connect
0x17
Size
Disconnect
0x18
Size
11.4
MDTx
Connection Identifier
Source/Destination Interface Type
Source Time Slot No.
Destination Time Slot No.
Connection Identifier
Page
11-50
11-52
Boot Procedure
After reset the DELIC jumps into the boot routine and waits for downloading a program
via the µP-Mailbox. Figure 11-4 shows the handshake.
Preliminary Data Sheet
11-11
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
µP
DELIC
Start Loading Program RAM
Start Boot
Write Program Memory [Amount, Address, Data]
Write Program Memory [Amount, Address, Data]
Write Program Memory [Amount, Address, Data]
Finish Boot
Start Loading Data RAM
Start Boot
Write Data Memory [Amount, Address, Data]
Write Data Memory [Amount, Address, Data]
Write Data Memory [Amount, Address, Data]
Finish Boot
Firmware Version
deli_554.emf
Figure 11-4 Boot Sequence
The range for Amount must be between 1 and 15. In case of an verification failure or if
an amount of zero has been used the Start Boot Command has to be issued again before
continuing the download. After issuing Start Boot any invalid command is ignored.
Preliminary Data Sheet
11-12
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.4.1
Boot Commands
After reset the DELIC waits for downloading a program from the processor via the
mailbox indicated by the Start Loading Program RAM Indication (0x1F) (Figure 11-4).
11.4.1.1 Start Boot Command (0x55)
This command has to be issued before using the Write Program Memory Command
(0xAn) and Write Data Memory Command (0xEn) directly after receiving the Start
Loading Program RAM Indication (0x1F) or the Start Loading Data RAM Indication
(0xEF).
Mailbox Register (MCMD)
bit
µP-write
Address:
40H
7
6
5
4
3
2
1
0
0
1
0
1
0
1
0
1
11.4.1.2 Finish Boot Command (0x1F)
First usage of this command finishes filling of the program memory. The second usage
finishes filling of the data memory and let the DELIC wait for initialization commands.
Mailbox Register (MCMD)
bit
µP-write
Address:
40H
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
1
11.4.1.3 Write Program Memory Command (0xAn)
After issuing the Start Boot Command (0x55) the first time the program memory can be
filled with this command. The filling has to be finished with the Finish Boot Command
(0x1F).
Mailbox Register (MCMD)
bit
N3..0
µP-write
Address:
40H
7
6
5
4
3
2
1
0
1
0
1
0
N3
N2
N1
N0
Amount of 16-bit data words within MDT1 to MDT15 (range: 1..15)
Preliminary Data Sheet
11-13
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MDT0)
bit
7
6
µP-write
5
4
High
bit
Address: 00+01H
3
2
1
0
2
1
0
AD(15:8)
7
6
5
4
Low
3
AD(7:0)
AD15..0
Start Address (DELIC Address Space)
11.4.1.4 Write Data Memory Command (0xEn)
After issuing the Start Boot Command (0x55) the second time the data memory can be
filled with this command. The filling has to be finished with the Finish Boot Command
(0x1F).
Mailbox Register (MCMD)
bit
µP-write
6
5
4
3
2
1
0
1
1
1
0
N3
N2
N1
N0
Amount of 16-bit data words within MDT1 to MDT15 (range: 1..15)
Mailbox Register (MDT0)
7
6
µP-write
5
4
High
bit
Address: 00+01H
3
2
1
0
2
1
0
AD(15:8)
7
6
Low
AD15..0
40H
7
N3..0
bit
Address:
5
4
3
AD(7:0)
Start Address (DELIC Address Space)
Preliminary Data Sheet
11-14
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.4.2
Boot Indications
11.4.2.1 Error Indication (0b011100XX)
Mailbox Register (OCMD)
bit
µP-read
Address:
60H
7
6
5
4
3
2
1
0
0
1
1
1
0
0
EN1
EN0
EN1..0
Error Code
00 =
Wrong command error
01 =
Data verification failure
10 =
Incorrect amount of data (zero size)
Note: After an zero size error and after a verification failure the
Start Boot Command (0x55) has to be issued again.
11.4.2.2 Start Loading Program RAM Indication (0x1F)
This indication is issued after reset to inform the processor that program download can
begin.
Mailbox Register (OCMD)
bit
µP-read
Address:
60H
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
1
11.4.2.3 Start Loading Data RAM Indication (0xEF)
This indication is issued after issuing the Finish Boot Command (0x1F) the first time to
inform the processor that data download can begin.
Mailbox Register (OCMD)
bit
µP-read
Address:
60H
7
6
5
4
3
2
1
0
1
1
1
0
1
1
1
1
11.4.2.4 Firmware Version Indication (0x00)
This indication is sent after the last Finish Boot Command (0x1F) to confirm the correct
program and daa boot.
Preliminary Data Sheet
11-15
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (ODT0)
bit
7
6
µP-read
5
High
bit
4
Address: 20+21H
3
2
1
0
2
1
0
FVNO(15:8)
7
6
5
Low
4
3
FVNO(7:0)
FVNO15..0 Firmware Version Number
11.5
General Commands and Indications
The following commands and indications are used during initialization and during normal
operation.
11.5.1
General Commands
11.5.1.1 Write Register Command (0x01)
The command writes any 16-bit value(s) to DELIC’s register(s), starting from the
specified destination address (and continuing to the consecutive address(es)).
Parameter:
– Number of values to be written
– Destination address for write
– Register value(s) to be written
Mailbox Register (MGEN Low)
µP-write
bit
4
SIZE3..0
7
6
5
Address:
42H
3
2
1
0
(SIZE3)
SIZE2
SIZE1
SIZE0
Number of valid 16-bit values within MDT1..7(15) (range: 1..7(15))
Preliminary Data Sheet
11-16
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MDT0)
bit
7
6
µP-write
5
High
bit
4
3
2
1
0
2
1
0
2
1
0
2
1
0
DAD(15:8)
7
6
5
Low
4
3
DAD(7:0)
DAD15..0
Destination Address (DELIC Address Space)
Mailbox Register (MDT1..7(15))
µP-write
bit
4
7
6
5
High
bit
Address: 00+01H
3
WRV(15:8)
7
6
Low
WRV15..0
5
4
3
WRV(7:0)
MDT1: Write Value to Destination Address DAD
MDT2: Write Value to Destination Address DAD+1
..
MDT7(15): Write Value to Destination Address DAD+6(14)
11.5.1.2 Read Register Command (0x02)
The command initiates read access(es) to DELIC’s register(s), starting from the
specified base address (and continuing to the consecutive address(es)).
Preliminary Data Sheet
11-17
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Parameter:
– Number of values to be read
– Base address for read
Mailbox Register (MGEN Low)
µP-write
bit
4
3
2
1
0
(SIZE4)
SIZE3
SIZE2
SIZE1
SIZE0
7
SIZE4..0
6
5
7
6
µP-write
5
High
bit
42H
Amount of 16-bit values to be read from the base address (range: 1..8(16))
Mailbox Register (MDT0)
bit
Address:
4
Address: 00+01H
3
2
1
0
2
1
0
BAD(15:8)
7
6
5
Low
4
3
BAD(7:0)
BAD15..0 Base address from which register value is to be read
11.5.2
General Indication
11.5.2.1 Read Register Indication (0x01)
The indication returns the values read from DELIC’s register(s) as specified in the Read
Register Command (0x02).
Preliminary Data Sheet
11-18
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Parameter:
– Number of read values
– Read register values
Mailbox Register (OGEN Low)
bit
15
SIZE4..0
14
13
µP-read
62H
12
11
10
9
8
(SIZE4)
SIZE3
SIZE2
SIZE1
SIZE0
Number of valid 16-bit values that have been read (range: 1..8(16))
Mailbox Register (ODT0..7(14))
µP-read
bit
4
7
6
5
High
bit
Address:
3
2
1
0
2
1
0
RRV(15:8)
7
6
Low
5
4
3
RRV(7:0)
RRV15..0 ODT0: Read Register Value from Base Address BAD
ODT1: Read Register Value from Base Address BAD+1
..
ODT7(15): Read Register Value from Base Address BAD+7(15)
11.6
Initialization/Configuration
After issuing the last Finish Boot Command (0x1F) the DELIC waits for the Finish
Initialization Command (0x06) before it starts all tasks. Here the device can be
configured according the application requirements.
Preliminary Data Sheet
11-19
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
µP
DELIC
Finish Boot
Any configuration command
Any configuration command
Write Register [Amount, Address, Data]
Read Register [Amount, Address]
Read Register [Amount, Data]
IOM-2000 VIP Channel Configuration
Finish VIP Channel Configuration
Finish Initialization
deli_550.emf
Figure 11-5 Initialization Flow Diagram: Configuration Example
11.6.1
Configuration Commands
11.6.1.1 IOM-2000 Reference Channel Select Command (0x05)
The command selects the VIP channel which provides the reference clock.
Parameter:
– IOM-2000 VIP and channel number
– External reference source
Preliminary Data Sheet
11-20
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MGEN Low)
µP-write
bit
5
4
3
2
1
0
EXREF
SAD4
SAD3
SAD2
SAD1
SAD0
7
6
Address:
42H
SAD4..0 Subscriber Address i.e. IOM-2000 VIP and channel number
EXREF
External Reference Clock Selection (LT-T)
0 = No external reference clock source. Reference clock is generated from
internal VIP_n channel specified in REFCLK(2:0) and passed on via
REFCLK pin to VIP_n-1 or directly to DELIC.
1 = Reference clock is generated from external source via pin INCLK and
passed on via REFCLK pin to VIP_n-1 or directly to DELIC. The internal
reference clock generation logic is disabled.
Note: VIP_0 has the highest priority in terms of clock selection
Note: This command is only applicable for channels in LT-T Mode
11.6.1.2 IOM-2000 Delay Measurement Command (0x04)
This command selects the VIP channel in which the line delay is to be measured. The
delay is reported with the IOM-2000 Delay Indication (0x04).
Parameter:
– IOM-2000 VIP and channel number
Mailbox Register (MGEN Low)
µP-write
bit
4
3
2
1
0
SAD4
SAD3
SAD2
SAD1
SAD0
SAD4..0
7
6
5
Address:
42H
Subscriber Address i.e. IOM-2000 VIP and channel number
Note: This command is only applicable for channels in UPN Mode
Preliminary Data Sheet
11-21
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.6.1.3 IOM-2000 VIP Channel Configuration Command (0x03)
The command initializes or re configures the channel register in the TRANSIU for the
specified VIP channel.
Parameter:
– Initialization values of VIP Channel Command Register TICCR (4 bytes including VIP
and channel number)
Mailbox Register (MDT0 High)
bit
15
14
x
13
µP-write
12
VIPADR(1:0)
Address:
11
10
CHADR(2:0)
Mailbox Register (MDT0 Low)
µP-write
bit
01H
9
8
FIL
EXLP
Address:
00H
7
6
5
4
3
2
1
0
PLLS
PD
DHEN
x
x
PDOWN
LOOP
TX_EN
Mailbox Register (MDT1 High)
bit
15
14
PLLINT
13
AAC(1:0)
µP-write
12
µP-write
bit
4
6
MF_EN
5
11
10
BBC(1:0)
Mailbox Register (MDT1 Low)
7
Address:
MODE(2:0)
9
03H
8
OWIN(2:0)
Address:
3
2
MOSEL(1:0)
02H
1
0
RD
WR
Note: For the meaning of the bits, refer to "TRANSIU Initialization Channel Command
Register" on page 6-15. ’x’=unused
11.6.1.4 GHDLC Configuration Command (0x14)
Mailbox Register (MGEN Low)
µP-write
bit
4
GCA1..0
7
6
5
Address:
3
2
42H
1
0
GCA1
GCA0
GHDLC Channel Address
00 = GHDLC Channel 0 (all other combinations are reserved)
Preliminary Data Sheet
11-22
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MDT0 Low)
µP-write
bit
4
7
AUTO
6
5
Address:
3
2
00H
1
0
ADM
AUTO
Auto Mode Enable
0 = Disable Auto Mode
1 = Enable Auto Mode
ADM
Address Mode
0 = 8-bit address mode
1 = 16-bit address mode
Mailbox Register (MDT1)
bit
7
6
µP-write
5
High
bit
4
Address: 02+03H
3
2
1
0
2
1
0
AAD(15:8)
7
6
Low
5
4
3
AAD(7:0)
AAD15..0 Address for address recognition (ELIC reg. RAL1 and RAH1)
Note: If ADM is set to 0 (8-bit address) only the low part is considered
Preliminary Data Sheet
11-23
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MDT2)
bit
7
µP-write
6
5
4
High
bit
Address: 04+05H
3
2
1
0
2
1
0
BAD(15:8)
7
6
5
4
Low
3
BAD(7:0)
BAD15..0 Broadcast address (ELIC reg. RAL2 and RAH2)
Note: If ADM is set to 0 (8-bit address) only the low part is considered
11.6.1.5 Finish Initialization Command (0x06)
This command has to be issued after downloading program and data and configuring the
DELIC correctly. It forces the DELIC to start with all tasks.
Mailbox Register (MCMD)
bit
µP-write
Address:
40H
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
0
11.6.2
Configuration Indications
11.6.2.1 IOM-2000 Far-end Code Violation Indication (0x07)
This indication reports a far-end code violation (FECV) in the specified VIP channel.
Parameter:
– IOM-2000 VIP and channel number
Mailbox Register (OGEN High)
µP-read
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
SIZE5..0
7
6
Address:
63H
Amount of entries in ODT0..7(15) (range: 1..16(32))
Preliminary Data Sheet
11-24
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
For every entry (one byte per entry):
Mailbox Register (ODT0..7(15))
µP-read
bit
4
3
2
1
0
SAD4
SAD3
SAD2
SAD1
SAD0
7
6
5
FECV
SAD4..0
Subscriber Address i.e. IOM-2000 VIP and channel number
FECV
Far-end Code Violation
0 = No far-end code violation detected
1 = Far-end code violation (bit error) detected
11.6.2.2 IOM-2000 Delay Indication (0x04)
This indication returns the measured line delay value of an UPN channel. This indication
is the answer to the IOM-2000 Delay Measurement Command (0x04).
Parameter:
– IOM-2000 VIP and channel number
– Delay Value
Mailbox Register (OGEN High)
bit
15
SAD4..0
14
13
µP-read
63H
12
11
10
9
8
SAD4
SAD3
SAD2
SAD1
SAD0
Subscriber Address i.e. IOM-2000 VIP and channel number
Mailbox Register (OGEN Low)
µP-read
bit
DV7..0
Address:
Address:
62H
7
6
5
4
3
2
1
0
DV7
DV6
DV5
DV4
DV3
DV2
DV1
DV0
Delay Value
Note: This command is only applicable for channels in UPN Mode
Preliminary Data Sheet
11-25
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.6.2.3 Finish VIP Channel Configuration Indication (0x02)
After issuing the IOM-2000 VIP Channel Configuration Command (0x03) with set read
bit the DELIC confirms the command by this indication.
Mailbox Register (ODT0 High)
bit
15
x
14
13
µP-read
12
VIPADR(1:0)
11
10
CHADR(2:0)
Mailbox Register (ODT0 Low)
µP-read
bit
21H
9
8
FIL
EXLP
Address:
20H
7
6
5
4
3
2
1
0
PLLS
PD
DHEN
x
x
PDOWN
LOOP
TX_EN
Mailbox Register (ODT1 High)
bit
Address:
15
14
PLLINT
13
AAC(1:0)
µP-read
12
µP-read
bit
4
6
MF_EN
5
11
10
BBC(1:0)
Mailbox Register (ODT1 Low)
7
Address:
MODE(2:0)
9
23H
8
OWIN(2:0)
Address:
3
2
MOSEL(1:0)
22H
1
0
RD
WR
Note: For the meaning of the bits, refer to "TRANSIU Initialization Channel Status
Register (TICSTR)" on page 6-20. ’x’=unused
11.7
IOM-2 C/I Handling
Purpose of the C/I handler is to transmit C/I values and to receive C/I value changes on
the C/I channels. The C/I values itself are not interpreted.
A new C/I value will be considered if it is detected for at least two consecutive frames
(double last look).
The DELIC considers all channels affected by at least one C/I value change. After
detecting the first change the DELIC reports it to the µP. As soon as the mailbox is free
the DELIC sends the current C/I values of the affected channels, together with their
addresses, to the µP. If the µP is fast enough to serve the interrupts every change will
be reported. But if the µP is not as fast preceding changes according to the same
channel will be lost (Figure 11-6).
Preliminary Data Sheet
11-26
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.7.1
IOM-2 C/I Command
The following command is sent from the µP to the DELIC.
11.7.1.1 Write C/I Value Command (0x23)
(ELIC Reg.: MACR, MADR, MAAR)
This command provides the DELIC with new C/I values to be sent on the specified
channels. It can be issued any time.
Parameter:
– Amount of following entries
For every entry:
– IOM-2 port and channel number
– C/I value
See "Common Mailbox Parameter Structure" on page 11-27
11.7.2
IOM-2 C/I Indication
The following indication is sent from the DELIC to the µP.
11.7.2.1 Change Detected Indication (0x41)
If at least one change is detected this indication will be issued. The amount of entries
depends on the mailbox size and the amount of used IOM-2 channels. Maximum values
of 8 entries (if DMA is used) or 16 (if DMA is not used) are possible.
Parameter:
– Amount of following entries
For every entry:
– IOM-2 port and channel number
– C/I value
See "Common Mailbox Parameter Structure" on page 11-27
11.7.3
Common Mailbox Parameter Structure
Both command and indication have the same structure.
Preliminary Data Sheet
11-27
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MGEN High)
µP-write
Address:
43H
Mailbox Register (OGEN High)
µP-read
Address:
63H
bit
4
3
2
1
0
(SIZE4)
SIZE3
SIZE2
SIZE1
SIZE0
7
SIZE4..0
6
5
Amount of valid entries in MDT0..7(15) or ODT0..7(15) (range: 1..8(16))
For every entry (two bytes per entry):
Mailbox Register (MDT0..7(15) Low)
µP-write
Mailbox Register (ODT0..7(15) Low)
µP-read
bit
4
7
SAD3..0
6
5
3
2
1
0
SAD3
SAD2
SAD1
SAD0
Subscriber Address i.e. IOM-2 port and channel number
Mailbox Register (MDT0..7(15) High) µP-write
Mailbox Register (ODT0..7(15) High) µP-read
bit
7
6
CI5..0
6-bit C/I value
CI3..0
4-bit C/I value
11.7.4
Flow Diagram
5
4
3
2
1
0
CI5
CI4
CI3
CI2
CI1
CI0
The following diagram describes the way of handling C/I value changes. It is assumed
that the mailbox is not free as the first change was detected. After releasing the mailbox
by the µP the DELIC sends the C/I values and their IOM-2 channel addresses. The
preceding change on channel 6 will not be reported.
Preliminary Data Sheet
11-28
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
µP
DELIC
IOM-2
1st C/I Value Change [ch3]
2nd C/I Value Change [ch6]
(N-1)th C/I Value Change [ch2]
Release Mailbox
Nth C/I Value Change [ch6]
Change Detected Indication
[N, channel + value..]
deli_555.emf
Figure 11-6 C/I Flow Diagram: Receiving C/I Value Changes
11.8
IOM-2 Monitor Handling
According to the monitor channels the DELIC has to manage the data exchange
between IOMU and mailbox. Only one of all possible channels is served at the same
time. The main task of the DELIC is to transform an acknowledged block stream from
and to the mailbox to an acknowledged byte stream from and to the IOMU. If the µP
issues a command it has to wait for the related indication before the next command can
be issued.
11.8.1
IOM-2 Monitor Commands
The following commands are sent from the µP to the DELIC:
11.8.1.1 Search On Command (0x2B)
(ELIC bit: MFSO)
By this command the DELIC is instructed to search for an active monitor channel. After
finding an active channel the search mechanism is stopped and the event is reported
with Monitor Active Indication. This command can be issued any time. If there is a
transmission command in progress the Search Mode is started after transmission was
terminated.
Preliminary Data Sheet
11-29
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.8.1.2 Search Reset Command (0x2C)
(ELIC bit: OMSO)
By this command the Search Mode is stopped. This command can be issued any time.
It will not stop a running transmission.
11.8.1.3 Monitor Reset Command (0x2D)
(ELIC bit: MFFR)
By this command the execution of the current transfer command is stopped immediately.
11.8.1.4 Transmit Continuous Command (0x29)
(ELIC bits: MFT1..0)
This command starts transmission of one of more blocks. The Search Mode is
suspended until transmission was terminated. After acknowledging the last sent byte
Transfer Ready is issued to ask for a new block. The size of the blocks is variable. The
last block is sent with Transmit or Transmit & Receive. Only with the first appearance of
this command the first parameter will be considered.
Parameter:
– IOM-2 port and channel number
– Size of data block
– Data block
See "Common Mailbox Parameter Structure" on page 11-32
11.8.1.5 Transmit Command (0x28)
(ELIC bits: MFT1..0)
This command starts transmission of a single/last block. The Search Mode is suspended
until transmission was terminated. After transmission was completed (rising edge of MR)
Transfer Ready is issued. If this command follows after Transmit Continuous the first
parameter will be ignored.
Parameter:
– IOM-2 port and channel number
– Size of data block
– Data block
See "Common Mailbox Parameter Structure" on page 11-32
11.8.1.6 Transmit&Receive/Receive Only Command (0x2A)
(ELIC bits: MFT1..0)
This command starts transmission of a single/last block and waits for reception on the
same channel. The Search Mode is suspended during transmission and reception. If this
Preliminary Data Sheet
11-30
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
command follows after Transmit Continuous the first parameter will be ignored.
Received blocks are reported with Receive and/or Receive Continuous. If size of data is
zero the command has the meaning of Receive Only i.e. reception on the specified
channel is activated.
Parameter:
– IOM-2 port and channel number
– Size of data block
– Data block
See "Common Mailbox Parameter Structure" on page 11-32
11.8.2
IOM-2 Monitor Indications
The following indications are sent from the DELIC to the µP.
11.8.2.1 Transfer Ready Indication (0x53)
(ELIC bit: MFFI)
Indicates end of Transmit or end of Transmit Broadcast or asks for a new block after
Transmit Continuous.
11.8.2.2 Receive Continuous Indication (0x52)
(ELIC bit: MFFI)
This indication reports one of more received blocks to the µP. The reception has not
been terminated yet.
Parameter:
– Size of data block
– Data block
Mailbox Register (OGEN High)
µP-read
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
SIZE5..0
7
6
Address:
63H
Amount of following data bytes within ODT0..7(15) (range: 1..16(32))
11.8.2.3 Receive Indication (0x51)
(ELIC bits: MFFI, MFFE)
The only/last received block is reported to the µP.
Preliminary Data Sheet
11-31
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Parameter:
– Size of data block
– Data block
Mailbox Register (OGEN High)
µP-read
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
7
SIZE5..0
6
Address:
63H
Amount of following data bytes within ODT0..7(15) (range: 1..16(32))
11.8.2.4 Transmit Abort Indication (0x55)
(ELIC bit: MFAB)
The remote receiver aborted reception of a locally issued Transmit Command.
11.8.2.5 Monitor Active Indication (0x54)
(ELIC bit: MAC)
Informs the µP that an active monitor channel has been found. The µP may issues
Receive Only to activate the receiver.
Parameter:
– IOM-2 port and channel number
Mailbox Register (OGEN Low)
µP-read
Address:
62H
Reset value: unchanged
bit
7
6
5
4
3
2
1
0
SAD3
SAD2
SAD1
SAD0
SAD3..0
Subscriber Address i.e. IOM-2 port and channel number (up to 16 channels)
11.8.3
Common Mailbox Parameter Structure
This structure is valid for Transmit Continuous Command (0x29), Transmit Command
(0x28), Transmit&Receive/Receive Only Command (0x2A).
Preliminary Data Sheet
11-32
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MGEN Low)
µP-write
bit
4
7
SAD3..0
6
5
Address:
42H
3
2
1
0
SAD3
SAD2
SAD1
SAD0
Subscriber Address i.e. IOM-2 port and channel number (up to 16 channels)
Mailbox Register (MGEN High)
µP-write
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
7
6
Address:
43H
SIZE5..0
Amount of following data bytes within MDT0..7(15) (range: 1..16(32))
11.8.4
Flow Diagrams
The following flow diagrams describe the way the DELIC transforms the protocols. N and
M are always less or equal the mailbox size and less or equal the buffer size.
µP
DELIC
Transmit [ch, N Bytes]
IOM-2 [ch]
1st Byte
Ack
N th Byte
Ack
EOM
EOM Ack
Transfer Ready
deli_559.emf
Figure 11-7 Monitor Flow Diagram: Transmit
Preliminary Data Sheet
11-33
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
µP
DELIC
Transmit Continuous [ch, N Bytes]
IOM-2 [ch]
1st Byte 1st Block
Ack
N th Byte 1st Block
Ack
Transfer Ready
Transmit [M Bytes]
1st Byte Last Block
Ack
M th Byte Last Block
Ack
EOM
EOM Ack
Transfer Ready
deli_560.emf
Figure 11-8 Monitor Flow Diagram: Transmit Continuous
Preliminary Data Sheet
11-34
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
µP
DELIC
IOM-2 [ch]
Search On
1st Byte
Monitor Active [ch]
Receive Only [ch]
1st Byte
Ack
N th Byte
Ack
EOM
EOM Ack
Receive [N Bytes]
deli_563.emf
Figure 11-9 Monitor Flow Diagram: Search Mode
Preliminary Data Sheet
11-35
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
µP
DELIC
Receive Only [ch]
IOM-2 [ch]
1st Byte
Ack
16 th (32 th) Byte
Ack
17 th (33 th) Byte
Receive Continuous [16 (32) Bytes]
17 th (33 th) Byte
Ack
Last Byte
Ack
EOM
EOM Ack
Receive [Last Bytes]
deli_562.emf
Figure 11-10 Monitor Flow Diagram: Receive Only with Receive Continuous
Preliminary Data Sheet
11-36
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
µP
DELIC
Transmit & Receive [ch, N Bytes]
IOM-2 [ch]
1st Byte
Ack
N th Byte
Ack
EOM
EOM Ack
1st Byte
Ack
M th Byte
Ack
EOM
EOM Ack
Receive [M Bytes]
deli_561.emf
Figure 11-11 Monitor Flow Diagram: Transmit & Receive
11.9
IOM-2000 C/I Handling
The layer 1 state machine is accessed the same way as the C/I channels.
11.9.1
IOM-2000 C/I Command
The following command is sent from the µP to the DELIC:
Preliminary Data Sheet
11-37
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.9.1.1 Write C/I Value Command (0x0B)
This command provides the DELIC with new C/I values to be sent on the specified
channels. It can be issued any time.
Parameter:
– Amount of following entries
For every entry:
– IOM-2000 VIP and channel number
– C/I value
See "Common Mailbox Parameter Structure" on page 11-38
11.9.2
IOM-2000 C/I Indication
The following indication is sent from the DELIC to the µP.
11.9.2.1 Change Detected Indication (0x11)
If at least one change is detected this indication will be issued. The amount of entries
depends on the mailbox size and the amount of used IOM-2000 channels. Maximum
values of 8 entries (if DMA is used) or 16 (if DMA is not used) are possible.
Parameter:
– Amount of following entries
For every entry:
– IOM-2000 VIP and channel number
– C/I value
See "Common Mailbox Parameter Structure" on page 11-38
11.9.3
Common Mailbox Parameter Structure
Both command and indication use the same structure.
Mailbox Register (MGEN High)
µP-write
Address:
43H
Mailbox Register (OGEN High)
µP-read
Address:
63H
bit
4
3
2
1
0
(SIZE4)
SIZE3
SIZE2
SIZE1
SIZE0
SIZE4..0
7
6
5
Amount of valid entries in MDT0..7(15) or ODT0..7(15) (range: 1..8(16))
Preliminary Data Sheet
11-38
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
For every entry (two bytes per entry):
Mailbox Register (MDT0..7(15) Low)
µP-write
Mailbox Register (ODT0..7(15) Low)
µP-read
bit
4
3
2
1
0
SAD4
SAD3
SAD2
SAD1
SAD0
7
SAD4..0
6
5
Subscriber Address i.e. IOM-2000 VIP and channel number
Mailbox Register (MDT0..7(15) High) µP-write
Mailbox Register (ODT0..7(15) High) µP-read
bit
7
6
5
CI3..0
C/I value
11.10
HDLC Handling
Flag
Address
Control
4
I-
Field
3
2
1
0
CI3
CI2
CI1
CI0
CRC
Flag
Auto Mode
Non-Auto Mode
Transparent Mode 1
Transparent Mode 0
Extended Transparent Mode
Device
User
deli_556.emf
Figure 11-12 HDLC Frame Structure
11.10.1
HDLC Commands
The following commands are sent from the µP to the DELIC.
Preliminary Data Sheet
11-39
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.10.1.1 Reset Command (0x1F)
This command resets the specified HDLC controllers.
Parameter:
– Amount of following entries
For every entry:
– HDLC channel address
– Receiver or transmitter or both
Mailbox Register (MGEN High)
µP-write
bit
4
3
2
1
0
(SIZE4)
SIZE3
SIZE2
SIZE1
SIZE0
7
SIZE4..0
6
5
Address:
43H
Amount of following entries within MDT0..7(15) (range: 1..8(12))
For every entry (two bytes per entry):
Mailbox Register (MDT0..7(15) Low)
µP-write
bit
4
3
2
1
0
HCA4
HCA3
HCA2
HCA1
HCA0
2
1
0
7
HCA4..0
6
5
HDLC Channel Address
Mailbox Register (MDT0..7(15) High) µP-write
bit
7
6
5
4
3
RX
TX
TX
Transmitter will be reset (ELIC bit XRES)
0 = No action
1 = Reset
RX
Receiver will be reset (ELIC bit RHR)
0 = No action
1 = Reset
Preliminary Data Sheet
11-40
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.10.1.2 Transmit Command (0x1D)
(ELIC bits: XTF, XME)
This command initiates sending of a single message or the last block of a long message.
After transmission Transmit Ready will be issued.
Parameter:
– HDLC channel address
– Amount of data bytes
– Data bytes
See "Common Mailbox Parameter Structure" on page 11-44
11.10.1.3 Transmit Continuous Command (0x1E)
(ELIC bit: XTF)
This command allows sending of one of more blocks. The last block has to be sent with
the Transmit Command. The next block is requested by Transmit Ready Indication.
Parameter:
– HDLC channel address
– Amount of data bytes
– Data bytes
See "Common Mailbox Parameter Structure" on page 11-44
11.10.1.4 Activation/Deactivation Command (0x20)
(ELIC bit: RAC)
The command activates or deactivates the specified HDLC channel.
Parameter:
– Amount of following entries
For every entry:
– HDLC channel address
Mailbox Register (MGEN High)
µP-write
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
SIZE5..0
7
6
Address:
43H
Amount of following bytes within MDT0..7(15) (range: 1..16(32))
Preliminary Data Sheet
11-41
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
For every entry (one byte per entry):
Mailbox Register (MDT0..7(15))
µP-write
bit
4
3
2
1
0
HCA4
HCA3
HCA2
HCA1
HCA0
7
6
5
D
HCA4..0
HDLC Channel Address
D
Activation/Deactivation bit
0 = Activate HDLC channel
1 = Deactivate HDLC channel
Note: Both receiver and transmitter are activated/deactivated
11.10.2
HDLC Indications
The following indications are sent from the DELIC to the µP.
11.10.2.1 Error Indication (0x34)
This indication reports HDLC errors to the µP.
Parameter:
– HDLC channel address
– Error code
According to the receiver following errors can occur: Abort, CRC-Check failure, byte not
complete, address recognition error, receive buffer overflow, extended HDLC frame (i.e.
neither a RR nor an I frame in Auto Mode).
According to the transmitter following errors can occur: underflow of the transmit buffer,
repeat request according to long messages (long frame polled twice, collision after first
block).
Mailbox Register (OGEN Low)
µP-read
bit
4
3
2
1
0
HCA4
HCA3
HCA2
HCA1
HCA0
HCA4..0
7
6
5
Address:
62H
HDLC Channel Address
Preliminary Data Sheet
11-42
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (ODT0 Low)
µP-read
bit
7
RXE2..0
6
5
4
TXE2
TXE1
TXE0
Address:
3
20H
2
1
0
RXE2
RXE1
RXE0
Receiver Error Codes
001 = Abort (ELIC bits VFR, RAB)
010 = CRC check failure (ELIC bit CRC)
011 = Non octet (ELIC bit VFR)
100 = Address recognition error (ELIC bits HA1..0)
101 = Frame too short (ELIC bit VFR)
110 = Receive buffer overflow (ELIC bits RFO, RDO)
111 = Extended HDLC frame (Auto Mode: neither RR nor I frame) (ELIC
bit EHC)
TXE2..0
Transmitter Error Codes
001 = Transmit buffer underflow (ELIC bits XDU, EXE)
010 = Repeat Request (ELIC bit XMR)
011 = Transmit buffer overflow
100 = Collision Detected
11.10.2.2 Transmit Ready Indication (0x33)
(ELIC bit XPR)
This indication informs the µP which HDLC controller finished the last transmit
command.
Parameter:
– HDLC channel address
Mailbox Register (OGEN Low)
µP-read
bit
4
3
2
1
0
HCA4
HCA3
HCA2
HCA1
HCA0
HCA4..0
7
6
5
Address:
62H
HDLC Channel Address
Preliminary Data Sheet
11-43
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.10.2.3 Receive Indication (0x31)
(ELIC bit RME)
This indication reports a single or the last received block to the µP.
Parameter:
– HDLC channel address
– Amount of data bytes
– Data bytes
See "Common Mailbox Parameter Structure" on page 11-44
11.10.2.4 Receive Continuous Indication (0x32)
(ELIC bit RPF)
This indication sends a received block to the µP. More data follows. The last block will
be sent with Receive Indication.
Parameter:
– HDLC channel address
– Amount of data bytes
– Data bytes
See "Common Mailbox Parameter Structure" on page 11-44
11.10.3
Common Mailbox Parameter Structure
The following structure is valid for following commands or indications respectively:
Transmit Command (0x1D), Transmit Continuous Command (0x1E), Receive Indication
(0x31), Receive Continuous Indication (0x32).
Mailbox Register (MGEN Low)
µP-write
Address:
42H
Mailbox Register (OGEN Low)
µP-read
Address:
62H
bit
4
3
2
1
0
HCA4
HCA3
HCA2
HCA1
HCA0
HCA4..0
7
6
5
HDLC Channel Address
Preliminary Data Sheet
11-44
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MGEN High)
µP-write
Address:
43H
Mailbox Register (OGEN High)
µP-read
Address:
63H
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
7
SIZE5..0
6
Amount of following data bytes within MDT0..7(15) or ODT0..7(15)
Note: A SIZE value of ’0’ stands for a byte count of zero data bytes. Thus
the width of SIZE is 5 bits to include a mailbox transfer of 16 data
bytes, or 6 bits to include a mailbox transfer of 32 data bytes.
11.10.4
Flow Diagrams
µP
DELIC
B/D [ch]
Transmit [ch, N Bytes]
HDL
C Fr
am e
Transfer Ready [ch]
deli_557.emf
Figure 11-13 HDLC Flow Diagram: Transmit
µP
DELIC
B/D [ch]
Transmit Continuous [ch, N Bytes]
Transfer Ready [ch]
Transmit Continuous [ch, N Bytes]
HD
LC
Transfer Ready [ch]
Fra
me
Transmit [ch, M Bytes]
Transfer Ready [ch]
deli_558.emf
Figure 11-14 HDLC Flow Diagram: Transmit Continuous
Preliminary Data Sheet
11-45
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.11
GHDLC Handling
According to the commands and indications the same parameter structure as in HDLC
handling is used. The only difference is that HCA4..0 (HDLC channel address) is called
GCA1..0 (GHDLC channel address).
11.11.1
GHDLC Commands
11.11.1.1 Reset Command (0x15)
This command resets the specified GHDLC channel.
Parameter:
– Amount of following entries
For every entry:
– GHDLC channel address
Mailbox Register (MGEN High)
µP-write
bit
4
7
6
5
Address:
3
2
43H
1
0
SIZE1
SIZE0
1
0
GCA1
GCA0
Amount of following bytes within MDT0..7(15)
SIZE1..0
For every entry (one byte per entry):
Mailbox Register (MDT0 and MDT1)
µP-write
bit
4
GCA1..0
7
6
5
3
2
GHDLC Channel Address
Preliminary Data Sheet
11-46
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.11.1.2 Transmit Command (0x11)
Parameter:
–
–
–
–
–
GHDLC channel address
Transmit prepared or direct data
Enable/Disable auto repeat
Amount of data bytes
Data bytes
Mailbox Register (MGEN Low)
µP-write
bit
4
7
6
XPD/
XDD
AREP
5
Address:
3
2
42H
1
0
GCA1
GCA0
XPD/XDD Transmit prepared or direct data (Auto Mode only)
0 = Transmit direct data
1 = Transmit prepared data
AREP
Auto Repeat Enable
0 = Disable Auto Repeat
1 = Enable Auto Repeat
GCA1..0
GHDLC Channel Address
00= GHDLC Channel 0 (all other combinations are reserved)
Mailbox Register (MGEN High)
µP-write
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
SIZE5..0
7
6
Address:
43H
Amount of data bytes within MDT0..7(15) (range: 1..16(32))
Preliminary Data Sheet
11-47
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.11.1.3 Transmit Continuous Command (0x12)
Parameter:
– GHDLC channel address
– Amount of data bytes
– Data bytes
Mailbox Register (MGEN Low)
µP-write
bit
4
7
GCA1..0
6
5
Address:
3
2
42H
1
0
GCA1
GCA0
GHDLC Channel Address
00= GHDLC Channel 0 (all other combinations are reserved)
Mailbox Register (MGEN High)
µP-write
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
7
6
Address:
SIZE5..0
Amount of data bytes within MDT0..7(15) (range: 1..16(32))
11.11.2
GHDLC Indications
43H
11.11.2.1 Error Indication (0x24)
For the structure see "Error Indication (0x34)" on page 11-42 and replace HCA4..0
(HDLC channel address) with GCA1..0 (GHDLC channel address).
11.11.2.2 Fatal Error Indication (0x25)
This indication reports the status of the GHDLC unit to the µP in case of an error.
Parameter:
– GHDLC channel address
– Status of GHDLC channel
Preliminary Data Sheet
11-48
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (OGEN Low)
µP-read
bit
4
7
GCA2..0
6
5
Address:
3
2
62H
1
0
GCA1
GCA0
GHDLC Channel Address
Mailbox Register (ODT0 High)
µP-read
bit
Address:
21H
7
6
5
4
3
2
1
0
x
x
x
x
x
x
COLLD
UNDER
Mailbox Register (ODT0 Low)
µP-read
bit
4
7
6
5
EMPTY
OVER
FULL
Address:
3
2
1
20H
0
RBFILL(4:0)
Note: For the meaning of the bits, refer to "GHDLC Receive Channel Status Registers
0..3" on page 6-40
11.11.2.3 Transmit Ready Indication (0x23)
For the structure see "Transmit Ready Indication (0x33)" on page 11-43 and replace
HCA4..0 (HDLC channel address) with GCA1..0 (GHDLC channel address).
11.11.2.4 Receive Indication (0x21)
For the structure see "Receive Indication (0x31)" on page 11-44 and replace HCA4..0
(HDLC channel address) with GCA1..0 (GHDLC channel address).
11.11.2.5 Receive Continuous Indication (0x22)
For the structure see "Receive Continuous Indication (0x32)" on page 11-44 and replace
HCA4..0 (HDLC channel address) with GCA1..0 (GHDLC channel address).
Preliminary Data Sheet
11-49
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
11.12
B-Channel Switching
(ELIC registers MAAR, MADR, MACR)
Purpose of the switching task is to manage connections between time slots i.e. to
transfer data between memory locations. To every connection an identification is
assigned in order to make fast disconnection possible and to avoid hole handling within
the used connection table.
The connection information can be read back with the "Read Register Command (0x02)"
on page 11-17. The internal connection table (base address t.b.d.) contains consecutive
entries consisting of two consecutive 16-bit values each determining the source (first
word) and destination (second word) time slot address. The actual time slot can be
recalculated with the following table.
Table 11-18 Time Slot Address Ranges
Unit
Direction
Address Range
Time Slot Range
IOM-2
Receive
Transmit
0x8000..0x803F
0x8040..0x807F
0..63
0..63
IOM-2000
Receive
Transmit
0x6000..0x607F
0x6080..0x80FF
0..127
0..127
PCM
Receive
Transmit
0xA000..0xA07F
0xA080..0xA0FF
0..127
0..127
11.12.1
Switching Commands
The following commands are sent from the µP to the DELIC:
11.12.1.1 8-bit Connect Command (0x17)
This command creates or overwrites a connection between two time slots.
Parameter:
– Amount of following entries
For every entry:
–
–
–
–
–
Connection Identifier
Source unit
Source TS
Destination unit
Destination TS
Preliminary Data Sheet
11-50
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MGEN High)
µP-write
bit
4
7
SIZE3..0
6
5
Address:
43H
3
2
1
0
(SIZE3)
SIZE2
SIZE1
SIZE0
Amount of following entries within MDT0..7(15) (range: 1..4(8))
For every entry (four bytes per entry):
Mailbox Register (MDT[x] Low)
µP-write
bit
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
3
2
1
0
SIT2
SIT1
SIT0
ID7..0
Connection Identification
Mailbox Register (MDT[x] High)
µP-write
bit
SIT2..0
7
6
5
4
DIT2
DIT1
DIT0
Source Interface Type
001 = IOM-2
010 = IOM-2000
100 = PCM
DIT2..0
Destination Interface Type
001 = IOM-2
010 = IOM-2000
100 = PCM
Preliminary Data Sheet
11-51
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
Mailbox Register (MDT[x+1] Low)
bit
µP-write
7
6
5
4
3
2
1
0
STSN7
STSN6
STSN5
STSN4
STSN3
STSN2
STSN1
STSN0
STSN7..0 Source Time Slot Number
Mailbox Register (MDT[x+1] High)
bit
µP-write
7
6
5
4
3
2
1
0
DTSN7
DTSN6
DTSN5
DTSN4
DTSN3
DTSN2
DTSN1
DTSN0
DTSN7..0 Destination Time Slot Number
Note: Values for x are 0, 2, 4, 6, (8, 10, 12, 14)
11.12.1.2 8-bit Disconnect Command (0x18)
This command deactivates a connection between two time slots.
Parameter:
– Amount of following entries
For every entry:
– Connection Identifier
Mailbox Register (MGEN High)
µP-write
bit
5
4
3
2
1
0
(SIZE5)
SIZE4
SIZE3
SIZE2
SIZE1
SIZE0
SIZE5..0
7
6
Address:
43H
Amount of following bytes within MDT0..7(15) (range: 1..16(32))
Preliminary Data Sheet
11-52
2003-08
DELIC
PEB 20571
Mailbox Protocol Description
For every entry (one byte per entry):
Mailbox Register (MDT0..7(15))
µP-write
bit
ID7..0
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Connection Identification
Preliminary Data Sheet
11-53
2003-08
DELIC
Index
12
Index
Write Program Memory Command 11-13
Write Register Command 11-16
A
Applications
1-7
D
B
Block Diagram 4-2
Block Diagram of the DELIC-LC
Boot Strap Pin Setting 4-41
Differences DELIC-LC - DELIC-PB
F
1-2
Features
DELIC-LC
DELIC-PB
C
Commands
8-bit Connect Command 11-50
8-bit Disconnect Command 1152
Activation/Deactivation
Command 11-41
Finish Boot Command 11-13
Finish Initialization Command
11-24
GHDLC Configuration Command
11-22
IOM-2000 Delay Measurement
Command 11-21
IOM-2000 VIP Channel Configuration Command 11-22
Monitor Reset Command 11-30
Read Register Command 11-17
Reset Command 11-40, 11-46
Search On Command 11-29
Search Reset Command 11-30
Start Boot Command 11-13
Transmit Command 11-30, 1141, 11-47
Transmit
Continuous
Command 11-30, 11-41, 11-48
Transmit&Receive/Receive Only
Command 11-30
Write C/I Value Command 1127, 11-38
Write Data Memory Command
11-14
Preliminary Data Sheet
4-1
1-4
1-4
I
Indications
Change Detected Indication 1127, 11-38
Error Indication
11-15, 11-42,
11-48
Fatal Error Indication 11-48
Finish VIP Channel Configuration
Indication 11-26
Firmware Version Indication 1115
IOM-2000 Delay Indication 1125
IOM-2000 Far-end Code Violation Indication 11-24
Monitor Active Indication 11-32
Read Register Indication 11-18
Receive Continuous Indication
11-31, 11-44, 11-49
Receive Indication
11-31, 1144, 11-49
Start Loading Data RAM Indication 11-15
Start Loading Program RAM Indication 11-15
Transfer Ready Indication
1131
Transmit Abort Indication 11-32
Transmit Ready Indication 1143, 11-49
Interfaces
I-1
2003-08
DELIC
Index
µP Interface 3-24
IOM®-2 Interface 3-23
IOM-2000 3-2
Overview 3-1
Interrupts 3-26
Introduction 1-1
IOM-2000
Command and Status Interface
Data Interface 4-11
Framing Bits 4-6
IOM-2000 Frame Structure 3-3
IOMU
Overview of Features 4-14
4-7
J
JTAG Test Interface
3-27
L
Logic Symbol
1-6
P
Pin Definitions 2-3, 2-15
Pin Diagram 2-1, 2-2
Principle Block Diagram of the DELIC-PB
1-3
S
S/T State Machine 3-14
Strap Pin Definitions 2-28
Subscriber Address 11-4
T
TRANSIU
Initialization 4-3
Overview of Features
4-3
U
UPN State Machine
3-9
V
VIP
Initialization
Preliminary Data Sheet
4-4
12-2
2003-08
DELIC
Glossary
13
Glossary
AHV-SLIC
PEB 4165
High voltage part of SLIC
CMOS
Complementary Metal Oxide Semiconductor
CO
Central Office
CODEC
Coder Decoder
DC
Direct Current
DECT
Digital European Cordless Telecommunication
DELIC
DSP Embedded Line and Port Interface Controller
(PEB 20570, PEB 20571)
DSL
Digital Subscriber Line
DSP
Digital signal processor
HDLC
High-level Data Link Control
IEEE
Institute of Electrical and Electronic Engineers
INFO
U- and S-interface signal as specified by ANSI/ETSI
I/O
Input/Output
IOM-2
ISDN-Oriented Modular 2nd generation
IOM-2000
Proprietary ISDN inferface for S/T and UP
ISDN
Integrated services Digital Network
ITU
International Telecommunications Union
MUBIC
PEB22521
MDSL transceiver
MuPP
PEB 31665
16-channel CODEC digital front end part
µP
Micro Processor
OCTAT-P
OCTAl Transceiver for UPN-Interfaces (PEB 2096)
LT-S
Line Termination-Subscriber
LT-T
Line Termination-Trunk
PLL
Phase-Locked Loop
PBX
Private Branch Exchange
QUAD-U
PEB 2491
4-channel U-transceiver
Preliminary Data Sheet
13-1
2003-08
DELIC
Glossary
QAP
PEB 3465
Equivalent 4-channel analog front end part for MuPP
QUAT-S
QUAdrupleTransceiver for S/T-Interface (PEB 2084)
SLICOFI-2
PEB 3265
Dual channel CODEC + low voltage part of SLIC
S/T
Two-wire pair ISDN interface
TAP
Test Access Port
TBD
To Be Defined
Preliminary Data Sheet
13-2
2003-08