FAIRCHILD SCAN182374ASSC

Revised August 2000
SCAN182374A
D-Type Flip-Flop with 25Ω Series Resistor Outputs
General Description
Features
The SCAN182374A is a high performance BiCMOS D-type
flip-flop featuring separate D-type inputs organized into
dual 9-bit bytes with byte-oriented clock and output enable
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan
test logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
■ IEEE 1149.1 (JTAG) Compliant
■ High performance BiCMOS technology
■ 25Ω series resistor outputs eliminate need for external
terminating resistors
■ Buffered positive edge-triggered clock
■ 3-STATE outputs for bus-oriented applications
■ 25 mil pitch SSOP (Shrink Small Outline Package)
■ Includes CLAMP, IDCODE and HIGHZ instructions
■ Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
■ Power up 3-STATE for hot insert
■ Member of Fairchild’s SCAN Products
Ordering Code:
Order Number
Package Number
SCAN182374ASSC
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
AI(0–8), BI(0–8)
Data Inputs
ACP, BCP
Clock Pulse Inputs
AOE1, BOE1
3-STATE Output Enable Inputs
AO(0–8), BO(0–8)
3-STATE Outputs
Truth Tables
Inputs
ACP
AOE1
(Note 1)
AI(0–8)
AO(0–8)
H
X
Z
L
L
L
L
H
H
X
Inputs
BCP
BOE1
(Note 1)
BI(0–8)
BO(0–8)
H
X
Z
L
L
L
L
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= L-to-H Transition
Note 1: Inactive-to-active transition must occur to enable outputs upon
power-up.
© 2000 Fairchild Semiconductor Corporation
DS011545
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SCAN182374A D-Type Flip-Flop with 25Ω Series Resistor Outputs
January 1993
SCAN182374A
Functional Description
LOW-to-HIGH Clock (ACP or BCP) transition. With the
Output Enable (AOE1 or BOE1) LOW, the contents of the
nine flip-flops are available at the outputs. When the Output
Enable is HIGH, the outputs go to the high impedance
state. Operation of the Output Enable input does not affect
the state of the flip-flops.
The SCAN182374A consists of two sets of nine edge-triggered flip-flops with individual D-type inputs and 3-STATE
true outputs. The buffered clock and buffered Output
Enable pins are common to all flip-flops. Each set of the
nine flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
Byte-A
Note: BSR stands for Boundary Scan Register
Tap Controller
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SCAN182374A
Block Diagrams
(Continued)
Byte-B
Note: BSR stands for BOUNDARY-SCAN Register
Description of BOUNDARY-SCAN Circuitry
The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required
to shift in the 8-bit instruction for SAMPLE/PRELOAD. The
sequence of: CAPTURE-IR → EXIT1-IR → UPDATE-IR
will update the SAMPLE/PRELOAD instruction. For more
information refer to the section on instruction definitions.
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high.
Instruction Register Scan Chain Definition
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
MSB → LSB
Instruction Code
SCAN182374A Product IDCODE
(32-Bit Code per IEEE 1149.1)
Version Entity
Per
Number
0000
MSB
111111 0000000111 00000001111
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGH-Z
by 1149.1
01000001
SAMPLE-IN
1
01000010
SAMPLE-OUT
00100010
EXTEST-OUT
Manufacturer Required
ID
Instruction
00000000
LSB
3
10101010
IDCODE
11111111
BYPASS
All Other
BYPASS
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SCAN182374A
Description of BOUNDARY-SCAN Circuitry
Scan Cell TYPE1
Scan Cell TYPE2
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(Continued)
SCAN182374A
Description of BOUNDARY-SCAN Circuitry
(Continued)
BOUNDARY-SCAN Register
SCAN182374A Scan Chain Definition (42 Bits in Length)
5
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SCAN182374A
Description of BOUNDARY-SCAN Circuitry
(Continued)
Input BOUNDARY-SCAN Register
Scan Chain Definition (22 Bits in Length)
When Sample In is Active
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SCAN182374A
Description of BOUNDARY-SCAN Circuitry
(Continued)
Output BOUNDARY-SCAN Register
Scan Chain Definition (20 Bits in Length)
When Sample Out and EXTEST Out are Active
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SCAN182374A
Description of BOUNDARY-SCAN Circuitry
(Continued)
BOUNDARY-SCAN Register Definition Index
Bit No.
Pin Name
Pin No.
Pin Type
41
AOE1
3
Input
40
ACP
54
39
AOE
38
BOE1
26
37
BCP
31
36
BOE
Scan Cell Type
TYPE1
Input
TYPE1
Internal
TYPE2
Input
TYPE1
Input
TYPE1
Internal
TYPE2
35
AI0
55
Input
TYPE1
34
AI1
53
Input
TYPE1
33
AI2
52
Input
TYPE1
32
AI3
50
Input
TYPE1
31
AI4
49
Input
TYPE1
30
AI5
47
Input
TYPE1
29
AI6
46
Input
TYPE1
28
AI7
44
Input
TYPE1
27
AI8
43
Input
TYPE1
26
BI0
42
Input
TYPE1
25
BI1
41
Input
TYPE1
24
BI2
39
Input
TYPE1
23
BI3
38
Input
TYPE1
22
BI4
36
Input
TYPE1
21
BI5
35
Input
TYPE1
20
BI6
33
Input
TYPE1
19
BI7
32
Input
TYPE1
18
BI8
30
Input
TYPE1
17
AO0
2
Output
TYPE2
16
AO1
4
Output
TYPE2
15
AO2
5
Output
TYPE2
14
AO3
7
Output
TYPE2
13
AO4
8
Output
TYPE2
12
AO5
10
Output
TYPE2
11
AO6
11
Output
TYPE2
10
AO7
13
Output
TYPE2
9
AO8
14
Output
TYPE2
8
BO0
15
Output
TYPE2
7
BO1
16
Output
TYPE2
6
BO2
18
Output
TYPE2
5
BO3
19
Output
TYPE2
4
BO4
21
Output
TYPE2
3
BO5
22
Output
TYPE2
2
BO6
24
Output
TYPE2
1
BO7
25
Output
TYPE2
0
BO8
27
Output
TYPE2
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Control
Signals
A–in
B–in
A–out
B–out
Recommended Operating
Conditions
Storage Temperature
−65°C to +150 °C
Ambient Temperature under Bias
−55°C to +125 °C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150 °C
Supply Voltage
VCC Pin Potential to Ground Pin
−0.5V to +7.0V
Input Voltage (Note 3)
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
−40°C to +85°C
+4.5V to +5.5V
(∆V/∆t)
Minimum Input Edge Rate
Data Input
50 mV/ns
Enable Input
20 mV/ns
Voltage Applied to Any Output
in the Disabled or
−0.5V to +5.5V
Power-Off State
−0.5V to VCC
in the HIGH State
Current Applied to Output
in LOW State (Max)
Twice the Rated IOL (mA)
−500 mA
DC Latchup Source Current
Over Voltage Latchup (I/O)
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
10V
ESD (HBM) Min.
2000V
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
VCC
Symbol
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VCD
Input Clamp Diode Voltage
Min
VOH
Output HIGH Voltage
Min
2.5
V
IOH = −3 mA
Min
2.0
V
IOH = −32 mA
VOL
Output LOW Voltage
IIH
Input HIGH Current
Min
Typ
Max
2.0
All Others
TMS, TDI Inputs
Units
Conditions
V
Recognized HIGH Signal
0.8
V
Recognized LOW Signal
−1.2
V
IIN = −18 mA
Min
0.8
V
IOL = 15 mA
Max
5
µA
VIN = 2.7V (Note 4)
Max
5
µA
VIN = VCC
Max
5
µA
VIN = VCC
IBVI
Input HIGH Current Breakdown Test
Max
7
µA
VIN = 7.0V
IBVIT
Input HIGH Current Breakdown Test (I/O)
Max
100
µA
VIN = 5.5V
IIL
Input LOW Current
Max
−5
µA
VIN = 0.5V (Note 4)
Max
−5
µA
VIN = 0.0V
Max
−385
µA
VIN = 0.0V
V
IID = 1.9 µA
All Others
TMS, TDI
VID
Input Leakage Test
0.0
4.75
IIH + IOZH
Output Leakage Current
Max
50
µA
VOUT = 2.7V
IIL + IOZL
Output Leakage Current
Max
−50
µA
VOUT = 0.5V
IOZH
Output Leakage Current
Max
50
µA
VOUT = 2.7V
IOZL
Output Leakage Current
Max
−50
µA
VOUT = 0.5V
IOS
Output Short-Circuit Current
Max
−275
mA
VOUT = 0.0V
ICEX
Output HIGH Leakage Current
Max
50
µA
VOUT = VCC
IZZ
Bus Drainage Test
0.0
100
µA
All Other Pins Grounded
−100
VOUT = 5.5V
All Others Grounded
ICCH
ICCL
ICCZ
ICCT
ICCD
Power Supply Current
Power Supply Current
Power Supply Current
Additional ICC/Input
Dynamic ICC
Max
250
µA
VOUT = VCC; TDI, TMS = VCC
Max
1.0
mA
VOUT = VCC; TDI, TMS = GND
Max
65
mA
VOUT = LOW; TDI, TMS = VCC
Max
65.8
mA
VOUT = LOW; TDI, TMS = GND
Max
250
µA
TDI, TMS = VCC
Max
1.0
mA
TDI, TMS = GND
VIN = VCC − 2.1V
All Other Inputs
Max
2.9
mA
TDI, TMS Inputs
Max
3
mA
VIN = VCC − 2.1V
No Load
Max
0.2
mA/
Outputs Open
MHz
One Bit Toggling, 50% Duty Cycle
Note 4: Guaranteed not tested.
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SCAN182374A
Absolute Maximum Ratings(Note 2)
SCAN182374A
AC Electrical Characteristics
Normal Operation
TA = −40°C to +85°C
VCC
Symbol
Parameter
(Note 5)
tPLH
Propagation Delay
tPHL
CP to Q
tPLZ
Disable Time
5.0
5.0
tPHZ
tPZL
CL = 50 pF
(V)
Enable Time
5.0
tPZH
Units
Min
Typ
Max
1.4
4.6
6.1
2.1
4.9
6.8
1.9
4.6
8.0
1.8
4.8
8.7
2.0
6.7
9.4
1.4
6.0
8.2
ns
ns
ns
Note 5: Voltage Range 5.0V ± 0.5V
AC Operating Requirements
Normal Operation
VCC
Symbol
tS
Parameter
Setup Time, H or L
Data to CP
tH
Hold Time, H or L
CP to Data
tW
CP Pulse Width
fMAX
Maximum ACP/BCP
Clock Frequency
TA = −40°C to +85°C
(V)
CL = 50 pF
(Note 6)
Guaranteed Minimum
5.0
2.8
ns
5.0
2.4
ns
5.0
0.0
ns
5.0
50
MHz
Units
Note 6: Voltage Range is 5.0V ± 0.5V.
AC Electrical Characteristics
Scan Test Operation
TA = −40°C to +85°C
VCC
Symbol
Parameter
(Note 7)
tPLH
Propagation Delay
tPHL
TCK to TDO
tPLZ
Disable Time
tPHZ
TCK to TDO
tPZL
Enable Time
tPZH
TCK to TDO
tPLH
Propagation Delay
tPHL
TCK to Data Out during Update-DR State
tPLH
Propagation Delay
tPHL
TCK to Data Out during Update-IR State
tPLH
Propagation Delay
tPHL
TCK to Data Out during Test Logic Reset State
tPLZ
Disable Time
tPHZ
TCK to Data Out during Update-DR State
tPLZ
Disable Time
tPHZ
TCK to Data Out during Update-IR State
tPLZ
Disable Time
tPHZ
TCK to Data Out during Test Logic Reset State
tPZL
Enable Time
tPZH
TCK to Data Out during Update-DR State
tPZL
Enable Time
tPZH
TCK to Data Out during Update-IR State
tPZL
Enable Time
tPZH
TCK to Data Out during Test Logic Reset State
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Note 7: Voltage Range 5.0V ± 0.5V
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CL = 50 pF
(V)
10
Min
Typ
Units
Max
2.9
5.8
9.5
4.0
7.3
11.5
1.9
5.6
10.0
3.0
7.1
12.1
4.4
8.4
13.2
2.7
6.4
10.9
3.4
6.5
10.5
4.3
8.1
12.7
3.9
7.8
12.8
4.7
9.1
14.5
4.7
9.5
15.6
5.6
10.9
17.4
3.2
7.8
13.6
3.9
8.5
14.2
3.2
8.6
15.0
3.8
9.3
15.6
4.2
10.2
18.0
5.0
11.0
18.5
5.0
9.6
15.3
3.7
7.7
13.0
5.3
10.8
17.4
4.0
9.0
15.1
6.2
12.6
20.4
4.7
10.7
18.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Scan Test Operation
TA = −40°C to +85°C
VCC
Symbol
(V)
CL = 50 pF
(Note 8)
Guaranteed Minimum
5.0
2.7
ns
5.0
3.1
ns
5.0
5.0
ns
5.0
1.8
ns
5.0
3.6
ns
5.0
2.1
ns
5.0
3.4
ns
5.0
1.8
ns
5.0
8.7
ns
5.0
1.8
ns
5.0
6.4
ns
5.0
3.2
ns
Parameter
Setup Time
tS
Data to TCK (Note 9)
tH
Hold Time
Data to TCK (Note 9)
Setup Time, H or L
tS
AOE1, BOE1 to TCK (Note 10)
Hold Time, H or L
tH
TCK to AOE1, BOE1 (Note 10)
tS
Setup Time, H or L
Internal AOE, BOE to TCK (Note 11)
Hold Time, H or L
tH
TCK to Internal AOE, BOE (Note 11)
tS
Setup Time
ACP, BCP (Note 12) to TCK
tH
Hold Time
TCK to ACP, BCP (Note 12)
Setup Time, H or L
tS
TMS to TCK
tH
Hold Time, H or L
TCK to TMS
tS
Setup Time, H or L
TDI to TCK
Hold Time, H or L
tH
TCK to TDI
tW
Pulse Width TCK
H
8.2
5.0
L
Units
ns
11.2
fMAX
Maximum TCK Clock Frequency
5.0
50
tPU
Wait Time, Power Up to TCK
5.0
100
ns
tDN
Power Down Delay
0.0
100
ms
MHz
Note 8: Voltage Range 5.0V ± 0.5V
Note 9: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0–8, 9–17, 18–26 and 27–35.
Note 10: Timing pertains to BSR 38 and 41 only.
Note 11: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 12: Timing pertains to BSR 37 and 40 only.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Capacitance
TA = 25°C
Symbol
CIN
Parameter
Input Capacitance
COUT (Note 13) Output Capacitance
Typ
Units
5.8
pF
VCC = 0.0V
Conditions
13.8
pF
VCC = 5.0V
Note 13: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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SCAN182374A
AC Operating Requirements
SCAN182374A D-Type Flip-Flop with 25Ω Series Resistor Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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