Revised August 2000 SCAN182373A Transparent Latch with 25Ω Series Resistor Outputs General Description Features The SCAN182373A is a high performance BiCMOS transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture with the incorporation of the defined boundaryscan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). ■ IEEE 1149.1 (JTAG) Compliant ■ High performance BiCMOS technology ■ 25Ω series resistor outputs eliminate need for external terminating resistors ■ Buffered active-low latch enable ■ 3-STATE outputs for bus-oriented applications ■ 25 mil pitch SSOP (Shrink Small Outline Package) ■ Includes CLAMP, IDCODE and HIGHZ instructions ■ Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT ■ Power up 3-STATE for hot insert ■ Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number SCAN182373ASSC MS56A Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 2000 Fairchild Semiconductor Corporation DS011544 Description AI(0–8), BI(0–8) Data Inputs ALE, BLE Latch Enable Inputs AOE1, BOE1 3-STATE Output Enable Inputs AO(0–8), BO(0–8) 3-STATE Latch Outputs www.fairchildsemi.com SCAN182373A Transparent Latch with 25Ω Series Resistor Outputs January 1993 SCAN182373A Truth Tables Inputs Inputs AO (0–8) ALE †AOE1 AI (0–8) BO (0–8) BLE †BOE1 BI (0–8) X H X Z X H X H L L L H L L L H L H H H L H H L L X AO0 L L X BO0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Z AO0 = Previous AO before H-to-L transition of ALE BO0 = Previous BO before H-to-L transition of BLE † = Inactive-to-active transition must occur to enable outputs upon power-up. Functional Description the inputs a set-up time preceding the HIGH-to-LOW transition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable (AOE1 or BOE1) input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches. The SCAN182373A consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable (ALE or BLE) input is HIGH, data on the inputs (AI(0–8) or BI(0–8)) enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 SCAN182373A Block Diagrams Byte-A Tap Controller Byte-B Note: BSR stands for Boundary Scan Register. 3 www.fairchildsemi.com SCAN182373A Description of BOUNDARY-SCAN Circuitry The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR → EXIT1-IR → UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE 1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. Instruction Register Scan Chain Definition The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 MSB → LSB Instruction Code SCAN182373A Product IDCODE (32-Bit Code per IEEE 1149.1) Version Entity Part Number 0000 Manufacturer Required by ID 111111 0000001000 00000001111 MSB 1149.1 1 LSB Scan Cell TYPE1 Scan Cell TYPE2 www.fairchildsemi.com 4 Instruction 00000000 EXTEST 10000001 SAMPLE/PRELOAD 10000010 CLAMP 00000011 HIGH-Z 01000001 SAMPLE-IN 01000010 SAMPLE-OUT 00100010 EXTEST-OUT 10101010 IDCODE 11111111 BYPASS All Others BYPASS SCAN182373A BOUNDARY-SCAN Register Scan Chain Definition (42 Bits in Length) 5 www.fairchildsemi.com SCAN182373A Input BOUNDARY-SCAN Register Scan Chain Definition (22 Bits in Length) When Sample In is Active www.fairchildsemi.com 6 SCAN182373A Output BOUNDARY-SCAN Register Scan Chain Definition (20 Bits in Length) When Sample Out and Extent Out are Active 7 www.fairchildsemi.com SCAN182373A BOUNDARY-SCAN Register Definition Index Bit No. Pin Name Pin No. Pin Type 41 AOE1 3 Input 40 ALE 54 39 AOE 38 BOE1 26 37 BLE 31 36 BOE Scan Cell Type TYPE1 Input TYPE1 Internal TYPE2 Input TYPE1 Input TYPE1 Internal TYPE2 35 AI0 55 Input TYPE1 34 AI1 53 Input TYPE1 33 AI2 52 Input TYPE1 32 AI3 50 Input TYPE1 31 AI4 49 Input TYPE1 30 AI5 47 Input TYPE1 29 AI6 46 Input TYPE1 28 AI7 44 Input TYPE1 27 AI8 43 Input TYPE1 26 BI0 42 Input TYPE1 25 BI1 41 Input TYPE1 24 BI2 39 Input TYPE1 23 BI3 38 Input TYPE1 22 BI4 36 Input TYPE1 21 BI5 35 Input TYPE1 20 BI6 33 Input TYPE1 19 BI7 32 Input TYPE1 18 BI8 30 Input TYPE1 17 AO0 2 Output TYPE2 16 AO1 4 Output TYPE2 15 AO2 5 Output TYPE2 14 AO3 7 Output TYPE2 13 AO4 8 Output TYPE2 12 AO5 10 Output TYPE2 11 AO6 11 Output TYPE2 10 AO7 13 Output TYPE2 9 AO8 14 Output TYPE2 8 BO0 15 Output TYPE2 7 BO1 16 Output TYPE2 6 BO2 18 Output TYPE2 5 BO3 19 Output TYPE2 4 BO4 21 Output TYPE2 3 BO5 22 Output TYPE2 2 BO6 24 Output TYPE2 1 BO7 25 Output TYPE2 0 BO8 27 Output TYPE2 www.fairchildsemi.com 8 Control Signals A-in B-in A-out B-out Recommended Operating Conditions Storage Temperature −65°C to +150 °C Ambient Temperature under Bias −55°C to +125 °C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150 °C Supply Voltage VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V (∆V/∆t) Minimum Input Edge Rate Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output −0.5V to +5.5V in Disabled or Power-Off State −0.5V to VCC in the HIGH State Current Applied to Output in LOW State (Max) Twice the Rated IOL (mA) −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) 10V ESD (HBM) Min Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. 2000V Note 2: Either voltage limit of current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VCC Parameter Min Typ Max VIL Input LOW Voltage VCD Input Clamp Diode Voltage Output Min VOH HIGH Voltage Min 2.5 V IOH = −3 mA Min 2.0 V IOH = −32 mA VOL Output LOW Voltage Input HIGH Current All Others TMS, TDI V Conditions Input HIGH Voltage IIH 2.0 Units VIH Recognized HIGH Signal 0.8 V Recognized LOW Signal −1.2 V IIN = −18 mA Min 0.8 V IOL = 15 mA Max 5 µA VIN = 2.7V (Note 3) Max 5 µA VIN = VCC Max 5 µA VIN = VCC IBVI Input HIGH Current Breakdown Test Max 7 µA VIN = 7.0V IBVIT Input HIGH Current Breakdown Test (I/O) Max 100 µA VIN = 5.5V IIL Input LOW Current Max −5 µA VIN = 0.5V (Note 3) Max −5 µA VIN = 0.0V Max −385 µA VIN = 0.0V V IID = 1.9 µA All Others TMS, TDI VID Input Leakage Test 0.0 IIH + IOZH Output Leakage Current Max 50 IIL + LOZL Output Leakage Current Max −50 IOZH Output Leakage Current Max 50 µA IOZL Output Leakage Current Max −50 µA VOUT = 0.5V IOS Output Short-Circuit Current Max −275 mA VOUT = 0.0V ICEX Output HIGH Leakage Current Max 50 µA VOUT = VCC IZZ Bus Drainage Test 0.0 100 µA 4.75 All Other Pins Grounded −100 µA VOUT = 2.7V VOUT = 0.5V VOUT = 2.7V VOUT = 5.5V All Others Grounded ICCH ICCL ICCZ ICCT ICCD Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC Max 250 µA VOUT = VCC; TDI, TMS = VCC Max 1.0 mA VOUT = VCC; TDI, TMS = GND Max 65 mA VOUT = LOW; TDI, TMS = VCC Max 65.8 mA VOUT = LOW; TDI, TMS = GND Max 250 µA TDI, TMS = VCC Max 1.0 mA TDI, TMS = GND VIN = VCC −2.1V All Other Inputs Max 2.9 mA TDI, TMS Inputs Max 3 mA VIN = VCC −2.1V No Load Max 0.2 mA/ Outputs Open MHz One Bit Toggling, 50% Duty Cycle Note 3: Guaranteed not tested. 9 www.fairchildsemi.com SCAN182373A Absolute Maximum Ratings(Note 1) SCAN182373A AC Electrical Characteristics Normal Operation: TA = −40°C to +85°C VCC Symbol Parameter tPLH Propagation Delay tPHL D to Q tPLH Propagation Delay tPHL LE to Q tPLZ Disable Time CL = 50 pF (V) Min Typ Max 5.0 1.2 3.7 6.5 2.0 4.5 7.4 1.3 4.1 7.4 1.8 4.5 7.3 1.6 4.9 9.0 1.8 6.0 10.7 1.6 6.0 9.5 1.0 5.0 9.3 5.0 5.0 tPHZ tPZL Enable Time Units (Note 4) 5.0 tPZH ns ns ns ns Note 4: Voltage Range 5.0V ± 0.5V AC Operating Requirements Normal Operation: TA = −40°C to +85°C VCC Symbol tS (V) CL = 50 pF (Note 5) Guaranteed Minimum 5.0 1.7 ns 5.0 1.6 ns 5.0 2.3 ns Parameter Setup Time, H or L Units Data to LE tH Hold Time, H or L LE to Data tW LE Pulse Width Note 5: Voltage Range 5.0V ±0.5V AC Electrical Characteristics Scan Test Operation: TA = −40°C to +85°C VCC Symbol Parameter tPLH Propagation Delay tPHL TCK to TDO tPLZ Disable Time tPHZ TCK to TDO tPZL Enable Time tPZH TCK to TDO tPLH Propagation Delay tPHL TCK to Data Out during Update-DR State CL = 50 pF (V) Min 5.0 3.6 5.8 8.6 4.8 7.4 10.6 5.0 5.0 Typ Units (Note 6) Max 2.7 5.6 9.0 4.0 7.1 10.9 5.2 8.6 12.5 3.6 6.6 10.1 3.9 6.4 9.5 5.0 5.1 8.0 11.6 tPLH Propagation Delay 4.7 7.7 11.3 tPHL TCK to Data Out during Update-IR State 5.0 5.7 9.1 13.1 5.0 5.5 9.2 13.6 6.7 10.7 15.6 tPLH Propagation Delay tPHL TCK to Data Out during Test Logic Reset State tPLZ Disable Time tPHZ TCK to Data Out during Update-DR State 4.1 7.7 12.1 5.0 4.7 8.4 12.7 tPLZ Disable Time 4.2 8.3 13.5 tPHZ TCK to Data Out during Update-IR State 5.0 4.7 9.0 14.0 5.0 5.5 10.1 15.6 6.3 10.8 16.2 tPLZ Disable Time tPHZ TCK to Data Out during Test Logic Reset State tPZL Enable Time tPZH TCK to Data Out during Update-DR State 5.8 9.6 14.2 5.0 4.3 7.7 11.7 tPZL Enable Time 6.1 11.0 16.0 tPZH TCK to Data Out during Update-IR State 5.0 4.7 9.0 13.7 tPZL Enable Time 5.0 7.3 12.5 18.3 tPZH TCK to Data Out during Test Logic Reset State 5.8 10.5 15.8 Note 6: Voltage Range 5.0V ± 0.5V www.fairchildsemi.com 10 ns ns ns ns ns ns ns ns ns ns ns ns Scan Test Operation: VCC Symbol tS CL = 50 pF (Note 7) Guaranteed Minimum 5.0 2.7 ns 5.0 2.4 ns 5.0 5.1 ns 5.0 1.8 ns 5.0 3.5 ns 5.0 1.8 ns 5.0 5.1 ns 5.0 1.8 ns 5.0 7.9 ns 5.0 1.8 ns 5.0 6.0 ns 5.0 3.0 ns Setup Time, Data to TCK (Note 8) tH Hold Time, Data to TCK (Note 8) tS Setup Time, H or L AOE 1, BOE 1 to TCK (Note 9) tH Hold Time, H or L TCK to AOE 1, BOE 1 (Note 9) tS Setup Time, H or L Internal AOE, BOE, to TCK (Note 10) tH TA = −40°C to +85°C (V) Parameter Units Hold Time, H or L TCK to Internal AOE, BOE (Note 10) tS Setup Time ALE, BLE (Note 11) to TCK tH Hold Time TCK to ALE, BLE (Note 11) tS Setup Time, H or L TMS to TCK tH Hold Time, H or L TCK to TMS tS Setup Time, H or L TDI to TCK tH Hold Time, H or L TCK to TDI tW Pulse Width TCK H 5.0 L 10.3 ns 10.3 fMAX Maximum TCK Clock Frequency 5.0 50 tPU Wait Time, Power Up to TCK 5.0 100 MHz ns tDN Power Down Delay 0.0 100 ms Note 7: Voltage Range 5.0V ± 0.5V. Note 8: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35. Note 9: Timing pertains to BSR 38 and 41 only. Note 10: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. Note 11: Timing pertains to BSR 37 and 40 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Capacitance Typ Units Conditions, TA = 25°C CIN Input Capacitance 5.8 pF VCC = 0.0V COUT Output Capacitance (Note 12) 13.8 pF VCC = 5.0V Symbol Parameter Note 12: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012 11 www.fairchildsemi.com SCAN182373A AC Operating Requirements SCAN182373A Transparent Latch with 25Ω Series Resistor Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 12