FAIRCHILD 74ACTQ573SJ

Revised November 1999
74ACQ573 • 74ACTQ573
Quiet Series Octal Latch with 3-STATE Outputs
General Description
Features
The ACQ/ACTQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common
Output Enable (OE) inputs. The ACQ/ACTQ573 is functionally identical to the ACQ/ACTQ373 but with inputs and
outputs on opposite sides of the package. The ACQ/ACTQ
utilizes Fairchild’s Quiet Series technology to guarantee
quiet output switching and improved dynamic threshold
performance. FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split
ground bus for superior performance.
■ ICC and IOZ reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
■ Outputs source/sink 24 mA
Ordering Code:
Order Number
74ACQ573SC
74ACQ573SJ
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ573MTC
MTC20
74ACQ573PC
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ573QSC
MQA20
74ACTQ573PC
N20A
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
Description
Data Inputs
LE
Latch Enable Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Latch Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation
© 1999 Fairchild Semiconductor Corporation
DS010633
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74ACQ573 • 74ACTQ573 Quiet Series Octal Latch with 3-STATE Outputs
January 1990
74ACQ573 • 74ACTQ573
Functional Description
Truth Table
The ACQ/ACTQ573 contains eight D-type latches with 3STATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will
change state each time its D-type input changes. When LE
is LOW the latches store the information that was present
on the D-type inputs at setup time preceding the HIGH-toLOW transition of LE. The 3-STATE buffers are controlled
by the Output Enable (OE) input. When OE is LOW, the
buffers are enabled. When OE is HIGH the buffers are in
the high impedance mode but this does not interfere with
entering new data into the latches.
Inputs
Outputs
OE
LE
D
On
L
H
H
H
L
H
L
L
L
L
X
O0
H
X
X
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
Supply Voltage (VCC)
−0.5V to VCC + 0.5V
DC Input Voltage (VI)
VO = VCC + 0.5V
+20 mA
0V to VCC
−40°C to +85°C
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
DC Output Source
VIN from 30% to 70% of VCC
±50 mA
VCC @ 3.0V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate ∆V/∆t
DC VCC or Ground Current
±50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
0V to VCC
Operating Temperature (TA)
−0.5V to VCC + 0.5V
or Sink Current (IO)
4.5V to 5.5V
Output Voltage (VO)
−20 mA
DC Output Voltage (VO)
2.0V to 6.0V
ACTQ
Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
ACQ
ACTQ Devices
−65°C to +150°C
VIN from 0.8V to 2.0V
DC Latchup Source
VCC @ 4.5V, 5.5V
±300 mA
or Sink Current
Junction Temperature (TJ
PDIP
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
140°C
DC Electrical Characteristics for ACQ
Symbol
VIH
Parameter
Minimum HIGH Level
Input Voltage
VIL
VOH
VCC
TA = +25°C
(V)
Typ
3.0
1.5
TA = −40°C to +85°C
Guaranteed Limits
2.1
2.1
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
Units
Conditions
VOUT = 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
V
IOUT = −50 µA
VIN = VIL or VIH
VOL
IOH = −12 mA
V
IOH = −24 mA
IOH = −24 mA (Note 2)
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
± 0.1
± 1.0
µA
VI = VCC, GND
75
mA
VOLD = 1.65 VMax
V
IOUT = 50 µA
VIN = VIL or VIH
IOL = 12 mA
V
IOL = 24 mA
IOL = 24 mA (Note 2)
IIN (Note 4)
Maximum Input Leakage Current
5.5
IOLD
Minimum Dynamic
5.5
IOHD
Output Current (Note 3)
5.5
−75
mA
VOHD = 3.85 VMin
ICC (Note 4) Maximum Quiescent Supply Current
5.5
4.0
40.0
µA
VIN = VCC or GND
5.5
±0.25
±2.5
µA
VI = VCC, GND
IOZ
VI (OE) = VIL, VIH
Maximum 3-STATE
Leakage Current
VO = VCC, GND
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
3
V
Figure 1, Figure 2
(Note 5)(Note 6)
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74ACQ573 • 74ACTQ573
Absolute Maximum Ratings(Note 1)
74ACQ573 • 74ACTQ573
DC Electrical Characteristics for ACQ
Symbol
VOLV
Parameter
Quiet Output
Minimum Dynamic VOL
VIHD
Minimum HIGH Level
Dynamic Input Voltage
VILD
Maximum LOW Level
Dynamic Input Voltage
VCC
(Continued)
TA = +25°C
TA = −40°C to +85°C
Units
Conditions
(V)
Typ
Guaranteed Limits
5.0
−0.6
−1.2
V
5.0
3.1
3.5
V
(Note 5)(Note 7)
5.0
1.9
1.5
V
(Note 5)(Note 7)
Figure 1, Figure 2
(Note 5)(Note 6)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. (n − 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
VIH
VIL
VOH
Parameter
VCC
(V)
TA = +25°C
Typ
TA = −40°C to +85°C
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
3.86
3.76
Units
V
V
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
V
IOH = −24 mA
VIN = VIL or VIH
4.5
5.5
VOL
IOH = −24 mA (Note 8)
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
±0.1
±1.0
µA
5.5
±0.25
±2.5
µA
1.5
mA
V
IOUT = 50 µA
V
IOL = 24 mA
VIN = VIL or VIH
IIN
Maximum Input
Leakage Current
IOZ
Maximum 3-STATE
Leakage Current
VI = VCC, GND
VI = VIL, VIH
VO = VCC, GND
VI = VCC − 2.1V
ICCT
Maximum ICC/Input
5.5
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 9)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent Supply Current
5.5
40.0
µA
VOLP
Quiet Output
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
VIHD
Minimum HIGH Level
Dynamic Input Voltage
VILD
Maximum LOW Level
Dynamic Input Voltage
0.6
IOL = 24 mA (Note 8)
4.0
VIN = VCC or GND
Figure 1, Figure 2
5.0
1.1
1.5
V
5.0
−0.6
−1.2
V
5.0
1.9
2.2
V
(Note 10)(Note 12)
5.0
1.2
0.8
V
(Note 10)(Note 12)
(Note 10)(Note 11)
Figure 1, Figure 2
(Note 10)(Note 11)
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: Plastic DIP package.
Note 11: Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND.
Note 12: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f =1 MHz.
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4
Symbol
Parameter
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 13)
Min
Typ
Max
Min
Max
tPHL
Propagation Delay
3.3
2.5
8.5
10.5
2.5
11.0
tPLH
Dn to On
5.0
1.5
5.5
7.0
1.5
7.5
tPLH
Propagation Delay
3.3
2.5
8.5
12.0
2.5
12.5
tPHL
LE to On
5.0
2.0
6.0
8.0
2.0
8.5
tPZL
Output Enable Time
3.3
2.5
8.5
13.0
2.5
13.5
5.0
1.5
6.0
8.5
1.5
9.0
3.3
1.0
9.0
14.5
1.0
15.0
5.0
1.0
6.0
9.5
1.0
10.0
tPZH
tPHZ
Output Disable Time
tPLZ
tOSHL
Output to Output Skew (Note 14)
3.3
1.0
1.5
1.5
tOSLH
Dn to On
5.0
0.5
1.0
1.0
ns
ns
ns
ns
ns
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements for ACQ
Symbol
VCC
TA = +25°C
(V)
CL = 50 pF
Parameter
(Note 15)
tS
tH
tW
Typ
TA = −40°C to +85°C
CL = 50 pF
Units
Guaranteed Minimum
Setup Time, HIGH or LOW
3.3
0
3.0
3.0
Dn to LE
5.0
0
3.0
3.0
Hold Time, HIGH or LOW
3.3
0
1.5
1.5
Dn to LE
5.0
0
1.5
1.5
LE Pulse Width, HIGH
3.3
2.0
4.0
4.0
5.0
2.0
4.0
4.0
ns
ns
ns
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
AC Electrical Characteristics for ACTQ
Symbol
Parameter
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 16)
Min
Typ
Max
Min
Max
5.0
2.0
6.5
7.5
2.0
8.0
ns
5.0
2.5
7.0
8.5
2.5
9.0
ns
tPHL
Propagation Delay
tPLH
Dnto On
tPLH
Propagation Delay
tPHL
LE to On
tPZL, tPZH
Output Enable Time
5.0
2.0
7.0
9.0
2.0
9.5
ns
tPHZ, tPLZ
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
tOSHL
Output to Output Skew (Note 17)
tOSLH
Dn to On
0.5
1.0
1.0
ns
5.0
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
5
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74ACQ573 • 74ACTQ573
AC Electrical Characteristics for ACQ
74ACQ573 • 74ACTQ573
AC Operating Requirements for ACTQ
Symbol
tS
Parameter
Setup Time, HIGH or LOW
Dn to LE
tH
Hold Time, HIGH or LOW
Dn to LE
LE Pulse Width, HIGH
tW
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Typ
Guaranteed Minimum
5.0
0
3.0
3.0
ns
5.0
0
1.5
1.5
ns
5.0
2.0
4.0
4.0
ns
Note 18: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
VCC = OPEN
CPD
Power Dissipation Capacitance
42.0
pF
VCC = 5.0V
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Units
(Note 18)
6
Conditions
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
• Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
VILD and VIHD:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are the correct voltage.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
• Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
Note 19: VOHV and VOLP are measured with respect to ground reference.
Note 20: Input pulses have the following characteristics: f = 1 MHz,
tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
7
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74ACQ573 • 74ACTQ573
FACT Noise Characteristics
74ACQ573 • 74ACTQ573
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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8
74ACQ573 • 74ACTQ573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
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74ACQ573 • 74ACTQ573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Package Number MQA20
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10
74ACQ573 • 74ACTQ573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
11
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74ACQ573 • 74ACTQ573 Quiet Series Octal Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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