Revised November 1999 74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The 74ACTQ541 is an octal buffer/line driver designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. ■ ICC and IOZ reduced by 50% This device is similar in function to the 74ACTQ244 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes this device especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density. ■ Guaranteed pin-to-pin skew AC performance The 74ACTQ541 utilizes FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to split ground bus for superior performance. ■ Guaranteed 4 kV minimum ESD immunity ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Inputs and outputs on opposite sides of package for easy board layout ■ Non-inverting 3-STATE outputs ■ TTL compatible inputs ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number 74ACTQ541SC M20B 74ACTQ541MTC MTC20 74ACTQ541PC N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code. Logic Symbol Connection Diagram IEEE/IEC Truth Table Pin Descriptions Inputs Pin Name Pin Description OE1 – OE2 3-STATE Output Enable (Active-LOW) I0 –I7 Inputs O1 – O7 Outputs OE1 DS010932 I L L H H X X Z X H X Z L L L L H = HIGH Voltage Level L = LOW Voltage Level FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation Outputs OE2 H X = Immaterial Z = High Impedance www.fairchildsemi.com 74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs March 1993 74ACTQ541 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Input Voltage (VI) 0V to VCC Output Voltage (VO) −0.5V to VCC + 0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V Supply Voltage VCC VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V 125 mV/ns ±50 mA DC Output Source or Sink Current (IO) DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) −65°C to +150°C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ± 300 mA DC Latch-up Source or Sink Current Junction Temperature (TJ) 140°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter (V) Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 3.0 2.99 2.9 2.9 4.5 4.49 Output Voltage VOL TA = +25°C VCC 4.4 4.4 4.5 3.86 3.76 5.5 4.86 4.76 Units V V VIN = VIL or VIH (Note 2) IOH = −24 mA −24 mA V IOUT = 50 µA VIN = VIL or VIH (Note 2) IOH = 24 mA 24 mA 0.002 0.1 0.1 4.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 V 5.5 ± 0.1 ± 1.0 µA Maximum 3-STATE Leakage Current ±0.25 5.5 or VCC − 0.1V V 3.0 Maximum Input Leakage Current or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA Maximum LOW Level IIN VOUT = 0.1V V Output Voltage IOZ Conditions ±2.5 µA 1.5 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent Supply Current 5.5 40.0 µA VIN = VCC or GND VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Minimum HIGH Level Dynamic Input Voltage VILD Maximum LOW Level Dynamic Input Voltage 0.6 4.0 Figure 1, Figure 2 5.0 1.1 1.5 V 5.0 −0.6 −1.2 V 5.0 1.9 2.2 V (Note 4)(Note 6) 5.0 1.2 0.8 V (Note 4)(Note 6) (Note 4)(Note 5) Figure 1, Figure 2 (Note 4)(Note 5) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Plastic DIP package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 6: Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 7) tPLH Propagation Delay tPHL Data to Output tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 5.0 5.0 5.0 Min TA = −40°C to +85°C CL = 50 pF Typ Max Min Units Max 2.0 4.5 7.0 2.0 7.5 2.0 5.5 7.0 2.0 7.5 2.0 5.0 9.0 2.0 9.5 2.0 6.5 9.0 2.0 9.5 1.5 5.5 7.5 1.5 8.0 1.5 5.5 7.5 1.5 8.0 tOSHL Output to Output 0.5 1.0 1.0 tOSLH Skew Data to Output (Note 8) 0.5 1.0 1.0 ns ns ns ns Note 7: Voltage Range 5.0 is 5.0V ± 0.5V Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 70 pF VCC = 5.0V 3 Conditions www.fairchildsemi.com 74ACTQ541 AC Electrical Characteristics 74ACTQ541 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as V ILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability on the measurements. VOHVand VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit www.fairchildsemi.com 4 74ACTQ541 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com 74ACTQ541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com