FAIRCHILD NC7SBU3157

NC7SBU3157, FSAU3157
Low-Voltage SPDT Analog Switch or 2:1
Multiplexer / De-multiplexer Bus Switch
Features
General Description
■ Analog and digital applications
The NC7SBU3157 / FSAU3157 is a high-performance,
single-pole / double-throw (SPDT) analog switch or 2:1
multiplexer / de-multiplexer bus switch.
■ Space-saving, SC70 6-lead, surface-mount package
■ Low on resistance: <10Ω on typical at 3.3V VCC
■ Broad VCC operating range: 1.65V to 5.5V
■ Rail-to-rail signal handling
■ Power-down, high-impedance control input
■ Over-voltage tolerance of control input to 7.0V
■ Break-before-make enable circuitry
■ 250 MHz, 3dB bandwidth
The device is fabricated with advanced sub-micron
CMOS technology to achieve high-speed enable and
disable times and low on resistance. The break-beforemake select circuitry prevents disruption of signals on
the B port due to both switches temporarily being
enabled during select pin switching. The device is specified to operate over the 1.65 to 5.5V VCC operating
range. The control input tolerates voltages up to 5.5V,
independent of the VCC operating range.
Fairchild's integrated Undershoot Hardened Circuit
(UHC®) senses undershoot at the I/Os, and responds by
preventing voltage differentials from developing and
turning the switch on.
Ordering Information
Part Number
Top
Mark
Operating
Temperature
Range
Package Description
NC7SBU3157P6X
B7A
-40 to +85°C
6-Lead, SC70, EIAJ SC88, 1.25mm Wide Package
3000 Units
Tape and Reel
FSAU3157P6X
B7A
-40 to +85°C
6-Lead, SC70, EIAJ SC88, 1.25mm Wide Package
3000 Units
Tape and Reel
Packing
Method
All packages are lead free per JEDEC: J-STD-020B standard.
MicroPak™ is a trademark of Fairchild Semiconductor Corporation.
UHC® is a registered trademark of Fairchild Semiconductor Corporation.
©2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
April 2008
Connection Diagrams
B1
S
A
B0
2. Pin Assignments SC70
Figure 1. Logic Symbol
Analog Symbol
B1
S
VCC
GND
B0
A
Figure 4. Pin One Orientation
Figure 3. Analog Symbol
Note:
Orientation of top mark determines pin one location.
Read the top mark left to right and pin one is the lower
left pin (see Figure 4).
Function Table
Input (S)
Function
Logic Level Low
B0 Connected to A
Logic Level High
B1 Connected to A
Pin Descriptions
Pin Names
Description
A, B0, B1
Data Ports
S
Control Input
© 2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
2
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
Logic Symbol
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only
Symbol
VCC
VS
Parameter
Min.
Max.
Units
Supply Voltage
–0.5
+7.0
V
DC Switch Voltage(1)
–0.5
VCC +0.5
V
–0.5
+7.0
V
(1)
VIN
DC Input Voltage
IIK
DC Input Diode Current at VIN < 0V
DC Output Current
–50
mA
128
mA
DC VCC or Ground Current
±100
mA
+150
°C
°C
IOUT
ICC/IGND
TSTG
Storage Temperature Range
–65
TJ
Junction Temperature Under Bias
+150
TL
Junction Lead Temperature (Soldering, 10 seconds)
+260
°C
PD
Power Dissipation at +85°C
180
mW
Note:
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VIN
VIN
Parameter
Min.
Max
Units
1.65
5.50
V
Control Input
Voltage(2)
0
VCC
V
Switch Input
Voltage(2)
V
Supply Voltage Operating
0
VCC
Voltage(2)
0
VCC
V
TA
Operating Temperature
–40
+85
°C
tr, tf
Input Rise and Fall Time
Control Input VCC=2.3V–3.6V
0
10
ns/V
Control Input VCC=4.5V–5.5V
0
5
ns/V
θJA
Thermal Resistance
350
°C/W
VOUT
Output
Note:
2. Control input must be held HIGH or LOW; it must not float.
© 2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
3
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
Absolute Maximum Ratings
Symbol
Parameter
Conditions
TA = –40°C to
+85°C
TA = +25°C
VCC (V)
Min.
Typ.
Max.
Min.
VIH
High Level
Input Voltage
1.65 to 1.95 0.75 VCC
VIL
Low Level
Input Voltage
1.65 to 1.95
0.25 VCC
0.25 VCC
2.3 to 5.5
0.3 VCC
0.3 VCC
IIN
Input Leakage
Current
IOFF
2.3 to 5.5
0 ≤ VIN ≤ 5.5V
±0.1
±1
µA
1.65 to 5.5
±0.05
±0.1
±1
µA
4.5
3.0
15.0
15.0
VIN=2.4V, IO=–30mA
5.0
15.0
15.0
VIN=4.5V, IO=–30mA
7.0
15.0
15.0
4.0
20.0
20.0
10.0
20.0
20.0
VIN=0V, IO=24mA
3.0
VIN=3V, IO=–24mA
VIN=0V, IO=8mA
2.3
VIN=2.3V, IO=–8mA
VIN=0V, IO=4mA
1.65
VIN=1.65V, IO=–4mA
ICC
RRANGE
ΔRON
VIKU
Rflat
Quiescent Supply
Current;
V =V or GND IOUT=0
All Channels On or IN CC
Off
5.5
Analog Signal
Range
VCC
IA=–30mA, 0 ≤ VBn ≤ VCC
On Resistance
IA=–24mA, 0 ≤ VBn ≤ VCC
Over Signal Range
(3, 7)
IA=–8mA, 0 ≤ VBn ≤ VCC
On Resistance
Match BetweenChannels(3, 4, 5)
Voltage Undershoot
On Resistance
Flatness(3, 4, 6)
V
±0.05
Off State Leakage
0 ≤ A, B ≤ VCC
Current
Switch On
Resistance(3)
V
0.7 VCC
0 to 5.5
VIN=0V, IO=30mA
RON
0.75 VCC
0.7 VCC
Units
Max.
5.0
30.0
30.0
13.0
30.0
30.0
Ω
6.5
50.0
50.0
17.0
50.0
50.0
1
10
µA
VCC
V
0
VCC
0
4.5
25.0
3.0
50.0
2.3
100
IA=–4mA, 0 ≤ VBn ≤ VCC
1.65
300
IA=–30mA, VBn=3.15
4.5
0.15
IA=–24mA, VBn 2.1
3.0
0.2
IA=–8mA, VBn=1.6
2.3
0.5
IA=–4mA, VBn=1.15
1.65
0.5
0.0mA ≤ IIN ≤–50, OE 5.5v
5.5
IA=–30mA, 0 ≤ VBn ≤ VCC
5.0
6.0
IA=–24mA, 0 ≤ VBn ≤ VCC
3.3
12.0
IA=–8mA, 0 ≤ VBn ≤ VCC
2.5
28.0
IA=–4mA, 0 ≤ VBn ≤ VCC
1.8
125
Ω
Ω
–2
V
Ω
Notes:
3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is
determined by the lower of the voltages on the two (A or B Ports).
4. Parameter is characterized, but not tested in production.
5. ΔRON = RON max – RON minimum measured at identical VCC, temperature, and voltage levels.
6. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified
range of conditions.
7. Guaranteed by design.
© 2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
4
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
DC Electrical Characteristics
Symbol
Parameter
Conditions
VCC
(V)
TA = –40°C to
+85°C
Units Figure
Min. Typ. Max. Min. Max.
TA = +25°C
1.65 to 1.95
tPHL,
tPLH
Propagation Delay
Bus-to-Bus(8)
VI = OPEN
2.3 to 2.7
1.2
1.2
3.0 to 3.6
0.8
0.8
4.5 to 5.5
tPZL,
tPZH
tPLZ,
tPHZ
tBBM
Q
OIRR
Output Enable Time
Turn-On Time
(A to Bn)
Output Disable Time
Turn-Off Time
(A Port to B Port)
VI = 2 x VCC for tPZL
VI = 0V for tPZH
VI = 2 x VCC for tPLZ
VI = 0V for tPHZ
Break-Before-Make
Time(9)
Charge Injection(9)
0.3
Figure 7
Figure 8
ns
Figure 7
Figure 8
ns
Figure 7
Figure 8
ns
Figure 9
pC
Figure 10
dB
Figure 11
dB
Figure 12
0.3
1.65 to 1.95
7.0
23.0
7.0
24.0
2.3 to 2.7
3.5
13.0
3.5
14.0
3.0 to 3.6
2.5
6.9
2.5
7.6
4.5 to 5.5
1.7
5.2
1.7
5.7
1.65 to 1.95
3.0
12.5
3.0
13.0
2.3 to 2.7
2.0
7.0
2.0
7.5
3.0 to 3.6
1.5
5.0
1.5
5.3
3.5
0.8
3.8
4.5 to 5.5
0.8
1.65 to 1.95
0.5
0.5
2.3 to 2.7
0.5
0.5
3.0 to 3.6
0.5
0.5
4.5 to 5.5
0.5
0.5
CL = 0.1nF, VGEN = 0V,
5.0
7.0
RGEN = 0Ω
3.3
3.0
Off Isolation(10)
RL = 50Ω, f = 10MHz
1.65 to 5.5
–57.0
Crosstalk
RL = 50Ω, f = 10MHz
1.65 to 5.5
–54.0
BW
–3dB Bandwidth
RL = 50Ω
1.65 to 5.5
250
THD
Total Harmonic
Distortion(9)
RL = 600Ω, 0.5VPP,
f = 20Hz to 20KHz
5.0
.011
Xtalk
ns
MHz Figure 15
%
Notes:
8. This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than
the RC delay of the on resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage
source (zero output impedance).
9. Guaranteed by design.
10. Off Isolation = 20 log10 [VA / VBn].
Capacitance
TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested in production.
Symbol
CIN
CIO-B
CIOA-ON
Parameter
Conditions
Control Pin Input Capacitance
Typ.
Max.
Units
Figure
VCC = 0V
2.3
pF
B Port Off Capacitance
VCC = 5.0V
6.5
pF
Figure 13
A Port Capacitance When Switch Is Enabled
VCC = 5.0V
18.5
pF
Figure 14
© 2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
5
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
AC Electrical Characteristics
Symbol
VOUTU
Parameter
Output Voltage During Undershoot
Min.
Typ.
Units
Figure
2.5
VOH - 0.3
V
Figure 5
Note:
11. This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during
an input transient voltage undershoot event.
Figure 5. Output Voltage During Undershoot
Device Test Conditions
Parameter
Value
Units
VIN
see Figure 6
V
R1 = R2
100
KΩ
VTRI
7.0
V
VCC
5.5
V
Transient Input Voltage (VIN) Waveform
Figure 6. Transient Input Voltage Waveform
© 2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
6
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
Undershoot Characteristic
Notes:
Input driven by 50Ω source terminated in 50Ω.
CL includes load and stray capacitance.
Input PRR=1.0MHz; tw = 500ns.
Figure 7. AC Test Circuit
tr = 2.5ns
tr = 2.5ns
90%
Switch
Input
90%
50%
Control
Input
tr = 2.5ns
VCC
tr = 2.5ns
50%
10%
10%
tPZL
GND
Output
tPHL
50%
VOH
Output
50%
GND
tPLZ
VTRI
10%
tW
tPLH
50%
10%
50%
VCC
90%
90%
VOL
tPHZ
VOH
tPZH
50%
VOL
Output
VOL+0.3V
50%
VOH–0.3V
VTRI
Figure 8. AC Waveforms
Figure 9. Break-Before-Make Interval Timing
© 2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
7
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
AC Loading and Waveforms
RGEN
A
BN
Logic
Input
VOUT
OFF
ON
OFF
VGE
S
RL
1MΩ
CL
100pF
ΔVOUT
VOUT
Logic
Input
Q = (ΔVOUT)(CL)
Figure 10. Charge Injection Test
10nF
10nF
50Ω
Signal
Generator
0dBm
VCC
A
Logic Input
0V or VIH
S
BN
Analyzer
50Ω
B0 VCC
A
50Ω
B1
S
Analyzer
GND
50Ω
GND
Figure 11. Off Isolation
Figure 12. Crosstalk
10nF
10nF
A
Capacitance
Meter
f = 1MHz
Capacitance
Meter
VCC
S
Logic Input
0V or VCC
A
VCC
f = 1MHz
S
Logic Input
0V or VCC
BN
BN
GND
GND
Figure 14. Channel On Capacitance
Figure 13. Channel Off Capacitance
10nF
Signal
Generator
0dBm
BN
VCC
A
50Ω
S
Logic Input
0V or VCC
GND
Figure 15. Bandwidth
© 2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
8
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
AC Loading and Waveforms (continued)
Figure 16. 6-Lead, SC70, EIAJ SC88, 1.25mm Wide Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
For SC70 Tape and Reel Specifications, please visit:
http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf
© 2005 Fairchild Semiconductor Corporation
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
9
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
Physical Dimensions
NC7SBU3157, FSAU3157 — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch
10
NC7SBU3157, FSAU3157 Rev. 1.0.4
www.fairchildsemi.com
© 2005 Fairchild Semiconductor Corporation