Revised March 2000 DM74LS83A 4-Bit Binary Adder with Fast Carry General Description Features These full adders perform the addition of two 4-bit binary numbers. The sum (∑) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. ■ Full-carry look-ahead across the four bits The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion. ■ Typical power dissipation per 4-bit adder 95 mW ■ Systems achieve partial look-ahead performance with the economy of ripple carry ■ Typical add times Two 8-bit words 25 ns Two 16-bit words 45 ns Ordering Code: Order Number DM74LS83AN Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006378 www.fairchildsemi.com DM74LS83A 4-Bit Binary Adder with Fast Carry August 1986 DM74LS83A Truth Table H = HIGH Level, L = LOW Level Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs ∑1 and ∑2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs ∑3, ∑4, and C4. Logic Diagram www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA TA Free Air Operating Temperature 70 °C 2 V 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min 2.7 IOL = 4 mA, VCC = Min II IIH IIL Input Current @ Max VCC = Max Input Voltage VI = 7V HIGH Level VCC = Max Input Current VI = 2.7V LOW Level VCC = Max Input Current VI = 0.4V Typ (Note 2) Max Units −1.5 V 3.4 V 0.35 0.5 0.25 0.4 A or B 0.2 C0 0.1 A or B 40 C0 20 A or B −0.8 C0 −0.4 −20 V mA µA mA IOS Short Circuit Output Current VCC = Max (Note 3) −100 mA ICC1 Supply Current VCC = Max (Note 4) 19 34 mA ICC2 Supply Current VCC = Max (Note 5) 22 39 mA Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC1 is measured with all outputs open, all B inputs LOW and all other inputs at 4.5V, or all inputs at 4.5V. Note 5: ICC2 is measured with all outputs OPEN and all inputs grounded. 3 www.fairchildsemi.com DM74LS83A Absolute Maximum Ratings(Note 1) DM74LS83A Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output www.fairchildsemi.com Max CL = 50 pF Min Units Max C0 to ∑1 or ∑2 24 28 ns C0 to ∑1 or ∑2 24 30 ns C0 to ∑3 24 28 ns C0 to ∑3 24 30 ns C0 to ∑4 24 28 ns C0 to ∑4 24 30 ns Ai, Bi to ∑i 24 28 ns Ai, Bi to ∑i 24 30 ns C0 to C4 17 24 ns C0 to C4 17 25 ns Ai, Bi to C4 17 24 ns Ai, Bi to C4 17 26 ns 4 DM74LS83A 4-Bit Binary Adder with Fast Carry Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com