5-BIT REGISTERED TRANSCEIVER FEATURES SY100S891 DESCRIPTION 25Ω cut-off bus outputs 50Ω receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs (BUS) 1500ps max. delay from CLK2 to Receiver Outputs (Q) Individual bus enable pins Internal 75KΩ input pull-down resistors Voltage and temperature compensation for improved noise immunity ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Available in 28-pin PLCC package ■ ■ ■ ■ ■ ■ ■ ■ The SY100S891 is a 5-bit registered transceiver containing five bus transceivers with both transmit and receive registers. The bus outputs (BUS0 – BUS4) are specified for driving a 25 ohm bus and the receive outputs (Q0 – Q4) are specified for driving a 50 ohm line. The bus outputs have a normal high level output voltage and a normal low level output voltage when the bus enable (BUSEN0 – BUSEN4) is high. However, the output is switched to a cut-off level when a bus-enable is low. This cut-off level is sufficiently low that a relatively high impedance is presented to the bus in order to minimize reflections. There is one bus-enable for each bus driver; a clock (CLK1) which is common to all five bus driver registers; and a separate clock (CLK2) which is common to all five receive registers. Data at the D inputs is clocked to the Bus register by a positive transition of CLK1 and data on the bus is clocked into the Receiver register by a positive transition of CLK2. A high on the Master Reset clears all registers. PIN CONFIGURATION PIN NAMES Q4 BUS 4 VCCA D3 BUSEN3 D4 BUSEN4 Pin 25 24 23 22 21 20 19 Function BUSEN0–4 Bus Enable Inputs D0 – D4 Data Inputs CLK1 Bus Driver Clock Input CLK2 Receive Register Clock MR 26 18 Q3 MR Master Reset CLK2 27 17 CLK1 VEE 28 16 BUS3 VCC Q0 – Q4 Bus Receive Outputs 15 Q2 BUS0–4 Bus Outputs 14 13 BUS2 VCCA 12 Q1 TOP VIEW PLCC J28-1 1 D2 BUSEN2 2 D1 4 8 9 10 11 BUS1 D0 BUSEN0 7 Q0 6 BUS0 VCCA 5 BUSEN1 3 Rev.: E 1 Amendment: /0 Issue Date: August, 1998 SY100S891 Micrel BLOCK DIAGRAM D0 25Ω CUTOFF D Q R C D Q R C 50Ω BUS 0 Q0 BUSEN0 D1 25Ω CUTOFF D Q R C D Q R C 50Ω BUS 1 Q1 BUSEN1 D2 25Ω CUTOFF D Q R C D Q R C 50Ω BUS 2 Q2 BUSEN2 D3 25Ω CUTOFF D Q R C D Q R C BUSEN3 D4 50Ω 25Ω CUTOFF D Q R C D Q R C BUSEN4 MR CLK 1 CLK 2 2 50Ω BUS 3 Q3 BUS 4 Q4 SY100S891 Micrel DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol Parameter Min. Typ. Max. Unit –2160 –2100 mV VIN = VIH (Max.) or VIL (Min.) VIN = VIH (Max.) or VIL (Min.) VCUT Cut-off Bus Output Voltage –2200 Condition Loading with 25Ω to –2.20V VOH Output HIGH Voltage Bus –1025 –955 –880 mV VOL Output LOW Voltage Bus –1810 –1705 –1620 mV VOHA Output HIGH Voltage Bus –1035 — — mV VOLA Output LOW Voltage Bus — — –1610 mV VOH Output HIGH Voltage Receiver –1025 –955 –880 mV VOL Output LOW Voltage Receiver –1810 –1705 –1620 mV VOHA VOLA Output HIGH Voltage Receiver Output LOW Voltage Receiver –1035 — — — — –1610 mV mV VIH Input HIGH Voltage –1165 — –880 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage –1810 — –1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.5 — — µA VIN = VIL (Min.) IIH Input High Current — — 150 µA VIN = VIH (Max.) IEE Power Supply Current –216 — — mA Inputs Open CIN Input Pin Capacitance — 4 — pF COUT Output Pin Capacitance — 5 — pF 3 Loading with 25Ω to –2.0V VIN = VIH (Min.) or VIL (Max.) VIN = VIH (Max.) or VIL (Min.) Loading with 50Ω to –2.0V VIN = VIH (Min.) or VIL (Max.) SY100S891 Micrel AC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit tPLH tPHL Propagation CLK1 to Bus Delay(1) 600 1000 1500 600 1000 1500 600 1000 1500 ps tPLH tPHL Propagation Delay(2) CLK2 to Q 500 800 1200 500 800 1200 500 800 1200 ps tPLH tPHL Propagation Delay(1) BUSEN to Bus 500 800 1200 500 800 1200 500 800 1200 ps tPLH tPHL Propagation Delay(1) Master Reset to Bus 600 1000 1500 600 1000 1500 600 1000 1500 ps tPLH tPHL Propagation Delay(2) Master Reset to Q 500 800 1200 500 800 1200 500 800 1200 ps tS Set-up Time Bus Wrt CLK2 D Wrt CLK1 — — — — 400 400 — — — — 400 400 — — — — 400 400 — — 1000 — — 1000 — — 1000 — — — — 400 400 — — — — 400 400 — — — — 400 400 Output Rise Time Bus(3) Q(4) 500 300 — — 1000 900 500 300 — — 1000 900 500 300 — — 1000 900 Output Fall Time Bus(3) Q(4) 500 300 — — 1000 900 500 300 — — 1000 900 500 300 — — 1000 900 — 100 — — 100 — — 100 — tREL Master Reset Release Time tH Hold Time Bus Wrt CLK2 D Wrt CLK1 tr tf tskew ps ps ps ps ps Skew (Maximum difference between slowest and fastest path) NOTES: 1. Loaded with 25Ω to –2.0V 2. Loaded with 50Ω to –2.0V 3. 25Ω Load 4. 50Ω Load PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY100S891JC J28-1 Commercial SY100S891JCTR J28-1 Commercial 4 ps Condition SY100S891 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 5