TRIPLE D FLIP-FLOP FEATURES BLOCK DIAGRAM VEE VEES CD Q2 CP MR D Q2 SD SD1 D1 4 3 Q1 Q1 VCCA 2 1 Top View PLCC J28-1 VCC VCC 28 27 18 Q2 26 Q2 1 2 SD2 CD2 3 4 5 6 CP2 Q0 D2 MS CPC SD1 MR VEE 24 23 22 21 20 19 18 17 Top View 16 Flatpack 15 F24-1 14 13 7 8 9 10 11 12 Q2 SD CP1 CD1 SD0 CD0 CP0 D0 Q0 Q0 Q1 Q1 Q0 CP D D1 Q1 SD Q2 VCC VCCA D CD2 CP2 D2 Q1 CP CD CP0 D0 SD0 12 13 14 15 16 17 19 20 21 22 23 24 25 CD CP1 D1 SD1 CD0 Q0 11 10 9 8 7 6 5 MS CPC CD2 CPC CP2 D2 SD2 CD1 D0 Q0 PIN CONFIGURATIONS SD0 CD0 CP0 VEES ■ ■ ■ ■ ■ The SY100S331 offers three D-type, edge-triggered master/slave flip-flops with true and complement outputs, designed for use in high-performance ECL systems. Each flip-flop is controlled by a common clock (CPc), as well as its own clock pulse (CPn). The resultant clock signal controlling the flip-flop is the logical OR operation of these two clock signals. Data enters the master when both CPc and CPn are LOW and enters the slave on the rising edge of either CPc or CPn (or both). Additional control signals include Master Set (MS) and Master Reset (MR) inputs. Each flip-flop also has its own Direct Set (SDn) and Direct Clear (CD n) signals. The MR, MS, SDn and DCn signals override the clock signals. The inputs on this device have 75KΩ pull-down resistors. Max. toggle frequency of 800MHz Differential outputs IEE min. of –80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors 150% faster than Fairchild 40% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages CD1 SD2 VEES ■ DESCRIPTION CP1 ■ ■ ■ ■ ■ SY100S331 MS MR Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S331 Micrel PIN NAMES Pin Function CP0 – CP2 Individual Clock Inputs CPc Common Clock Input D0 – D2 Data Inputs CD0 – CD2 Individual Direct Clear Inputs SDn Individual Direct Set Inputs MR Master Reset Input MS Master Set Input Q0 – Q2 Data Outputs Q0 – Q2 Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs TRUTH TABLES Synchronous Operation(1) Asynchronous Operation(1) Inputs Inputs Outputs Outputs Dn CPn CPc MS SDn MR DCn Qn (t+1) Dn CPn CPc MS SDn MR DCn Qn X X X H L H L u L L L L X X X L H L H u L L L H X X X H H U L L u L L L H L u L L H X L L L L Qn (t) X H X L L Qn (t) X X H L L Qn (t) NOTE: 1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U = Undefined, t = Time before CP Positive Transition, t+1 = Time after CP Positive Transition, u = Low-to-High Transition NOTE: 1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U = Undefined, t = Time before CP Positive Transition, t+1 = Time after CP Positive Transition, u = Low-to-High Transition DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND Symbol Parameter IIH Input HIGH Current, All Inputs IEE Power Supply Current Min. Typ. Max. Unit — — 200 µA VIN = VIH (Max.) –80 –65 –35 mA Inputs Open 2 Condition SY100S331 Micrel AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fmax Toggle Frequency 800 — 800 — 800 — MHz tPLH tPHL Propagation Delay CPc to Output 300 800 300 800 300 800 ps tPLH tPHL Propagation Delay CPn to Output 300 800 300 800 300 800 ps tPLH tPHL Propagation Delay CDn, SDn to Output 300 900 300 900 300 900 ps tPLH tPHL Propagation Delay MS, MR to Output 300 1000 300 1000 300 1000 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dn CDn, SDn (Release Time) MS, MR (Release Time) 400 500 800 — — — 400 500 800 — — — 400 500 800 — — — tH Hold Time Dn 300 — 300 — 300 — ps tpw (H) Pulse Width HIGH CPn, CPc, DCn SDn, MR, MS 800 — 800 — 800 — ps Condition ps PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fmax Toggle Frequency 800 — 800 — 800 — MHz tPLH tPHL Propagation Delay CPc to Output 300 700 300 700 300 700 ps tPLH tPHL Propagation Delay CPn to Output 300 700 300 700 300 700 ps tPLH tPHL Propagation Delay CDn, SDn to Output 300 800 300 800 300 800 ps tPLH tPHL Propagation Delay MS, MR to Output 300 900 300 900 300 900 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dn CDn, SDn (Release Time) MS, MR (Release Time) 400 500 800 — — — 400 500 800 — — — 400 500 800 — — — tH Hold Time Dn 300 — 300 — 300 — ps tpw (H) Pulse Width HIGH CPn, CPc, DCn SDn, MR, MS 800 — 800 — 800 — ps ps 3 Condition SY100S331 Micrel TIMING DIAGRAMS DATA 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V 80% 50% 20% CLOCK –1.69V tpw (H) 1/fmax tPHL tPLH OUTPUT 50% tPLH tPHL OUTPUT tTHL tTLH Propagation Delay (Clock) and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND 0.7 ± 0.1 ns 0.7 ± 0.1 ns +1.05V 80% 50% 20% SDn, CDn MS, MR +0.31V tS (RELEASE TIME) tpw (H) CLOCK 50% tPHL tPLH OUTPUT 50% tPLH tPHL 80% 50% 20% OUTPUT Propagation Delay (Sets and Resets) 4 SY100S331 Micrel TIMING DIAGRAMS +1.05V DATA 50% +0.31V th tS +1.05V CLOCK 50% +0.31V Data Setup and Hold Time NOTES: ts is the minimum time before the transition of the clock that information must be present at the data input. th is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code 5 Package Type Operating Range SY100S331FC F24-1 Commercial SY100S331JC J28-1 Commercial SY100S331JCTR J28-1 Commercial SY100S331 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 6 SY100S331 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 7