4-STAGE COUNTER/ SHIFT REGISTER FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S336 functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three Select inputs (Sn) are provided for determining the mode of operation. The Function Table lists the available modes of operation. In order to allow cascading for multistage counters, two Count Enable controls (CEP, CET) are provided. The CET input also functions as the Serial Data input (S0) for a shift-up operation, while the D3 input serves as the Serial Data input for the shift-down operation. When the device is in the counting mode, the Terminal Count (TC) goes to a logical LOW when the count reaches 15 for count-up or reaches 0 for count-down. When in the shift mode, the TC output simply repeats the Q3 output. The flexiblity provided by the TC/Q3 output and the D0/ CET input allows these signals to be interconnected from one stage to the next higher stage for multistage counting or shift-up operations. The individual Presets (Pn) allow initialization of the counter by entering data in parallel to preset the counter. A logic HIGH on the Master Reset (MR) overrides all other inputs and asynchronously clears the flip-flops. An additional synchronous Clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 75KΩ pulldown resistors. Max. shift frequency of 700MHz Clock to Q delay max. of 1100ps IEE min. of –170mA Internal 75KΩ input pull-down resistors Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity 50% faster than Fairchild 300K at lower power Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages D3 Q3 Q3 P2 P3 VEES P1 PIN CONFIGURATIONS 11 10 9 8 7 6 5 18 PIN NAMES VCC VCC Pin Q1 26 Q1 Function CP Clock Pulse Input CEP Count Enable Parallel Input (Active LOW) D0/CET Serial Data Input/Count Enable Trickle Input (Active LOW) S0 — S2 Select Inputs 24 23 22 21 20 19 1 18 P1 MR Master Reset Input 2 3 17 16 P2 P3 VEES VEE Substrate 15 14 D3 Q3 VCCA VCCO for ECL Outputs P0 – P3 Preset Inputs 13 7 8 9 10 11 12 Q3 4 5 Q0 6 Q2 Q2 TC Q0 Top View Flatpack F24-1 VCCA S2 CEP D0/CET CP P0 Q0 TC Q0 S2 19 20 21 22 23 24 25 CEP D0/CET VEES S0 S1 Q2 VCCA 2 1 28 27 Top View PLCC J28-1 S0 MR VEE 14 15 16 17 Q2 S1 VEE VEES MR 4 3 Q1 VCC 12 13 Q1 P0 CP SY100S336 D3 Serial Data Input TC Terminal Count Output Q0 — Q3 Data Outputs Q0 — Q3 Complementary Data Outputs Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S336 Micrel BLOCK DIAGRAM D3 D0/CET S0 CEP S1 S2 TC T Q0 T T Q1 T T Q2 R Q1 T T C R Q2 T TC T T Q0 R RT C T T Q3 T T R Q3 T TC CP MR P0 Q0 Q0 P1 Q1 Q1 P2 Q2 Q2 2 P3 Q3 Q3 SY100S336 Micrel TRUTH TABLE(1) Inputs Outputs MR S2 S1 S0 CEP D0/CET D3 CP Q0 Q1 Q2 Q3 TC L L L L X X X u P0 P1 P2 P3 L Preset (Parallel Load) Mode L L L H X X X u Q0 Q1 Q2 Q3 L Invert L L H L X X X u Q1 Q2 Q3 D3 D3 Shift Left L L H H X X X u D0 Q0 Q1 Q2 Q3* Shift Right L H L L L L X u L H L L H L X X Q0 Q1 Q2 L H L L X H X X Q0 Q1 L H L H X X X u L L L H H L L L X u L H H L H L X X Q0 Q1 Q2 L H H L X H X X Q0 Q1 L H H H X X X X Q0 H H H H H H H H H L L L L H H H H H L L H H L L L H H L H L H L L H L H X X X X X X X X X X X X X L H X X X X X X X X X X X X X X X X X X X X X L L L L L L L L L ① Count Down Q3 ① Q2 Q3 H Count Down with CEP Not Active Count Down with CET Not Active L L H Clear ≠ Count Up Q3 ≠ Q2 Q3 H Count Up with CEP Not Active Count Up with CET Not Active Q1 Q2 Q3 H Hold L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H Asynchronous Master Reset (Q0–3) minus 1 (Q0–3) plus 1 NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care u = LOW-to-HIGH Transition ① = L if Q0 – Q3 = LLLL H if Q0 – Q3 ≠ LLLL ≠ = L if Q0 – Q3 = HHHH H if Q0 – Q3 ≠ HHHH * Before the clock, TC is Q3; after the clock, TC is Q2 DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND Symbol Parameter IIH Input HIGH Current, All Inputs IEE Power Supply Current Min. Typ. Max. Unit Condition — — 200 µA VIN = VIH (Max.) –170 –145 –90 mA Inputs Open 3 SY100S336 Micrel AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fshift Shift Frequency700 — 700 — 700 — MHz tPLH tPHL Propagation Delay CP to Qn, Qn 450 1200 450 1200 450 1200 ps tPLH tPHL Propagation Delay CP to TC 600 1900 600 1900 600 1900 ps tPLH tPHL Propagation Delay MR to Qn, Qn 500 1400 500 1400 500 1400 ps tPLH tPHL Propagation Delay MR to TC 600 1900 600 1900 600 1900 ps tPLH tPHL Propagation Delay D0/CET to TC 400 1200 400 1200 400 1200 ps tPLH tPHL Propagation Delay Sn to TC 1500 2600 1500 2600 1500 2600 ps tTLH tTHL Transition Time300 20% to 80%, 80% to 20% 900 300 900 300 900 ps tS Set-up Time D3 Pn D0/CET to CEP Sn MR (Release Time) 800 800 700 2000 900 — — — — — 800 800 700 2000 900 — — — — — 800 800 700 2000 900 — — — — — Hold Time D3 Pn D0/CET to CEP Sn 200 200 200 -600 — — — — 200 200 200 -600 — — — — 200 200 200 -600 — — — — — 800 — 800 — 800 tH tpw (H) Pulse Width HIGH, CP, MR ps ps 4 ps Condition SY100S336 Micrel AC ELECTRICAL CHARACTERISTICS PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fshift Shift Frequency700 — 700 — 700 — MHz tPLH tPHL Propagation Delay CP to Qn, Qn 450 1100 450 1100 450 1100 ps tPLH tPHL Propagation Delay CP to TC 600 1800 600 1800 600 1800 ps tPLH tPHL Propagation Delay MR to Qn, Qn 500 1300 500 1300 500 1300 ps tPLH tPHL Propagation Delay MR to TC 600 1800 600 1800 600 1800 ps tPLH tPHL Propagation Delay D0/CET to TC 400 1100 400 1100 400 1100 ps tPLH tPHL Propagation Delay Sn to TC 1500 2500 1500 2500 1500 2500 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time D3 Pn D0/CET to CEP Sn MR (Release Time) 800 800 700 2000 900 — — — — — 800 800 700 2000 900 — — — — — 800 800 700 2000 900 — — — — — Hold Time D3 Pn D0/CET to CEP Sn 200 200 200 -600 — — — — 200 200 200 -600 — — — — 200 200 200 -600 — — — — — 800 — 800 — 800 tH tpw (H) Pulse Width HIGH, CP, MR ps ps 5 ps Condition SY100S336 Micrel TIMING DIAGRAMS DATA 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V 80% 50% 20% CLOCK –1.69V 1/fshift tPHL tpw (H) tPLH OUTPUT 50% tPLH tPHL OUTPUT tTLH tTHL Propagation Delay (Clock) and Transition Times 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V 80% 50% 20% MR –1.69V tS (RELEASE TIME) tpw (H) CLOCK 50% tPHL tPLH OUTPUT 50% tPLH tPHL 80% 50% 20% OUTPUT Propagation Delay (Reset) 6 SY100S336 Micrel TIMING DIAGRAMS 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V INPUT 80% 50% 20% –1.69V tPHL tPLH 80% 50% 20% OUTPUT tTLH tTHL Propagation Delay (Serial Data, Selects) INHIBIT COUNT –0.95V 50% CEP –1.69V ENABLE COUNT tH tS –0.95V D3 , P n , S n 50% –1.69V tH tS –0.95V CLOCK 50% –1.69V Set-up and Hold Time NOTES: 1. VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND. 2. tS is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY100S336FC F24-1 Commercial SY100S336JC J28-1 Commercial SY100S336JCTR J28-1 Commercial 7 SY100S336 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 8 SY100S336 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. 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