TRIPLE D FLIP-FLOP Micrel, Inc. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S331 offers three D-type, edge-triggered master/slave flip-flops with true and complement outputs, designed for use in high-performance ECL systems. Each flip-flop is controlled by a common clock (CPc), as well as its own clock pulse (CPn). The resultant clock signal controlling the flip-flop is the logical OR operation of these two clock signals. Data enters the master when both CPc and CPn are LOW and enters the slave on the rising edge of either CPc or CPn (or both). Additional control signals include Master Set (MS) and Master Reset (MR) inputs. Each flip-flop also has its own Direct Set (SDn) and Direct Clear (CDn) signals. The MR, MS, SDn and DCn signals override the clock signals. The inputs on this device have 75KΩ pull-down resistors. Max. toggle frequency of 800MHz Differential outputs IEE min. of –80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors 150% faster than Fairchild 40% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages PIN NAMES BLOCK DIAGRAM Pin CD2 CPC CP2 D2 SD2 CD1 CD Q2 CP D Q2 SD CP D SD D Individual Clock Inputs CPc Common Clock Input D0 – D2 Data Inputs CD0 – CD2 Individual Direct Clear Inputs Individual Direct Set Inputs MR Master Reset Input Q1 MS Master Set Input Q0 – Q2 Data Outputs Q0 – Q2 Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs Q0 CP CP0 – CP2 SDn CD CP0 D0 SD0 Function Q1 CD CP1 D1 SD1 CD0 SY100S331 SY100S331 Q0 SD MS MR M9999-032206 [email protected] or (408) 955-1690 Rev.: H 1 Amendment: /0 Issue Date: March 2006 SY100S331 Micrel, Inc. 11 10 9 8 7 6 MS CPC 14 15 MR 16 17 SD1 D1 Package Type Operating Range Package Marking Lead Finish SY100S331FC F24-1 Commercial SY100S331FC Sn-Pb SY100S331FCTR(1) F24-1 Commercial SY100S331FC Sn-Pb VCC VCC SY100S331JC J28-1 Commercial SY100S331JC Sn-Pb Q2 SY100S331JCTR(1) J28-1 Commercial SY100S331JC Sn-Pb Q2 SY100S331JZ(2) J28-1 Commercial SY100S331JZ with Pb-Free bar-line indicator Matte-Sn SY100S331JZTR(1, 2) J28-1 Commercial SY100S331JZ with Pb-Free bar-line indicator Matte-Sn 5 12 13 VEE VEES Ordering Information Q0 D0 Q0 SD0 CD0 CP0 VEES PACKAGE/ORDERING INFORMATION 4 3 2 1 Top View PLCC J28-1 28 27 18 26 Q1 Q1 VCCA CD2 CP2 D2 CD1 SD2 VEES CP1 19 20 21 22 23 24 25 Notes: 5 6 MS CPC 24 23 22 21 20 19 18 17 Top View 16 Flatpack 15 F24-1 14 13 7 8 9 10 11 12 Q2 Q2 VCC VCCA D2 3 4 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. SD0 CD0 CP0 D0 Q0 Q0 Q1 Q1 CD2 CP2 1 2 SD1 MR VEE D1 28-Pin PLCC (J28-1) CP1 CD1 SD2 Part Number 24-Pin Cerpack (F24-1) M9999-032206 [email protected] or (408) 955-1690 2 SY100S331 Micrel, Inc. TRUTH TABLES Synchronous Operation(1) Asynchronous Operation(1) Inputs Inputs Outputs Outputs Dn CPn CPc MS SDn MR DCn Qn (t+1) Dn CPn CPc MS SDn MR DCn Qn X X X H L H L u L L L L X X X L H L H u L L L H X X X H H U L L u L L L H L u L L H X L L L L Qn (t) X H X L L Qn (t) X X H L L Qn (t) NOTE: 1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U = Undefined, t = Time before CP Positive Transition, t+1 = Time after CP Positive Transition, u = Low-to-High Transition NOTE: 1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U = Undefined, t = Time before CP Positive Transition, t+1 = Time after CP Positive Transition, u = Low-to-High Transition DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND Symbol Parameter IIH Input HIGH Current, All Inputs IEE Power Supply Current M9999-032206 [email protected] or (408) 955-1690 Min. Typ. Max. Unit — — 200 µA VIN = VIH (Max.) –80 –65 –35 mA Inputs Open 3 Condition SY100S331 Micrel, Inc. AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fmax Toggle Frequency 800 — 800 — 800 — MHz tPLH tPHL Propagation Delay CPc to Output 300 800 300 800 300 800 ps tPLH tPHL Propagation Delay CPn to Output 300 800 300 800 300 800 ps tPLH tPHL Propagation Delay CDn, SDn to Output 300 900 300 900 300 900 ps tPLH tPHL Propagation Delay MS, MR to Output 300 1000 300 1000 300 1000 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dn CDn, SDn (Release Time) MS, MR (Release Time) 400 500 800 — — — 400 500 800 — — — 400 500 800 — — — tH Hold Time Dn 300 — 300 — 300 — ps tpw (H) Pulse Width HIGH CPn, CPc, DCn SDn, MR, MS 800 — 800 — 800 — ps Condition ps PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter Min. TA = +25°C Max. Min. Max. TA = +85°C Min. Max. Unit fmax Toggle Frequency 800 — 800 — 800 — MHz tPLH tPHL Propagation Delay CPc to Output 300 700 300 700 300 700 ps tPLH tPHL Propagation Delay CPn to Output 300 700 300 700 300 700 ps tPLH tPHL Propagation Delay CDn, SDn to Output 300 800 300 800 300 800 ps tPLH tPHL Propagation Delay MS, MR to Output 300 900 300 900 300 900 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dn CDn, SDn (Release Time) MS, MR (Release Time) 400 500 800 — — — 400 500 800 — — — 400 500 800 — — — tH Hold Time Dn 300 — 300 — 300 — ps tpw (H) Pulse Width HIGH CPn, CPc, DCn SDn, MR, MS 800 — 800 — 800 — ps M9999-032206 [email protected] or (408) 955-1690 ps 4 Condition SY100S331 Micrel, Inc. TIMING DIAGRAMS DATA 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V 80% 50% 20% CLOCK –1.69V tpw (H) 1/fmax tPHL tPLH OUTPUT 50% tPLH tPHL OUTPUT tTHL tTLH Propagation Delay (Clock) and Transition Times Note: VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND 0.7 ± 0.1 ns 0.7 ± 0.1 ns +1.05V 80% 50% 20% SDn, CDn MS, MR +0.31V tS (RELEASE TIME) tpw (H) CLOCK 50% tPHL tPLH OUTPUT 50% tPLH tPHL 80% 50% 20% OUTPUT Propagation Delay (Sets and Resets) M9999-032206 [email protected] or (408) 955-1690 5 SY100S331 Micrel, Inc. TIMING DIAGRAMS +1.05V DATA 50% +0.31V th tS +1.05V CLOCK 50% +0.31V Data Setup and Hold Time Notes: ts is the minimum time before the transition of the clock that information must be present at the data input. th is the minimum time after the transition of the clock that information must remain unchanged at the data input. M9999-032206 [email protected] or (408) 955-1690 6 SY100S331 Micrel, Inc. 24-PIN CERPACK (F24-1) Rev. 03 M9999-032206 [email protected] or (408) 955-1690 7 SY100S331 Micrel, Inc. 28-PIN PLCC (J28-1) Rev. 03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-032206 [email protected] or (408) 955-1690 8