LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow each circuit to be used as an inverting/non-inverting translator, or as a differential line driver. A common enable (E), when LOW, holds all inverting outputs HIGH and all non-inverting inputs LOW. The SY100S391 is ideal for those mixed PECL/TTL applications which only have a +5V supply available. When used in the differential mode, the S391, due to its high common mode rejection, overcomes voltage gradients between the TTL and PECL ground systems. Operates from a single +5V supply Differential PECL outputs Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages BLOCK DIAGRAM E D2 GND TTL Data Outputs (PECL) Q0 — Q5 Inverting Data Outputs (PECL) E Enable Input (TTL) VCCA VCCO for ECL Outputs Q0 1 24 23 22 21 20 19 18 D1 D5 Q5 2 3 17 16 D0 Q0 Q5 Q4 4 5 15 14 Q0 Q1 Q4 6 13 7 8 9 10 11 12 Q1 Top View Flatpack F24-1 Rev.: G 1 D2 GND PECL GND TTL D4 Q2 Q2 Q0 — Q5 Q3 VCC VCCA Data Inputs (TTL) Q3 26 Q3 Function D0 — D5 VCC VCC 28 27 19 20 21 22 23 24 25 PIN NAMES Pin Q2 VCCA 2 1 Top View PLCC J28-1 D3 Q5 Q5 18 Q2 E GND PECL D5 D3 4 3 Q3 D4 Q4 Q4 GND PECL E 12 13 14 15 16 17 GND PECL GNDS Q3 Q3 D3 Q1 Q1 D2 Q2 Q2 11 10 9 8 7 6 5 Q5 Q4 Q4 Q1 Q1 D1 D1 D5 Q5 GNDS D0 D0 Q0 GNDS PIN CONFIGURATIONS Q0 Q0 D4 ■ ■ ■ ■ SY100S391 Amendment: /0 Issue Date: July, 1999 SY100S391 Micrel TRUTH TABLE LOGIC SYMBOL Inputs Outputs Dn E Qn Qn H H H L L H L H H L L H L L L H E NOTE: 1. H = High Voltage Level, L = Low Voltage Level D0 D1 D2 D3 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 GUARANTEED OPERATING CONDITIONS Rating TA Value Operating Temperature Commercial Supply Voltage VCC D5 Q4 Q4 Q5 Q5 ABSOLUTE MAXIMUM RATINGS(1) Symbol Symbol D4 (1) Rating — Unit +4.5 to +5.5 –0.5 to +7.0 V (2) –30 to +5.0 V –50 V — TTL Input Current — PECL Output Current (DC Output HIGH) — VCC Pin Potential to Ground Pin –0.5 to +7.0 V Tstore Storage Temperature –65 to +150 ˚C TJ Max. Junction Temp. Ceramic Plastic +175 +150 V NOTE: 1. Do not exceed. Unit TTL Input Voltage ˚C 0 to +85 Value (2) ˚C NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. 2. Either voltage limit or current limit is siffucient to protect inputs. TTL-TO-PECL DC ELECTRICAL CHARACTERISTICS(1) VCC = +5.0V ± 10%; GND = 0V Symbol Min. Typ. Max. Unit VOH Output HIGH Voltage Parameter VCC –1025 VCC –955 VCC –870 mV VOL Output LOW Voltage VCC –1890 VCC –1705 VCC –1620 VOHC Output HIGH Voltage Corner Point High VCC –1035 — — mV VOLC Output LOW Voltage Corner Point Low — — VCC –1610 mV VIH Input HIGH Voltage 2.0 — 5.0 V Over VTTL, VEE, TA Range VIL Input LOW Voltage 0 — 0.8 V Over VTTL, VEE, TA Range IIH Input HIGH Current — — 10 µA VIN = +2.7V Breakdown Current — — 100 µA VIN = +5.5V, VCC = Max. — — –0.8 –4.2 mA VIN = +0.5V Dn E Condition VIN = VIH (Max.) or VIL (Min.) Loading with 50Ω to VCC –2V VIN = VIH (Min.) or VIL (Max.) Loading with 50Ω to VCC –2V IIL Input LOW Current VCD Input Clamp Diode Voltage — — –1.2 V IIN = –18mA ICC VCC Supply Current 25 — 69 mA Inputs Open NOTE: 1. The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions. 2 SY100S391 Micrel AC ELECTRICAL CHARACTERISTICS CERPACK AND PLCC VCC = +5.0V ± 10% TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Data and Enable to Output 400 1400 400 1400 400 1400 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 350 1700 350 1700 350 1700 ps TIMING DIAGRAM 2.5 ± 0.3ns 2.5 ± 0.3ns 3.0V 90% 50% 10% INPUT 1.5V 0V tPLH tPHL COMPLEMENT 50% tPLH OUTPUT tPHL 80% 50% 20% TRUE tTHL tTLH Propagation Delay and Transition Times 3 Condition SY100S391 Micrel TEST CIRCUIT GNDTTL VIH 0.1µF 0.1µF 0.1µF L1 SCOPE CHAN A L2 S/H RT 50 RT 100 –4V PECL TERMINATOR NET L3 PULSE GENERATOR 0.1µF 2.5µF VCC GNDPECL PRODUCT ORDERING CODE Ordering Code 4 Package Type Operating Range SY100S391FC F24-1 Commercial SY100S391JC J28-1 Commercial SY100S391JCTR J28-1 Commercial SY100S391 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 5 SY100S391 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 6