Micrel ×4 CML ULTRA PRECISION 4× SWITCH WITH INTERNAL I/O TERMINATION SY58040U Precision Edge™ SY58040U FEATURES ■ Provides crosspoint switching between any input pair to any output pair ■ Guaranteed AC performance over temperature and voltage: • DC to >5Gbps throughput • <350ps propagation delay • <60ps tr / tf times • <25ps skew (output-to-output) ■ Unique, patent-pending, channel-to-channel isolation design provides superior crosstalk performance ■ Ultra-low jitter design: • <1psrms random jitter • <10pspp deterministic jitter • <10pspp total jitter (clock) • <0.7psrms crosstalk-induced jitter ■ Unique, patent-pending, 50Ω input termination extended CMVR, and VT pin accepts DC- and ACcoupled differential inputs ■ 400mV CML output swing ■ 50Ω source terminated outputs minimize round-trip reflections ■ Power supply 2.5V ±5% or 3.3V ±10% ■ –40°C to +85°C temperature range ■ Available in 44-pin (7mm × 7mm) MLF™ package Precision Edge™ DESCRIPTION The SY58040U is a low jitter, low skew, high-speed 4×4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY58040U distributes clock frequencies from DC to 4GHz, and data rates to 5Gbps guaranteed over temperature and voltage. The SY58040U differential input includes Micrel’s unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The outputs are 50Ω source-terminated CML with extremely fast rise/fall times guaranteed to be less than 60ps. The SY58040U features a patent-pending isolation design that significantly improves on channel-to-channel crosstalk performance. The SY58040U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY58040U is part of Micrel’s high-speed, Precision Edge™ product line. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. APPLICATIONS ■ ■ ■ ■ Data communication systems All SONET/SDH data/clock applications All Fibre Channel applications All Gigabit Ethernet applications Precision Edge is a trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. M9999-072904 [email protected] or (408) 955-1690 Rev.: A 1 Amendment: /0 Issue Date: July 2004 SY58040U Micrel FUNCTIONAL BLOCK DIAGRAM IN0 50Ω VT0 0 50Ω /IN0 VREF-AC0 1 Q0 2 /Q0 3 IN1 0 50Ω VT1 50Ω /IN1 VREF-AC1 1 Q1 2 /Q1 3 0 IN2 50Ω 1 Q2 50Ω 2 /Q2 VT2 /IN2 VREF-AC2 3 0 IN3 50Ω VT3 1 Q3 2 /Q3 3 50Ω /IN3 VREF-AC3 SIN0 (CMOS/TTL) SIN1 (CMOS/TTL) SOUT0 (CMOS/TTL) Control Logic SOUT1 (CMOS/TTL) CONF (CMOS/TTL) LOAD (CMOS/TTL) TRUTH TABLES Output Select Address Table Input Select Address Table SIN1 SIN0 INPUT SOUT1 SOUT0 OUTPUT 0 0 IN0 0 0 Q0 0 1 IN1 0 1 Q1 1 0 IN2 1 0 Q2 1 1 IN3 1 1 Q3 M9999-072904 [email protected] or (408) 955-1690 2 SY58040U Micrel PACKAGE/ORDERING INFORMATION GND GND VREF_AC3 IN3 VT3 /IN3 SOUT0 SOUT1 GND GND VCC Ordering Information(1) 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 /Q3 Q3 VCC /Q2 Q2 VCC /Q1 Q1 VCC /Q0 Q0 GND GND VREF-AC0 /IN0 VT0 IN0 SIN0 SIN1 GND GND VCC VREF_AC2 /IN2 VT2 IN2 CONFIG VCC LOAD /IN1 VT1 IN1 VREF_AC1 SY58040U SY58040UMI Package Operating Type Range MLF-44 Industrial Package Marking Lead Finish SY58040U Sn-Pb SY58040UMITR(2) MLF-44 Industrial SY58040U Sn-Pb SY58040UMY MLF-44 Industrial SY58040U with “Y” designator Pb-free SY58040UMYTR(2) MLF-44 Industrial SY58040U with “Y” designator Pb-free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 44-Pin MLF™ (MLF-44) PIN DESCRIPTION Pin Number Pin Name 17, 15, 10, 8, 4, 2, 41, 39 IN0, /IN0 IN1, /IN1 IN2, /IN2 IN3, /IN3 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details. 16, 9, 3, 40 VT0, VT1 VT2, VT3 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. 14, 11, 1, 42 VRef_AC0 VRef_AC1 VRef_AC2 VRef_AC3 Reference Voltage: This output biases to VCC–1.2V. It is used when AC coupling the inputs. Connect VRef-AC output pin to the VT input pin. Bypass each VRef-AC pin with a 0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section for more details. 18 19 SIN0 SIN1 These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. 38 37 SOUT0 SOUT1 These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs are internally connected to a 25kΩ pullup resistor and will default to a logic HIGH state if left open. 5 7 CONF, LOAD These single-ended TTL/CMOS compatible inputs control the transfer of the addresses to the internal multiplexers. See “Address Tables” and “Timing Diagram” sections for more details. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. Configuration Sequence 1. Load: Loads configuration into buffer, while Configuration Buffer holds existing switch configuration. 2. Configuration: Loads new configuration into the Configuration Buffer and updates switch configuration. Buffer Mode The SY58040U defaults to buffer mode (IN-to-Q) if the load and configuration control signals are floating. 23, 24, 26, 27, 29, 30 32, 33 Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, 6, 22, 25, 28, 31, 34 VCC 12, 13, 20, 21, GND, 35, 36, 43, 44 Exposed pad Differential Outputs: These CML output pairs are the outputs of the device. Please refer to the truth table below for details. Unused output pairs may be left open. Each output is designed to drive 400mV into 100Ω across the pair, or 50Ω to VCC. Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to each VCC pin. Ground. GND and EPad must both be connected to most negative potential of chip ground. M9999-072904 [email protected] or (408) 955-1690 3 SY58040U Micrel Absolute Maximum Ratings(1) Operating Ratings(2) Power Supply Voltage (VCC ) ...................... –0.5V to +4.0V Input Voltage (VIN) ......................................... –0.5V to VCC CML Output Voltage (VOUT) ......... VCC –0.5V to VCC +5.0V Termination Current(3) Source or sink current on VT pin ........................ ±100mA Input Current(3) Source or sink current on IN, /IN .......................... ±50mA VREF-AC Current(3) Source or sink current on IN, /IN ............................ ±2mA Lead Temperature (soldering, 10 sec.) ..................... 265°C Storage Temperature Range (TS ) ........... –65°C to +150°C Power Supply Voltage (VCC) ................. +2.375V to +3.60V Ambient Temperature Range (TA) ............. –40°C to +85°C Package Thermal Resistance(4) MLF™ (θJA) Still-Air ............................................................. 23°C/W MLF™ (ψJB) Junction-to-board ............................................ 12°C/W DC ELECTRICAL CHARACTERISTICS(5) TA= –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VCC Power Supply Voltage VCC = 2.5V. 2.375 2.5 2.625 V VCC = 3.3V. 3.0 3.3 3.6 V 225 300 mA ICC Power Supply Current RIN Input Resistance (IN-to-VT, /IN-to-VT) 40 50 60 Ω RDIFF_IN Differential Input Resistance (IN-to-/IN) 80 100 120 Ω VIH Input HIGH Voltage (IN-to-/IN) VCC–1.6 VCC V VIL Input LOW Voltage (IN-to-/IN) 0 VIH–0.1 V VIN Input Voltage Swing (IN-to-/IN) See Figure 1a. 0.1 1.7 V VDIFF_IN Differential Input Voltage Swing |IN – /IN| See Figure 1b. 0.2 VT_IN IN to VT (IN-to-/IN) VREF-AC Output Reference Voltage No load, max. VCC. Includes current from internal 50Ω pull-up on each output. Note 6 V 1.28 VCC–1.3 VCC–1.2 VCC–1.1 V V Notes: 1. Permanent device damage may occur if ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability, use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. θJA uses 4-layer in still-air number, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIH (min), not lower than 1.2V. M9999-072904 [email protected] or (408) 955-1690 4 SY58040U Micrel CML OUTPUT DC ELECTRICAL CHARACTERISTICS(7) VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C; RL = 100Ω across each output pair, unless otherwise stated. Symbol Parameter Condition Min Typ VOH Output HIGH Voltage Q, /Q VOUT Output Differential Swing Q, /Q See Figure 1a. 325 400 mV VDIFF_OUT Differential Output Voltage Swing Q, /Q See Figure 1b. 650 800 mV ROUT Output Source Impedance 40 50 60 Ω Min Typ Max Units VCC V 0.8 V 30 µA VCC–0.040 VCC–0.010 Max Units VCC V LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(7) VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C, unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current Condition 2.0 –125 VIL = 0V. –300 Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. M9999-072904 [email protected] or (408) 955-1690 5 µA SY58040U Micrel AC ELECTRICAL CHARACTERISTICS(8) VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C, RL = 100Ω across each output pair, unless otherwise stated. Symbol Parameter Condition fMAX Maximum Operating Frequency Min NRZ data VOUT ≥ 200mV tpd Differential Propagation Delay IN-to-Q Typ 5 Clock 3 150 Differential Propagation Delay Temperature Coefficient tS Set-Up Time tH tSKEW tJITTER 225 GHz 350 ps 500 ps 225 fs/°C SIN-to-LOAD 800 ps SOUT-to-LOAD 800 ps LOAD-to-CONFIG 800 ps CONFIG-to-LOAD 950 ps Hold Time LOAD-to-SIN, LOAD-to-SOUT 800 ps Output-to-Output Skew Note 9 25 ps Part-to-Part Skew Note 10 150 ps Data Random Jitter (RJ) Note 11 1 psrms Deterministic Jitter (DJ) Note 12 10 pspp Cycle-to-Cycle Jitter Note 13 1 psrms Total Jitter (TJ) Note 14 10 pspp Crosstalk-induced Jitter Note 15 0.7 psrms 60 ps Clock t r, t f Units Gbps CONFIG-to-Q ∆tpd Tempco Max Output Rise/Fall Time At full output swing, 20% to 80%. 20 40 Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Output-to-output skew is measured between two different outputs under identical input transitions. 10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs 11. Random jitter is measured with a K28.7 character pattern, measured at <fMAX. 12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 223–1 PRBS pattern. 13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 14. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 15. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs. M9999-072904 [email protected] or (408) 955-1690 6 SY58040U Micrel TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, GND = 0, VIN = 100mV, TA = 25°C, unless otherwise stated. WITHIN DEVICE SKEW (ps) OUTPUT AMPLITUDE (mV) 440 420 400 380 360 340 320 0 2000 4000 FREQUENCY (MHz) M9999-072904 [email protected] or (408) 955-1690 6000 20 18 16 14 12 Within-Device Skew vs. Temperature (Referenced to Q0) Q0 Q1 10 8 6 4 2 0 -40 -20 Q2 0 20 Q3 40 60 80 100 TEMPERATURE (°C) 7 Propagation Delay vs. Temperature 270 PROPAGATION DELAY (ps) Output Amplitude vs. Frequency 265 260 255 250 245 F = 200MHz 240 235 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) SY58040U Micrel FUNCTIONAL CHARACTERISTICS VCC = 3.3V, GND = 0, VIN = 100mV, TA = 25°C, unless otherwise stated. 622MHz Output Output Swing (100mV/div.) Output Swing (100mV/div.) 200MHz Output TIME (100ps/div.) TIME (200ps/div.) Output Swing (200mV/div.) 5Gbps Output (Q – /Q) TIME (50ps/div.) M9999-072904 [email protected] or (408) 955-1690 8 SY58040U Micrel SINGLE-ENDED AND DIFFERENTIAL SWINGS VDIFF_IN, VDIFF_OUT 800mV (Typ.) VIN, VOUT 400mV (Typ.) Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing INPUT AND OUTPUT STAGES VCC VCC VCC 50Ω 50Ω 50Ω ZO = 50Ω /Q 50Ω ZO = 50Ω /Q 100Ω IN Q Q ZO = 50Ω 50Ω VT GND 100mA ZO = 50Ω DC bias per application 100mA 50Ω /IN Figure 2a. Simplified Differential Input Stage M9999-072904 [email protected] or (408) 955-1690 GND GND Figure 2b. CML DC-Coupled (100Ω Termination) 9 Figure 2c. CML AC-Coupled (50Ω Termination) SY58040U Micrel INPUT INTERFACE APPLICATIONS VCC VCC VCC IN IN LVPECL VCC GND IN LVPECL /IN /IN SY58040U 0.01µF /IN Rpd VT SY58040U Rpd SY58040U VCC GND NC VT VREF-AC Rpd CML VREF-AC GND For VCC = 3.3V, Rpd = 50Ω. For VCC = 2.5V, Rpd = 39Ω. Figure 3a. LVPECL Interface (DC-Coupled) GND 0.01µF For 3.3V, Rpd = 100Ω. For 2.5V, Rpd = 50Ω. NC VT NC VREF-AC Option: May connect VT to VCC. Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled) VCC VCC IN CML IN /IN SY58040U LVDS /IN GND VCC SY58040U VT VREF-AC 0.01µF Figure 3d. CML Interface (AC-Coupled) GND NC VT NC VREF-AC Figure 3e. LVDS Interface RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY58040U Ultra Precision 4×4 CML Crosspoint Switch with Internal Input/Output Termination http://www.micrel.com/product-info/products/sy58040u.shtml MLF™ Application Note www.amkor.com/products/notes_paper/MLF_AppNote.pdf New Products and Applications www.micrel.com/product-info/products/solutions.shtml HBW Solutions M9999-072904 [email protected] or (408) 955-1690 10 SY58040U Micrel 44 LEAD MicroLeadFrame™ (MLF-44) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 44-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2004 Micrel, Incorporated. M9999-072904 [email protected] or (408) 955-1690 11