SY89859U Precision Low-Power 8:1 MUX with Internal Termination and 1:2 LVPECL Fanout Buffer General Description The SY89859U is a low jitter, low-power, high-speed 8:1 multiplexer with a 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. The SY89859U distributes clock frequencies from DC to >2.5GHz, and data rates to 2.5Gbps guaranteed over temperature and voltage. The SY89859U differential input includes Micrel’s unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV (200mVpp) without level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K-compatible LVPECL with extremely fast rise/fall time guaranteed to be less than 180ps. The SY89859U features a patent-pending isolation design that significantly improves on channel-tochannel crosstalk-induced jitter performance. The SY89859U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89859U is part of Micrel’s high-speed, Precision Edge® product line. All support documentation can be found on Micrel’s web site at: www.micrel.com. Precision Edge® Features • Selects between 1 of 8 inputs, and provides 2 precision, low skew 100K-compatible LVPECL output copies • Low power: 150mW typ. (2.5V) • Guaranteed AC performance over temperature and voltage: – DC to >2.5Gbps – DC to >2.5GHz – <690ps propagation delay – <180ps tr/tf time – <20ps skew (output-to-output) • Unique, patent-pending channel-to-channel isolation design provides superior crosstalk performance • Ultra-low jitter design: – <1psRMS random jitter – <10psPP deterministic jitter – <10psPP total jitter (clock) – <1psRMS cycle-to-cycle jitter – <0.7psRMS crosstalk-induced jitter • Unique, patented input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) • Power supply 2.5V ±5% or 3.3V ±10% • –40°C to +85°C industrial temperature range • Available in 44-pin (7mm x 7mm) MLF® package Applications • • • • Data communication systems All SONET/SDH data/clock applications All Fibre Channel applications All Gigabit Ethernet applications Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com February 2007 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U Functional Block Diagram February 2007 2 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY89859UMG MLF-44 Industrial SY89859U with Pb-Free bar-line indicator NiPdAu Pb-Free SY89859UMGTR(2) MLF-44 Industrial SY89859U with Pb-Free bar-line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. Pin Configuration 44-Pin MLF® (MLF-44) Truth Table February 2007 SEL2 SEL1 L L L L L H SEL0 Q /Q L IN0 /IN0 H IN1 /IN1 L IN2 /IN2 L H H IN3 /IN3 H L L IN4 /IN4 H L H IN5 /IN5 H H L IN6 /IN6 H H H IN7 /IN7 3 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U Pin Description Pin Number Pin Name 20, 18 16, 14 13, 11 9, 7 5, 3 1, 43 42, 40 38, 36 IN0, /IN0 IN1, /IN1 IN2, /IN2 IN3, /IN3 IN4, /IN4 IN5, /IN5 IN6, /IN6 IN7, /IN7 Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details. 19, 15 12, 8 4, 44 41, 37 VT0, VT1 VT2, VT3 VT4, VT5 VT6, VT7 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. For a CML or LVDS inputs, the VT pin is left floating. 17 10 2 39 VREF-AC0 VREF-AC1 VREF-AC2 VREF-AC3 Reference Voltage: These outputs bias to VCC–1.2V. They are used when AC coupling the inputs (IN, /IN). For AC-coupled applications, connect VREF-AC to the VT pin and bypass with a 0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section for more details. 21 22 35 SEL0 SEL1 SEL2 The single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. The threshold voltage is VTH = VCC/2. 24, 27, 29, 32 VCC Positive Power Supply. Bypass with 0.1µF||0.01µF low ESR capacitors and place as close to each VCC pin as possible. 25, 26 30, 31 Q0, /Q0 Q1, /Q1 Differential Outputs: These 100K-compatible LVPECL output pairs are the outputs of the device. Unused output pairs may be left open. Each output is designed to drive 800mV into 50Ω terminated to VCC–2V. 23, 28, 33 GND Exposed Pad Ground. GND and exposed pad must both be connected to the same ground plane. February 2007 Pin Function 4 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .......................... –0.5V to +4.0V Input Voltage SEL0, SEL1, SEL2 .......................... –0.5V to VCC IN0, /IN0, IN1, /IN1,…/IN7, /IN7 ...... –0.5V to VCC LVPECL Output Current (IOUT) Continuous................................................±50mA Surge ......................................................±100mA Termination Current Source or sink current VT0, VT1, VT2,…VT7.............................±100mA Input Current Source or sink current IN0, /IN0, IN1, /IN1,…IN7, /IN7 ................±50mA VREF Output Current VREF-AC0, VREF-AC1…, VREF-AC3.......±2mA Lead Temperature (soldering, 20 sec.) .......... +260°C Storage Temperature (Ts) ................. –65°C to 150°C Supply Voltage (VCC).................. +2.375V to +2.625V .................................................+3.0V to +3.6V Ambient Temperature (TA)................ –40°C to +85°C Package Thermal Resistance(3) MLF® (θJA) Still-Air ................................................ 24°C/W MLF® (ψJB) Junction-to-Board ............................... 12°C/W DC Electrical Characteristics(4) TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VCC Power Supply ICC Power Supply Current Condition Min Typ Max 2.375 2.5 2.625 V 3.0 3.3 3.6 V 60 85 mA No load, max. VCC Units RIN Input Resistance (IN-to-VT) 45 50 55 Ω RDIFF_IN Differential Input Resistance (IN-to-/IN) 90 100 110 Ω VIH Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) VCC–1.2 VCC V 0 VIH–0.1 V 0.1 1.7 V VIL VIN Input Voltage Swing (IN, /IN) See Figure 1a. VDIFF_IN Differential Input Voltage Swing |IN-to-/IN| See Figure 1b. VT_IN IN-to-VT (IN, /IN) VREF-AC Output Reference Voltage 0.2 VCC–1.3 V VCC–1.2 1.28 V VCC–1.1 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and ΨJB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. February 2007 5 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U 100K LVPECL Output DC Electrical Characteristics(6) VCC = +2.5V ±5% or 3.3V ±10%, RL = 50Ω to VCC–2V; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage (Q, /Q) VCC–1.145 VCC–0.895 V VOL Output LOW Voltage (Q, /Q) VCC–1.945 VCC–1.695 V VOUT Output Differential Swing See Figure 1a. 550 800 mV VDIFF_OUT Differential Output Voltage Swing See Figure 1b. 1100 1600 mV LVTTL/CMOS DC Electrical Characteristics(6) VCC = +2.5V ±5% or 3.3V ±10%; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage Condition Min Typ Max 2.0 IIH Input HIGH Current IIH @ VIN = VCC –125 IIL Input LOW Current IIL @ VIN = 0.5V –300 Units V 0.8 V 40 µA µA Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. February 2007 6 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U AC Electrical Characteristics(7) VCC = +2.5V ±5% or 3.3V ±10%; VIN ≥100mV (200mVpp); RL = 50Ω to VCC–2V; TA = –40°C to +85°C, unless otherwise stated. Symbol fMAX Parameter Condition Min Maximum Operating Frequency Typ Max 2.5 Units Gbps 2.5 3.5 GHz IN-to-Q 360 475 640 ps SEL-to-Q 200 600 850 ps Differential Propagation Delay tpd tpd Tempco tSKEW Differential Propagation Delay Temperature Coefficient IN-to-Q 300 SEL-to-Q 400 Output-to-Output Skew Note 8 Part-to-Part Skew Note 9 5 fs/oC 20 ps 200 ps Data tJITTER tr, tf Random Jitter (RJ) Note 10 1 psRMS Deterministic Jitter (DJ) Note 11 10 psPP Cycle-to-Cycle Jitter Note 12 1 psRMS Total Jitter (TJ) Note 13 10 psPP Adjacent Channel Crosstalk-induced Jitter Note 14 0.7 psRMS 180 ps Clock Output Rise/Fall Time (20% to 80%) At full output swing. 50 110 Notes: 7. High-frequency AC-parameters are guaranteed by design and characterization. 8. Output-to-output skew is measured between two different outputs under identical input transitions. 9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. Random jitter is measured with a K28.7 character pattern, measured at <fMAX. 23 11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 –1 PRBS pattern. 12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 12 13. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 14. Crosstalk-induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying two similar, differential clock frequencies that are asynchronous with respect to each other at the inputs. Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing February 2007 Figure 1b. Differential Voltage Swing 7 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U Typical Operating Characteristics VCC = 3.3V, GND = 0, VIN = 100mV (200mVpp), RL = 50Ω to VCC–2V; TA = 25°C, unless otherwise stated. February 2007 8 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U Functional Characteristics VCC = 3.3V, GND = 0, VIN = 100mV (200mVpp), RL = 50Ω to VCC–2V; TA = 25°C, unless otherwise stated. February 2007 9 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U Input and Output Stages Figure 2a. Simplified Differential Input Stage Figure 2b. Simplified LVPECL Output Stage Input Interface Applications Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3d. CML Interface (AC-Coupled) Figure 3e. LVDS Interface February 2007 10 Figure 3c. CML Interface (DC-Coupled) M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U LVPECL Output Interface Applications LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing which result in low EMI. LVPECL is ideal for driving 50Ω- and 100Ω-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output including: Parallel TerminationThevenin Equivalent, Parallel Termination (3Resistor), and AC-Coupled Termination. Unused output pairs may be left floating. However, singleended outputs must be terminated, or balanced. Figure 4b. Parallel Termination (3-Resistor) Figure 4a. Parallel Thevenin-Equivalent Termination Note: Note: For 2.5V system, R1 = 250Ω, R2 = 62.5Ω. For 2.5V system, Rb = 19Ω. Related Product and Support Documentation Part Number Function Data Sheet Link SY58037U Ultra Precision 8:1 MUX with Internal Termination and 1:2 CML Fanout Buffer http://www.micrel.com/product-info/products/sy58037u.shtml SY58038U Ultra Precision 8:1 MUX with Internal Termination and 1:2 LVPECL Fanout Buffer http://www.micrel.com/product-info/products/sy58038u.shtml SY58039U Ultra Precision 8:1 MUX with Internal Termination and 1:2 400mV LVPECL Fanout Buffer http://www.micrel.com/product-info/products/sy58039u.shtml HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml ® MLF Application Note February 2007 www.amkor.com/products/notes_papers/MLFAppNote.pdf 11 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U Package Information 44-Pin MLF® (MLF-44) PCB Thermal Consideration for 44-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: February 2007 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management. 12 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89859U MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. February 2007 13 M9999-022007-B [email protected] or (408) 955-1690