FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting General Description Features The Fairchild Universal Bus Switch FSTUD16450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The FSTUD16450 is designed to allow “customer” configuration control of the enable connections. The device is organized as either a 4-bit, 5-bit, 10-bit or 20-bit bus switch. 8-bit and 16-bit configurations are also achievable (see Functional Description). The device's bit configuration is chosen through select pin logic. (see Truth Table). When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN. ■ Undershoot hardened to −2V (A and B Ports) ■ Voltage level shifting The A and B Ports are “undershoot hardened” with UHC® protection to support an extended range to 2.0V below ground. Fairchild's integrated “Undershoot Hardened Circuit” (UHC) senses undershoot at the I/Os, and responds by preventing voltage differentials from developing and turning on the switch. Another key device feature is the addition of a level shifting select pin, “S2”. When S2 is LOW, the device behaves as a standard N-MOS switch. When S2 is HIGH, a diode to VCC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs. ■ 4Ω switch connection between two ports ■ Minimal propagation delay through the switch ■ Low lCC ■ Zero bounce in flow-through mode ■ Control inputs compatible with TTL level ■ See Applications Note AN-5008 for details ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Applications Note Select pins S0, S1, S2 are intended to be used as static user configurable control pins. The AC performance of these pins has not been characterized or tested. Switching of these select pins during system operation may temporarily disrupt output logic states and/or enable pin controls. Ordering Code: Order Number FSTUD16450GX (Note 1) FSTUD16450MTD Package Number BGA54A (Preliminary) MTD56 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1: BGA package available in Tape and Reel only. UHC® is a registered trademark of Fairchild Semiconductor Corporation. © 2001 Fairchild Semiconductor Corporation DS500391 www.fairchildsemi.com FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting January 2001 Revised October 2006 FSTUD16450 Connection Diagrams Pin Descriptions Pin Assignment for TSSOP Pin Name Description OE1, OE2 Bus Switch Enables 1A, 2A Bus A 1B, 2B Bus B S0 , S1 Bit Configuration Enables S2 Level Shifting Diode Enable NC No Connect FBGA Pin Assignments Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com 2 1 2 3 4 5 6 A 1A3 1A2 OE1 OE2 1B2 1B3 B 1A5 1A4 1A1 1B1 1B4 1B5 C 1A7 1A6 GND OE5 1B6 1B7 D 1A9 1A8 GND VCC 1B8 1B9 E 2A1 1A10 S0 VCC 1B10 2B1 F 2A3 2A2 S1 S2 2B2 2B3 G 2A5 2A4 VCC GND 2B4 2B5 H 2A7 2A6 2A10 2B10 2B6 2B7 J 2A9 2A8 OE4 OE3 2B8 2B9 FSTUD16450 Logic Diagrams 20-Bit Configuration (Configuration 1) 10-Bit Configuration (Configuration 2) 5-Bit Configuration (Configuration 3) 4-Bit Configuration (Configuration 4) 3 www.fairchildsemi.com FSTUD16450 Functional Description The device can also be configured as an 8 and 16-bit device by grounding the unused pins in Configurations 2 and 1 respectively. The 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and tying the remaining enable pin (OE) HIGH. Truth Tables (X = VCC or GND) (see Functional Description) Select Pin S2 Mode L Std. NMOS Switch H Level Shifting Diode Enabled S0 = S1 = L Configuration 1 20-Bit Configuration Inputs Inputs/Outputs OE1 OE2 OE3 OE4 OE5 L X X X X 1A1-10 = 1B1-10, 2A1-10 = 2B1-10 H X X X X Z S0 = L, S1 = H Configuration 2 10-Bit Configuration Inputs Inputs/Outputs OE1 OE2 OE3 OE4 OE5 1A1-10 = 1B1-10 2A1-10 = 2B1-10 L X X L X 1AX = 1BX 2AX = 2BX L X X H X 1AX = 1BX Z H X X L X Z 2AX = 2BX H X X H X Z Z S0 = H, S1 = L Configuration 3 5-Bit Configuration Inputs Inputs/Outputs OE1 OE2 OE3 OE4 OE5 1A1-5, 1B1-5 1A6-10, 1B6-10 2A1-5, 2B1-5 2A6-10, 2B6-10 L L L L X 1Ax = 1Bx 1Ay = 1By 2Ax = 2Bx 2Ay = 2By L L L H X 1Ax = 1Bx 1Ay = 1By 2Ax = 2Bx Z L L H L X 1Ax = 1Bx 1Ay = 1By Z 2Ay = 2By L L H H X 1Ax = 1Bx 1Ay = 1By Z Z L H L L X 1Ax = 1Bx Z 2Ax = 2Bx 2Ay = 2By L H L H X 1Ax = 1Bx Z 2Ax = 2Bx Z L H H L X 1Ax = 1Bx Z Z 2Ay = 2By L H H H X 1Ax = 1Bx Z Z Z H L L L X Z 1Ay = 1By 2Ax = 2Bx 2Ay = 2By H L L H X Z 1Ay = 1By 2Ax = 2Bx Z H L H L X Z 1Ay = 1By Z 2Ay = 2By H L H H X Z 1Ay = 1By Z Z H H L L X Z Z 2Ax = 2Bx 2Ay = 2By H H L H X Z Z 2Ax = 2Bx Z H H H L X Z Z Z 2Ay = 2By H H H H X Z Z Z Z www.fairchildsemi.com 4 (Continued) Configuration 4 S0 = S1 = H 4-Bit Configuration Inputs Inputs/Outputs 1A9-10, 2B9-10 OE1 OE2 OE3 OE4 OE5 1A1-4, 1B1-4 1A5-8, 1B5-8 2A3-6, 2B3-6 2A7-10, 2B7-10 L L L L L 1Ax = 1Bx 1Ay = 1By 2Ax = 2Bx 2Ay = 2By L L L L H 1Ax = 1Bx 1Ay = 1By 2Ax = 2Bx 2Ay = 2By Z 1Az = 1Bz 2Az = 2Bz 2A1-2, 2B1-2 1Az = 1Bz 2Az = 2Bz L L L H L 1Ax = 1Bx 1Ay = 1By 2Ax = 2Bx Z L L L H H 1Ax = 1Bx 1Ay = 1By 2Ax = 2Bx Z Z 1Az = 1Bz 2Az = 2Bz L L H L L 1Ax = 1Bx 1Ay = 1By Z 2Ay = 2By L L H L H 1Ax = 1Bx 1Ay = 1By Z 2Ay = 2By Z 1Az = 1Bz 2Az = 2Bz L L H H L 1Ax = 1Bx 1Ay = 1By Z Z L L H H H 1Ax = 1Bx 1Ay = 1By Z Z Z 1Az = 1Bz 2Az = 2Bz L H L L L 1Ax = 1Bx Z 2Ax = 2Bx 2Ay = 2By L H L L H 1Ax = 1Bx Z 2Ax = 2Bx 2Ay = 2By Z 1Az = 1Bz 2Az = 2Bz L H L H L 1Ax = 1Bx Z 2Ax = 2Bx Z L H L H H 1Ax = 1Bx Z 2Ax = 2Bx Z Z 1Az = 1Bz 2Az = 2Bz L H H L L 1Ax = 1Bx Z Z 2Ay = 2By L H H L H 1Ax = 1Bx Z Z 2Ay = 2By Z 1Az = 1Bz 2Az = 2Bz L H H H L 1Ax = 1Bx Z Z Z L H H H H 1Ax = 1Bx Z Z Z Z 1Az = 1Bz 2Az = 2Bz H L L L L Z 1Ay = 1By 2Ax = 2Bx 2Ay = 2By H L L L H Z 1Ay = 1By 2Ax = 2Bx 2Ay = 2By Z 1Az = 1Bz 2Az = 2Bz H L L H L Z 1Ay = 1By 2Ax = 2Bx Z H L L H H Z 1Ay = 1By 2Ax = 2Bx Z Z 1Az = 1Bz 2Az = 2Bz H L H L L Z 1Ay = 1By Z 2Ay = 2By H L H L H Z 1Ay = 1By Z 2Ay = 2By Z 1Az = 1Bz 2Az = 2Bz H L H H L Z 1Ay = 1By Z Z H L H H H Z 1Ay = 1By Z Z Z 1Az = 1Bz 2Az = 2Bz H H L L L Z Z 2Ax = 2Bx 2Ay = 2By H H L L H Z Z 2Ax = 2Bx 2Ay = 2By Z 1Az = 1Bz 2Az = 2Bz H H L H L Z Z 2Ax = 2Bx Z H H L H H Z Z 2Ax = 2Bx Z Z 1Az = 1Bz 2Az = 2Bz H H H L L Z Z Z 2Ay = 2By H H H L H Z Z Z 2Ay = 2By Z H H H H L Z Z Z Z 1Az = 1Bz 2Az = 2Bz H H H H H Z Z Z Z Z 5 www.fairchildsemi.com FSTUD16450 Truth Tables FSTUD16450 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC ) −0.5V to +7.0V DC Switch Voltage (VS) (Note 3) −2.0V to +7.0V Recommended Operating Conditions (Note 5) Power Supply Operating (VCC) DC Input Control Pin Voltage 4.0V to 5.5V Input Voltage (VIN) −0.5V to +7.0V (VIN) (Note 4) DC Input Diode Current (lIK) VIN < 0V −50 mA DC Output (IOUT ) Current 0V to 5.5V Output Voltage (VOUT) 0V to 5.5V Free Air Operating Temperature (TA) -40 °C to +85 °C 128 mA +/− 100 mA DC VCC/GND Current (ICC/IGND) −65°C to +150 °C Storage Temperature Range (TSTG) Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: VS is the voltage observed/applied at either the A or B Ports across the switch. Note 4: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 5: Unused control inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics VCC Symbol Parameter (V) VIK Clamp Diode Voltage VIH HIGH Level Input Voltage 4.0-5.5 VIL LOW Level Input Voltage 4.0-5.5 VOH HIGH Level Output Voltage 4.5-5.5 II Input Leakage Current 5.5 IOZ OFF-STATE Leakage Current RON Switch On Resistance 4.5 (Note 7) ICC TA = −40 °C to +85 °C Min Typ (Note 6) −1.2 4.5 2.0 0.8 Units V IIN = −18 mA V IF S2 = HIGH 4.5V ≤ VCC ≤ 5.5V V IF S2 = HIGH 4.5V ≤ VCC ≤ 5.5V S2 = VCC ±1.0 µA 0 ≤ VIN ≤ 5.5V 0 10 µA VIN = 5.5V 5.5 ±1.0 µA 0 ≤ A, B ≤ VCC 4 7 Ω VIN = 0V, IIN = 64 mA, S2 = 0V or VCC 4.5 4 7 Ω VIN = 0V, IIN = 30 mA, S2 = 0V or VCC 4.5 8 12 Ω VIN = 2.4V, IIN = 15 mA, S2 = 0V 4.0 11 20 Ω VIN = 2.4V, IIN = 15 mA, S2 = 0V 4.5 35 50 Ω VIN = 2.4V, IIN = 15 mA, S2 = VCC 3 µA S2 = GND, VIN = VCC or GND, IOUT = 0 10 µA S2 = VCC, OE x = VCC, VIN = VCC or GND, IOUT = 0 1.5 mA S2 = VCC, OE x = GND, VIN = VCC or GND, IOUT = 0 2.5 mA 4.0 mA −2.0 V Quiescent Supply Current Increase in ICC per Input 5.5 VIKU Voltage Undershoot Conditions V See Figure 4 5.5 ∆ ICC Max 5.5 One Input at 3.4V Other Inputs at VCC or GND, S2 = 0V One Input at 3.4V Other Inputs at VCC or GND, S2 = VCC 0.0 mA ≥ IIN ≥ −50 mA OEx = 5.5V Note 6: Typical values are at VCC = 5.0V and T A = +25°C Note 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B) pins. www.fairchildsemi.com 6 TA = −40 °C to +85 °C, Symbol Parameter CL = 50pF, RU = RD = 500Ω VCC = 4.5 – 5.5V Min tPHL, tPLH Propagation Delay Bus-to-Bus (Note 8) tPZH, tPZL Output Enable Time 1.5 Max Units VCC = 4.0V Min Conditions Figure (S2 = 0V) Number Max 0.25 0.25 ns VI = OPEN Figures 2, 3 6.5 7.0 ns VI = 7V for tPZL Figures 2, 3 VI = OPEN for tPZH tPHZ, tPLZ Output Disable Time 1.5 6.7 7.2 VI = 7V for tPLZ ns VI = OPEN for tPHZ tPZH, tPZL Sel (S0, 1) to Output Enable Time 1.5 7.0 7.5 VI = 7V for tPZL ns VI = OPEN for tPZH tPHZ, tPLZ Sel (S0, 1) to Output Disable Time 1.5 7.5 7.7 VI = 7V for tPLZ ns VI = OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). AC Electrical Characteristics: Translating Diode TA = −40 °C to +85 °C, Symbol Parameter CL = 50pF, RU = RD = 500Ω VCC = 4.5 – 5.5V Min tPHL, tPLH Propagation Delay Bus-to-Bus (Note 9) tPZH, tPZL Output Enable Time Units Conditions Figure (S2 = VCC) Number Max 1.5 0.25 ns 10.0 ns VI = OPEN Figures 2, 3 VI = 7V for tPZL Figures 2, 3 VI = OPEN for tPZH tPHZ, tPLZ Output Disable Time 1.5 9.0 ns VI = 7V for tPLZ Figures 2, 3 VI = OPEN for tPHZ tPZH, tPZL Sel (S0, 1) to Output Enable Time 1.5 11.0 ns VI = 7V for tPZL Figures 2, 3 VI = OPEN for tPZH tPHZ, tPLZ Sel (S0, 1) to Output Disable Time 1.5 10.0 ns VI = 7V for tPLZ Figures 2, 3 VI = OPEN for tPHZ Note 9: This parameter is guaranteed by design but is not tested. This bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). Capacitance Symbol (Note 10) Parameter Typ Max Units Conditions CIN Control Pin Input Capacitance 4 pF VCC = 5.0V, VIN = 0V CI/O Input/Output Capacitance “OFF State” 8 pF VCC, OE = 5.0V, VIN = 0V Note 10: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested. 7 www.fairchildsemi.com FSTUD16450 AC Electrical Characteristics FSTUD16450 Undershoot Characteristic (Note 11) Symbol VOUTU Parameter Output Voltage During Undershoot Min Typ 2.5 VOH − 0.3 Max Units V S2 = 0V, Figure 1 Conditions TBD TBD V S2 = V CC Note 11: This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event. FIGURE 1. Device Test Conditions Parameter Value VIN see Waveform V R1 = R2 100K Ω VTRI 11.0 V VCC 5.5 V Transient Input Voltage (VIN) Waveform Units AC Loading and Waveforms Note: Input driven by 50Ω source terminated in 50Ω Note: CL includes load and stray capacitance Note: Input Frequency = 1.0 MHz, tW = 500 ns FIGURE 2. AC Test Circuit FIGURE 3. AC Waveforms www.fairchildsemi.com 8 FSTUD16450 FIGURE 4. 9 www.fairchildsemi.com FSTUD16450 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary www.fairchildsemi.com 10 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting Physical Dimensions inches (millimeters) unless otherwise noted (Continued)