Preliminary Revised August 2001 FSTUD32211 40/48-Bit Bus Switch with -2V Undershoot Protection and Level Shifting (Preliminary) General Description Features The Fairchild Switch FSTUD32211 provides up to 48-bits of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. A diode to VCC has been integrated into the circuit to allow for level shifting between 5V inputs and 3.3V outputs. ■ Undershoot protected to −2V (A and B Ports) The device can be organized as four 12-bit, two 24-bit, or one 48-bit bus switch. When routed as a 40-bit bus switch, the device can be organized as four 10-bit, two 20-bit or one 40-bit bus switch. When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, the switch is ON and Port 2A is connected to Port 2B. When OE3 is LOW, the switch is ON and Port 3A is connected to Port 3B. When OE4 is LOW, the switch is ON and Port 4A is connected to Port 4B. When OE1, OE2, OE3, or OE4 are HIGH, a high impedance state exists between the A and B Ports. The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchild’s integrated Undershoot Hardened Circuit (UHC) senses undershoot at the I/O’s, and responds by preventing voltage differentials from developing and turning on the switch. ■ Control inputs compatible with TTL level ■ Voltage level shifting ■ 4Ω switch connection between two ports ■ Minimal propagation delay through the switch ■ Low lCC ■ Zero bounce in flow-through mode ■ See Applications Notes AN-5008 and AN-5021 for UHC details ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number FSTUD32211GX (Note 1) Package Number BGA114A (Preliminary) Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] Note 1: BGA package available in Tape and Reel only. © 2001 Fairchild Semiconductor Corporation DS500537 www.fairchildsemi.com FSTUD32211 40/48-Bit Bus Switch with -2V Undershoot Protection and Level Shifting (Preliminary) February 2001 FSTUD32211 Preliminary Logic Diagram Pin Descriptions Pin Name Description OE1, OE2, OE3, OE4 Bus Switch Enables 1A, 2A, 3A, 4A Bus A 1B, 2B, 3B, 4B Bus B NC No Connect FBGA Pin Assignments (40-Bit Routing) Connection Diagram 1 2 3 4 5 6 A 1A2 1A1 NC OE2 1B1 1B2 B 1A4 1A3 GND OE1 1B3 1B4 C 1A6 1A5 GND GND 1B5 1B6 D 1A8 1A7 GND GND 1B7 1B8 E 1A10 1A9 VCC VCC 1B9 1B10 F 2A2 2A1 VCC VCC 2B1 2B2 G 2A4 2A3 VCC GND 2B3 2B4 H 2A6 2A5 GND GND 2B5 2B6 J 2A8 2A7 2A9 2B9 2B7 2B8 K 2A10 3A10 GND GND 3B10 2B10 L 3A9 3A8 GND GND 3B8 3B9 M 3A7 3A6 GND VCC 3B6 3B7 N 3A5 3A4 VCC VCC 3B4 3B5 P 3A3 3A2 VCC VCC 3B2 3B3 R 3A1 4A10 GND GND 4B10 3B1 T 4A9 4A8 GND GND 4B8 4B9 U 4A7 4A6 GND 4B1 4B6 4B7 V 4A5 4A4 4A1 OE4 4B4 4B5 NC 4B2 4B3 W 4A3 4A2 OE3 Truth Tables Inputs OE2 OE1 (Top Thru View) Inputs/Outputs 2 2A, 2B L L 1A = 1B 2A = 2B L H 1A = 1B Z H L Z 2A = 2B H H Z Z OE3 OE4 3A, 3B 4A, 4B L L 3A = 3B 4A = 4B Inputs www.fairchildsemi.com 1A, 1B Inputs/Outputs L H 3A = 3B Z H L Z 4A = 4B H H Z Z Preliminary FSTUD32211 Connection Diagram Pin Descriptions Pin Name Description OE1, OE2, OE3, OE4 Bus Switch Enables 1A, 2A, 3A, 4A Bus A 1B, 2B, 3B, 4B Bus B NC No Connect FBGA Pin Assignments (48-Bit Routing) (Top Thru View) 1 2 3 4 5 6 A 1A2 1A1 NC OE2 1B1 1B2 B 1A4 1A3 1A7 OE1 1B3 1B4 C 1A6 1A5 GND 1B7 1B5 1B6 D 1A10 1A9 1A8 1B8 1B9 1B10 E 1A12 1A11 2A1 2B1 1B11 1B12 F 2A4 2A3 2A2 2B2 2B3 2B4 G 2A6 2A5 VCC GND 2B5 2B6 H 2A8 2A7 GND GND 2B7 2B8 J 2A10 2A9 2A11 2B11 2B9 2B10 K 2A12 3A12 GND GND 3B12 2B12 L 3A11 3A10 GND GND 3B10 3B11 M 3A9 3A8 GND VCC 3B8 3B9 N 3A7 3A6 3A2 3B2 3B6 3B7 P 3A5 3A4 3A1 3B1 3B4 3B5 R 3A3 4A12 4A8 4B8 4B12 3B3 T 4A11 4A10 4A7 4B7 4B10 4B11 U 4A9 4A6 GND 4B1 4B6 4B9 V 4A5 4A4 4A1 OE4 4B4 4B5 W 4A3 4A2 OE3 NC 4B2 4B3 Truth Tables Inputs Inputs/Outputs OE2 OE1 2A, 2B L L 1A = 1B 2A = 2B L H 1A = 1B Z H L Z 2A = 2B H H Z Z OE3 OE4 3A, 3B 4A, 4B L L 3A = 3B 4A = 4B Inputs 3 1A, 1B Inputs/Outputs L H 3A = 3B Z H L Z 4A = 4B H H Z Z www.fairchildsemi.com FSTUD32211 Preliminary Absolute Maximum Ratings(Note 2) Recommended Operating Conditions (Note 5) 0.5V to +7.0V Supply Voltage (VCC) −2V to +7.0V DC Switch Voltage (VS) (Note 3) Power Supply Operating (VCC) −0.5V to +7.0V DC Input Control Pin Voltage (VIN)(Note 4) 0V to 5.5V 0V to 5.5V DC Input Diode Current (lIK) VIN < 0V −50 mA Output Voltage (VOUT) DC Output (IOUT) 128 mA Input Rise and Fall Time (tr, tf) +/− 100 mA DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG) 4.5V to 5.5V Input Voltage (VIN) Switch Control Input −65°C to +150 °C 0 ns/V to 5 ns/V Switch I/O 0 ns/V to DC -40°C to +85°C Free Air Operating Temperature (TA) Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: VS is the voltage observed/applied at either A or B Ports across the switch. Note 4: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 5: Unused control inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol Parameter VCC (V) VIK Clamp Diode Voltage VIH HIGH Level Input Voltage 4.5 - 5.5 VIL LOW Level Input Voltage 4.5 - 5.5 VOH HIGH Level 4.5 - 5.5 II Input Leakage Current TA = −40 °C to +85 °C Min Typ (Note 6) Max −1.2 4.5 2.0 Units V Conditions IIN = −18 mA V 0.8 V 5.5 ±1.0 µA 0 10 µA VIN = 5.5V 5.5 ±1.0 µA 0 ≤ A, B ≤ VCC See Figure 4 V 0 ≤ VIN ≤ 5.5V IOZ OFF-STATE Leakage Current RON Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64 mA (Note 7) 4.5 4 7 Ω VIN = 0V, IIN = 30 mA 4.5 35 50 Ω ICC Quiescent Supply Current 1.5 mA 10 µA 5.5 ∆ ICC Increase in ICC per Input 5.5 2.5 mA VIKU Voltage Undershoot 5.5 −2.0 V VIN = 2.4V, IIN = 15 mA OE1 = OE2 = GND VIN = VCC or GND, IOUT = 0 OE1 = OE2 = V CC VIN = VCC or GND, IOUT = 0 One Input at 3.4V Other Inputs at VCC or GND 0.0 mA ≥ IIN ≥ −50 mA OE1,2 = 5.5V Note 6: Typical values are at VCC = 5.0V and T A= +25°C Note 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B) pins. www.fairchildsemi.com 4 Preliminary TA = −40 °C to +85 °C, Symbol CL = 50pF, RU = RD = 500Ω Parameter Units VCC = 4.5 – 5.5V Min tPHL, tPLH Propagation Delay Bus to Bus (Note 8) tPZH, tPZL Output Enable Time Figure Number Conditions Max 1.5 0.25 ns 10.0 ns VI = OPEN Figures 2, 3 VI = 7V for tPZL Figures 2, 3 VI = OPEN for tPZH tPHZ, tPLZ Output Disable Time 1.5 9.0 ns VI = 7V for tPLZ Figures 2, 3 VI = OPEN for tPHZ Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). Capacitance Symbol (Note 9) Parameter Typ Max Units Conditions CIN Control Pin Input Capacitance 3 pF VCC = 5.0V CI/O Input/Output Capacitance 6 pF VCC, OE = 5.0V Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested. Undershoot Characteristic (Note 10) Symbol VOUTU Parameter Min Typ Output Voltage During Undershoot 2.5 VOH - 0.3 Max Units V Conditions Figure 1 Note 10: This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event. FIGURE 1. Device Test Conditions Parameter Value Transient Input Voltage (VIN) Waveform Units VIN see Waveforms V R1 = R2 100K Ω VTRI 11.0 V VCC 5.5 V 5 www.fairchildsemi.com FSTUD32211 AC Electrical Characteristics FSTUD32211 Preliminary AC Loading and Waveforms Note: Input driven by 50Ω source terminated in 50Ω Note: CL includes load and stray capacitance Note: Input PRR = 1.0 MHz, tW = 500 ns FIGURE 2. AC Test Circuit FIGURE 3. AC Waveforms www.fairchildsemi.com 6 Preliminary FSTUD32211 Output Voltage HIGH vs. Supply Voltage FIGURE 4. 7 www.fairchildsemi.com FSTUD32211 40/48-Bit Bus Switch with -2V Undershoot Protection and Level Shifting (Preliminary) Preliminary Physical Dimensions inches (millimeters) unless otherwise noted 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Preliminary Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8